3c10754a8d
This patch did the work to use pci related functions provided by DPDK. Change-Id: I263b79f1b42868ef0c1efcf1bc392a4b3a328e93 Signed-off-by: Ziye Yang <ziye.yang@intel.com>
183 lines
6.5 KiB
C
183 lines
6.5 KiB
C
#ifndef __IOAT_IMPL_H__
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#define __IOAT_IMPL_H__
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#include <assert.h>
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#include <pthread.h>
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#include <stdio.h>
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#include <rte_malloc.h>
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#include <rte_config.h>
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#include <rte_atomic.h>
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#include <rte_cycles.h>
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#include "spdk/vtophys.h"
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#include "spdk/pci.h"
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#include "spdk/ioat.h"
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#include "ioat_pci.h"
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/**
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* \file
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*
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* This file describes the functions required to integrate
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* the userspace IOAT driver for a specific implementation. This
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* implementation is specific for DPDK. Users would revise it as
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* necessary for their own particular environment if not using it
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* within the SPDK framework.
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*/
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/**
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* Allocate a pinned, physically contiguous memory buffer with the
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* given size and alignment.
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*/
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static inline void *
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ioat_zmalloc(const char *tag, size_t size, unsigned align, uint64_t *phys_addr)
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{
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void *buf = rte_zmalloc(tag, size, align);
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*phys_addr = rte_malloc_virt2phy(buf);
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return buf;
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}
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/**
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* Free a memory buffer previously allocated with ioat_zmalloc.
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*/
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#define ioat_free(buf) rte_free(buf)
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/**
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* Return the physical address for the specified virtual address.
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*/
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#define ioat_vtophys(buf) vtophys(buf)
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/**
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* Delay us.
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*/
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#define ioat_delay_us(us) rte_delay_us(us)
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/**
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* Assert a condition and panic/abort as desired. Failures of these
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* assertions indicate catastrophic failures within the driver.
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*/
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#define ioat_assert(check) assert(check)
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/**
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* Log or print a message from the driver.
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*/
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#define ioat_printf(chan, fmt, args...) printf(fmt, ##args)
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#ifdef USE_PCIACCESS
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/**
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*
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*/
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#define ioat_pcicfg_read32(handle, var, offset) pci_device_cfg_read_u32(handle, var, offset)
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#define ioat_pcicfg_write32(handle, var, offset) pci_device_cfg_write_u32(handle, var, offset)
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static inline int
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ioat_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr)
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{
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struct pci_device *dev = devhandle;
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uint32_t flags = (read_only ? 0 : PCI_DEV_MAP_FLAG_WRITABLE);
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return pci_device_map_range(dev, dev->regions[bar].base_addr, 4096,
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flags, mapped_addr);
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}
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static inline int
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ioat_pcicfg_unmap_bar(void *devhandle, uint32_t bar, void *addr)
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{
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struct pci_device *dev = devhandle;
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return pci_device_unmap_range(dev, addr, dev->regions[bar].size);
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}
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#else
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/* var should be the pointer */
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#define ioat_pcicfg_read32(handle, var, offset) rte_eal_pci_read_config(handle, var, 4, offset)
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#define ioat_pcicfg_write32(handle, var, offset) rte_eal_pci_write_config(handle, var, 4, offset)
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static inline int
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ioat_pcicfg_map_bar(void *devhandle, uint32_t bar, uint32_t read_only, void **mapped_addr)
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{
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struct rte_pci_device *dev = devhandle;
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*mapped_addr = dev->mem_resource[bar].addr;
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return 0;
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}
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static struct rte_pci_id ioat_driver_id[] = {
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8)},
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{RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9)},
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{ .vendor_id = 0, /* sentinel */ },
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};
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static struct rte_pci_driver ioat_rte_driver = {
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.name = "ioat_driver",
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.devinit = NULL,
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.id_table = ioat_driver_id,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
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};
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static inline int
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ioat_driver_register_dev_init(void *fn_t)
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{
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int rc;
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ioat_rte_driver.devinit = fn_t;
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rte_eal_pci_register(&ioat_rte_driver);
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rc = rte_eal_pci_probe();
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rte_eal_pci_unregister(&ioat_rte_driver);
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return rc;
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}
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#endif
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typedef pthread_mutex_t ioat_mutex_t;
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#define ioat_mutex_lock pthread_mutex_lock
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#define ioat_mutex_unlock pthread_mutex_unlock
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#define IOAT_MUTEX_INITIALIZER PTHREAD_MUTEX_INITIALIZER
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#endif /* __IOAT_IMPL_H__ */
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