460327ea5c
NVMe doesn't require the specific 64-bit MMIO ordering on 32-bit platforms performed in spdk_mmio_read_8(), but it doesn't hurt. We have to pick one of the two possible orderings, so pick the one required by I/OAT. Change-Id: I2b909d64d0c077b797d0f64a11d78d1ecc55eec7 Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef SPDK_MMIO_H
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#define SPDK_MMIO_H
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#include <inttypes.h>
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#ifdef __x86_64__
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#define SPDK_MMIO_64BIT 1 /* Can do atomic 64-bit memory read/write (over PCIe) */
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#else
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#define SPDK_MMIO_64BIT 0
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#endif
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static inline uint32_t
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spdk_mmio_read_4(const volatile uint32_t *addr)
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{
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return *addr;
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}
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static inline void
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spdk_mmio_write_4(volatile uint32_t *addr, uint32_t val)
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{
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*addr = val;
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}
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static inline uint64_t
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spdk_mmio_read_8(volatile uint64_t *addr)
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{
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uint64_t val;
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (SPDK_MMIO_64BIT) {
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val = *addr;
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} else {
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/*
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* Read lower 4 bytes before upper 4 bytes.
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* This particular order is required by I/OAT.
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* If the other order is required, use a pair of spdk_mmio_read_4() calls.
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*/
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val = addr32[0];
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val |= (uint64_t)addr32[1] << 32;
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}
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return val;
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}
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static inline void
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spdk_mmio_write_8(volatile uint64_t *addr, uint64_t val)
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{
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volatile uint32_t *addr32 = (volatile uint32_t *)addr;
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if (SPDK_MMIO_64BIT) {
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*addr = val;
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} else {
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addr32[0] = (uint32_t)val;
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addr32[1] = (uint32_t)(val >> 32);
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}
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}
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#endif
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