dcfbafeb77
Add code to implement the write memory barrier and read/write memory barrier for ARM 64 platforms. Change-Id: I8b63db25ba1f70a729874ca143db13501d976676 Signed-off-by: Barry Spinney <spinney@mellanox.com> Reviewed-on: https://review.gerrithub.io/386534 Reviewed-by: Daniel Verkamp <daniel.verkamp@intel.com> Tested-by: SPDK Automated Test System <sys_sgsw@intel.com> Reviewed-by: Jim Harris <james.r.harris@intel.com> Reviewed-by: Ben Walker <benjamin.walker@intel.com>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* Copyright (c) 2017, IBM Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** \file
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* Memory barriers
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*/
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#ifndef SPDK_BARRIER_H
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#define SPDK_BARRIER_H
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#include "spdk/stdinc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Compiler memory barrier */
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#define spdk_compiler_barrier() __asm volatile("" ::: "memory")
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/** Write memory barrier */
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#ifdef __PPC64__
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#define spdk_wmb() __asm volatile("sync" ::: "memory")
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#elif defined(__aarch64__)
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#define spdk_wmb() __asm volatile("dsb st" ::: "memory")
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#elif defined(__i386__) || defined(__x86_64__)
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#define spdk_wmb() __asm volatile("sfence" ::: "memory")
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#else
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#define spdk_wmb()
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#error Unknown architecture
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#endif
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/** Full read/write memory barrier */
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#ifdef __PPC64__
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#define spdk_mb() __asm volatile("sync" ::: "memory")
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#elif defined(__aarch64__)
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#define spdk_mb() __asm volatile("dsb sy" ::: "memory")
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#elif defined(__i386__) || defined(__x86_64__)
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#define spdk_mb() __asm volatile("mfence" ::: "memory")
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#else
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#define spdk_mb()
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#error Unknown architecture
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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