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freebsd-dev/sys/arm/include/intr.h

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Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
/* $NetBSD: intr.h,v 1.7 2003/06/16 20:01:00 thorpej Exp $ */
Start all license statements with /*-
2005-01-05 21:58:49 +00:00
/*-
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
* Copyright (c) 1997 Mark Brinicombe.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Mark Brinicombe
* for the NetBSD Project.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
Merge WIP from p4: o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
/* XXX move to std.* files? */
The iop34x has 128 interrupts.
2007-06-16 15:03:33 +00:00
#ifdef CPU_XSCALE_81342
#define NIRQ 128
Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connex boards. This is enough to net-boot to multiuser. Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC add-on boards. I'll be putting some instructions on how to boot this on the Gumstix boards online soon. This is still fairly rough and will be refined over time but I felt it was better to get this out there where other people can help out.
2008-06-06 05:08:09 +00:00
#elif defined(CPU_XSCALE_PXA2X0)
#include <arm/xscale/pxa/pxareg.h>
#define NIRQ IRQ_GPIO_MAX
Introduce basic support for Marvell families of system-on-chip ARM devices: * Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
2008-10-13 20:07:13 +00:00
#elif defined(SOC_MV_DISCOVERY)
#define NIRQ 96
Merge WIP from p4: o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \
defined(CPU_XSCALE_IXP435)
Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides 64 irqs. This should be re-thought later.
2005-02-13 18:26:31 +00:00
#define NIRQ 64
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
#elif defined(CPU_CORTEXA)
Bump max number of IRQs for Cortex-Ax family to cover Exynos5 requirement. Submitted by: Ruslan Bukin <br@bsdpad.com>
2013-06-28 22:47:33 +00:00
#define NIRQ 160
Add identification and necessary type checks for Krait CPU cores. Krait CPU is used in Qualcomm Snapdragon S4 and Snapdragon 400/600/800 SoCs and has architectural similarities to ARM Cortex-A15. As for development boards IFC6400 series embedded boards from Inforce Computing uses Snapdragon S4 Pro/APQ8064. Approved by: stas (mentor)
2013-12-20 00:56:23 +00:00
#elif defined(CPU_KRAIT)
#define NIRQ 288
Replace generic ARM11 option with more specific support for ARM1136 and ARM1176 Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Obtained from: NetBSD
2012-12-20 04:32:02 +00:00
#elif defined(CPU_ARM1136) || defined(CPU_ARM1176)
ARM11 might have more then 32 interrupts, e.g. BCM2835: 72 interrupts
2012-08-25 20:13:19 +00:00
#define NIRQ 128
Add support for Armada XP A0. - Add functions to calculate clocks instead using hardcoded values - Update reset and timers functions - Update number of interrupts - Change name of platform from db88f78100 to db78460 - Correct DRAM size and PCI IRQ routing in dts file. Obtained from: Semihalf
2012-09-14 09:55:19 +00:00
#elif defined(SOC_MV_ARMADAXP)
Add support for MSI in interrupt controlller. MSI are implemented via software interrupt. PCIe cards will write into software interrupt register which will cause inbound shared interrupt which will be interpreted as a MSI. Obtained from: Marvell, Semihalf
2012-09-14 10:05:01 +00:00
#define MAIN_IRQ_NUM 116
#define ERR_IRQ_NUM 32
#define ERR_IRQ (MAIN_IRQ_NUM)
#define MSI_IRQ_NUM 32
#define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM)
#define NIRQ (MAIN_IRQ_NUM + ERR_IRQ_NUM + MSI_IRQ_NUM)
Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides 64 irqs. This should be re-thought later.
2005-02-13 18:26:31 +00:00
#else
Add new functions to know which irqs are pending, and to mask and unmask interrupts, as these are CPU specific. If the interrupt handler is not marked as INTR_FAST, don't unmask the interrupt until it as been serviced.
2004-09-23 22:09:57 +00:00
#define NIRQ 32
Define NIRQ to 64 for CPU_ARM9, because Cirrus Logic EP93XX cores provides 64 irqs. This should be re-thought later.
2005-02-13 18:26:31 +00:00
#endif
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
Pass the previously returned IRQ back to arm_get_next_irq() so that the implementation can guarantee forward progress in the event of a stuck interrupt or interrupt storm. This is especially critical for fast interrupt handlers, as they can cause a hard hang in that case. When first called, arm_get_next_irq() is passed -1. Obtained from: Juniper Networks, Inc.
2009-06-09 18:18:41 +00:00
int arm_get_next_irq(int);
- MFp4: modify slightly the arm intr API, there's arm CPUs with more than 32 interrupts. - Implement teardown methods where appropriate.
2005-06-09 12:26:20 +00:00
void arm_mask_irq(uintptr_t);
void arm_unmask_irq(uintptr_t);
Eliminate the need for an intermediate array of indices into the arrays of interrupt counts and names, by making the names into an array of fixed-length strings that can be directly indexed. This eliminates extra memory accesses on every interrupt to increment the counts. As a side effect, it also fixes a bug that would corrupt the names data if a name was longer than MAXCOMLEN, which led to incorrect vmstat -i output. Approved by: cognet (mentor)
2013-01-19 00:50:12 +00:00
void arm_intrnames_init(void);
trim trailing whitespace
2012-06-13 05:02:51 +00:00
void arm_setup_irqhandler(const char *, int (*)(void*), void (*)(void*),
void *, int, int, void **);
ARM interrupts improvements. - Fix nexus_setup_intr() abuse of setting up multiple IRQs in one go. Calling arm_setup_irqhandler() in loop is bogus, as there's just one cookie given from the caller and it is overwritten in each iteration so that only the last handler's cookie value prevails. - Proper intr masking/unmasking handling: the IRQ source is masked at PIC level only after the last handler has been removed from the list. Reviewed by: cognet, imp, sam, stass Obtained from: Grzegorz Bernacki gjb ! semihalf dot com
2008-09-11 12:36:13 +00:00
int arm_remove_irqhandler(int, void *);
On the AT91, we need to write on the EOI register after we handle an interrupt. So, add a new function pointer, arm_post_filter, which defaults to NULL, and which will be used as the post_filter arg for intr_event_create(). Set it properly for the AT91, so that it boots again. Reported by: hps
2008-04-20 23:29:06 +00:00
extern void (*arm_post_filter)(void *);
Add polarity and level support to ARM GIC Add suport for setting triggering level and polarity in GIC. New function pointer was added to nexus which corresponds to the function which sets level/sense in the hardware (GIC). Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf
2014-01-01 20:03:48 +00:00
extern int (*arm_config_irq)(int irq, enum intr_trigger trig,
enum intr_polarity pol);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
Eliminate one of the causes of spurious interrupts on armv6. The arm weak memory ordering model allows writes to different devices to complete out of order, leading to a situation where the write that clears an interrupt source at a device can complete after a write that unmasks and EOIs the interrupt at the interrupt controller, leading to a spurious re-interrupt. This adds a generic barrier function specific to the needs of interrupt controllers, and calls that function from the GIC and TI AINTC controllers. There may still be other soc-specific controllers that need to make the call. Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com> MFC after: 3 days
2014-05-24 16:21:16 +00:00
void arm_irq_memory_barrier(uintptr_t);
Merging projects/armv6, part 1 Cummulative patch of changes that are not vendor-specific: - ARMv6 and ARMv7 architecture support - ARM SMP support - VFP/Neon support - ARM Generic Interrupt Controller driver - Simplification of startup code for all platforms
2012-08-15 03:03:03 +00:00
void gic_init_secondary(void);
Import FreeBSD/arm kernel bits. It only supports sa1110 (on simics) right now, but xscale support should come soon. Some of the initial work has been provided by : Stephane Potvin <sepotvin at videotron.ca> Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00
#endif /* _MACHINE_INTR_H */
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