2017-11-13 20:15:33 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2016-01-28 20:21:15 +00:00
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/*
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* This header provides clock numbers for the ingenic,jz4740-cgu DT binding.
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*
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* They are roughly ordered as:
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* - external clocks
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* - PLLs
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* - muxes/dividers in the order they appear in the jz4740 programmers manual
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* - gates in order of their bit in the CLKGR* registers
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*/
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#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
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#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__
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#define JZ4740_CLK_EXT 0
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#define JZ4740_CLK_RTC 1
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#define JZ4740_CLK_PLL 2
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#define JZ4740_CLK_PLL_HALF 3
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#define JZ4740_CLK_CCLK 4
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#define JZ4740_CLK_HCLK 5
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#define JZ4740_CLK_PCLK 6
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#define JZ4740_CLK_MCLK 7
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#define JZ4740_CLK_LCD 8
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#define JZ4740_CLK_LCD_PCLK 9
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#define JZ4740_CLK_I2S 10
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#define JZ4740_CLK_SPI 11
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#define JZ4740_CLK_MMC 12
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#define JZ4740_CLK_UHC 13
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#define JZ4740_CLK_UDC 14
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#define JZ4740_CLK_UART0 15
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#define JZ4740_CLK_UART1 16
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#define JZ4740_CLK_DMA 17
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#define JZ4740_CLK_IPU 18
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#define JZ4740_CLK_ADC 19
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#define JZ4740_CLK_I2C 20
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#define JZ4740_CLK_AIC 21
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2019-11-28 19:05:03 +00:00
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#define JZ4740_CLK_TCU 22
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2016-01-28 20:21:15 +00:00
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#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */
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