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freebsd-dev/sys/mips/conf/AR934X_BASE.hints

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Add some initial board support for the AR934x and the Qualcomm Atheros DB120 development board. The AR934x SoCs are a MIPS74k based system with increased RAM addressing space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3 on-board dual-band wifi. This support isn't complete by any stretch; it's just enough to bring the board up for others to tinker with. Notably, the MIPS74k support is broken. However it boots enough to echo some basic probe/attach messages, before dying somewhere in the TLB code. Thankyou to Qualcomm Atheros for their continued support of me doing open source work with their hardware. Tested: * AR9344, mips74k
2013-07-21 04:00:48 +00:00
# This file (and the kernel config file accompanying it) are not designed
# to be used by themselves. Instead, users of this file should create a
# kernel # config file which includes this file (which gets the basic hints),
# then override the default options (adding devices as needed) and adding
# hints as needed (for example, the GPIO and LAN PHY.)
# $FreeBSD$
hint.apb.0.at="nexus0"
hint.apb.0.irq=4
[ar71xx] Start migrating the AR934x based boards over to the new world order. This unifies the PCI hints with the AHB/NOR hint syntax. Tested: * DIR825C1, AR9344 SoC / 2x2 2G + AR9580 PCI 2x2 5G
2017-07-06 04:06:25 +00:00
# ART calibration data mapping device
hint.ar71xx_caldata.0.at="nexus0"
hint.ar71xx_caldata.0.order=0
Add some initial board support for the AR934x and the Qualcomm Atheros DB120 development board. The AR934x SoCs are a MIPS74k based system with increased RAM addressing space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3 on-board dual-band wifi. This support isn't complete by any stretch; it's just enough to bring the board up for others to tinker with. Notably, the MIPS74k support is broken. However it boots enough to echo some basic probe/attach messages, before dying somewhere in the TLB code. Thankyou to Qualcomm Atheros for their continued support of me doing open source work with their hardware. Tested: * AR9344, mips74k
2013-07-21 04:00:48 +00:00
# uart0
hint.uart.0.at="apb0"
# NB: This isn't an ns8250 UART
hint.uart.0.maddr=0x18020003
hint.uart.0.msize=0x18
hint.uart.0.irq=3
#ehci - note the 0x100 offset for the AR913x/AR724x
hint.ehci.0.at="nexus0"
hint.ehci.0.maddr=0x1b000100
hint.ehci.0.msize=0x00001000
hint.ehci.0.irq=1
Enable use of the PCIe connected wifi on the DB120 (AR9344) board. The on-board NIC is an 3x3 AR9380 with 5GHz only. * enable pci code in AR9344_BASE * enable ath_pci and the firmware loading bits in DB120 * add in the relevant hints in DB120.hints to inform the probe/attach code where the PCIe fixup data is for the onboard chip. This is only relevant for a default development board. I also have a DB120 with the on-board PCIe wifi NIC disabled and it's exposed as a real PCIe slot (to put normal PCIe NICs in); the fixup code will need to be disabled to make this work correctly. Tested: * DB120
2014-02-14 05:25:15 +00:00
# pci
hint.pcib.0.at="nexus0"
hint.pcib.0.irq=0
Add some initial board support for the AR934x and the Qualcomm Atheros DB120 development board. The AR934x SoCs are a MIPS74k based system with increased RAM addressing space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3 on-board dual-band wifi. This support isn't complete by any stretch; it's just enough to bring the board up for others to tinker with. Notably, the MIPS74k support is broken. However it boots enough to echo some basic probe/attach messages, before dying somewhere in the TLB code. Thankyou to Qualcomm Atheros for their continued support of me doing open source work with their hardware. Tested: * AR9344, mips74k
2013-07-21 04:00:48 +00:00
hint.arge.0.at="nexus0"
hint.arge.0.maddr=0x19000000
hint.arge.0.msize=0x1000
hint.arge.0.irq=2
hint.arge.1.at="nexus0"
hint.arge.1.maddr=0x1a000000
hint.arge.1.msize=0x1000
hint.arge.1.irq=3
# XXX The ath device hangs off of the AHB, rather than the Nexus.
hint.ath.0.at="nexus0"
hint.ath.0.maddr=0x18100000
hint.ath.0.msize=0x20000
hint.ath.0.irq=0
hint.ath.0.vendor_id=0x168c
hint.ath.0.device_id=0x0031
# Set this to define where the ath calibration data
# should be fetched from in physical memory.
# hint.ath.0.eepromaddr=0x1fff1000
[ar71xx] Start migrating the AR934x based boards over to the new world order. This unifies the PCI hints with the AHB/NOR hint syntax. Tested: * DIR825C1, AR9344 SoC / 2x2 2G + AR9580 PCI 2x2 5G
2017-07-06 04:06:25 +00:00
# Where the ART is - last 64k in the first 8MB of flash
#hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
#hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
# And now tell the ath(4) driver where to look!
#hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
Add some initial board support for the AR934x and the Qualcomm Atheros DB120 development board. The AR934x SoCs are a MIPS74k based system with increased RAM addressing space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3 on-board dual-band wifi. This support isn't complete by any stretch; it's just enough to bring the board up for others to tinker with. Notably, the MIPS74k support is broken. However it boots enough to echo some basic probe/attach messages, before dying somewhere in the TLB code. Thankyou to Qualcomm Atheros for their continued support of me doing open source work with their hardware. Tested: * AR9344, mips74k
2013-07-21 04:00:48 +00:00
# SPI flash
hint.spi.0.at="nexus0"
hint.spi.0.maddr=0x1f000000
hint.spi.0.msize=0x10
hint.mx25l.0.at="spibus0"
hint.mx25l.0.cs=0
# Watchdog
hint.ar71xx_wdog.0.at="nexus0"
# The GPIO function and pin mask is configured per-board
hint.gpio.0.at="apb0"
hint.gpio.0.maddr=0x18040000
hint.gpio.0.msize=0x1000
hint.gpio.0.irq=2
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