2005-01-06 01:43:34 +00:00
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/*-
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2002-08-26 17:55:42 +00:00
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000, BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2003-08-24 17:55:58 +00:00
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
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#include "opt_acpi.h"
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2002-08-26 17:55:42 +00:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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2009-06-05 18:44:36 +00:00
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#include <contrib/dev/acpica/include/acpi.h>
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#include <contrib/dev/acpica/include/accommon.h>
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2002-08-26 17:55:42 +00:00
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#include <dev/acpica/acpivar.h>
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2016-04-07 17:15:16 +00:00
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#include <dev/acpica/acpi_pcivar.h>
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2002-08-26 17:55:42 +00:00
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#include <sys/pciio.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pci_private.h>
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#include "pcib_if.h"
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#include "pci_if.h"
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2004-05-29 04:32:50 +00:00
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/* Hooks for the ACPI CA debugging infrastructure. */
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2002-08-26 17:55:42 +00:00
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#define _COMPONENT ACPI_BUS
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ACPI_MODULE_NAME("PCI")
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struct acpi_pci_devinfo {
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2004-05-29 04:32:50 +00:00
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struct pci_devinfo ap_dinfo;
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ACPI_HANDLE ap_handle;
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2004-06-30 16:08:03 +00:00
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int ap_flags;
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2002-08-26 17:55:42 +00:00
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};
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2004-08-13 06:21:58 +00:00
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ACPI_SERIAL_DECL(pci_powerstate, "ACPI PCI power methods");
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2004-11-29 18:48:51 +00:00
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/* Be sure that ACPI and PCI power states are equivalent. */
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CTASSERT(ACPI_STATE_D0 == PCI_POWERSTATE_D0);
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CTASSERT(ACPI_STATE_D1 == PCI_POWERSTATE_D1);
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CTASSERT(ACPI_STATE_D2 == PCI_POWERSTATE_D2);
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CTASSERT(ACPI_STATE_D3 == PCI_POWERSTATE_D3);
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2016-04-15 03:42:12 +00:00
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static struct pci_devinfo *acpi_pci_alloc_devinfo(device_t dev);
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2019-10-15 19:04:39 +00:00
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static int acpi_pci_attach(device_t dev);
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2016-04-06 04:10:22 +00:00
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static void acpi_pci_child_deleted(device_t dev, device_t child);
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2004-03-31 17:27:19 +00:00
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static int acpi_pci_child_location_str_method(device_t cbdev,
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2004-05-29 04:32:50 +00:00
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device_t child, char *buf, size_t buflen);
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2019-10-15 19:04:39 +00:00
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static int acpi_pci_detach(device_t dev);
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2004-06-23 15:08:40 +00:00
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static int acpi_pci_probe(device_t dev);
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static int acpi_pci_read_ivar(device_t dev, device_t child, int which,
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uintptr_t *result);
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2004-06-30 16:08:03 +00:00
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static int acpi_pci_write_ivar(device_t dev, device_t child, int which,
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uintptr_t value);
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2002-08-26 17:55:42 +00:00
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static ACPI_STATUS acpi_pci_save_handle(ACPI_HANDLE handle, UINT32 level,
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2004-05-29 04:32:50 +00:00
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void *context, void **status);
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2004-06-23 15:08:40 +00:00
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static int acpi_pci_set_powerstate_method(device_t dev, device_t child,
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int state);
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static void acpi_pci_update_device(ACPI_HANDLE handle, device_t pci_child);
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
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static bus_dma_tag_t acpi_pci_get_dma_tag(device_t bus, device_t child);
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2002-08-26 17:55:42 +00:00
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static device_method_t acpi_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, acpi_pci_probe),
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2019-10-15 19:04:39 +00:00
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DEVMETHOD(device_attach, acpi_pci_attach),
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DEVMETHOD(device_detach, acpi_pci_detach),
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2002-08-26 17:55:42 +00:00
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, acpi_pci_read_ivar),
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2004-06-30 16:08:03 +00:00
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DEVMETHOD(bus_write_ivar, acpi_pci_write_ivar),
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2016-04-06 04:10:22 +00:00
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DEVMETHOD(bus_child_deleted, acpi_pci_child_deleted),
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2004-03-31 17:27:19 +00:00
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DEVMETHOD(bus_child_location_str, acpi_pci_child_location_str_method),
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2016-05-09 20:50:21 +00:00
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DEVMETHOD(bus_get_cpus, acpi_get_cpus),
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
|
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DEVMETHOD(bus_get_dma_tag, acpi_pci_get_dma_tag),
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2014-10-09 05:33:25 +00:00
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DEVMETHOD(bus_get_domain, acpi_get_domain),
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2002-08-26 17:55:42 +00:00
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/* PCI interface */
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2016-04-15 03:42:12 +00:00
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DEVMETHOD(pci_alloc_devinfo, acpi_pci_alloc_devinfo),
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2016-04-07 17:15:16 +00:00
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DEVMETHOD(pci_child_added, acpi_pci_child_added),
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2004-04-07 19:42:21 +00:00
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DEVMETHOD(pci_set_powerstate, acpi_pci_set_powerstate_method),
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2002-08-26 17:55:42 +00:00
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2013-01-30 18:01:20 +00:00
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DEVMETHOD_END
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2002-08-26 17:55:42 +00:00
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};
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2006-01-20 22:01:34 +00:00
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static devclass_t pci_devclass;
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2002-08-26 17:55:42 +00:00
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2012-03-02 20:38:04 +00:00
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DEFINE_CLASS_1(pci, acpi_pci_driver, acpi_pci_methods, sizeof(struct pci_softc),
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pci_driver);
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2002-08-26 17:55:42 +00:00
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DRIVER_MODULE(acpi_pci, pcib, acpi_pci_driver, pci_devclass, 0, 0);
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2004-04-09 18:14:32 +00:00
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MODULE_DEPEND(acpi_pci, acpi, 1, 1, 1);
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2002-08-26 17:55:42 +00:00
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MODULE_DEPEND(acpi_pci, pci, 1, 1, 1);
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2004-04-09 18:14:32 +00:00
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MODULE_VERSION(acpi_pci, 1);
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2002-08-26 17:55:42 +00:00
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2016-04-15 03:42:12 +00:00
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static struct pci_devinfo *
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acpi_pci_alloc_devinfo(device_t dev)
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{
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struct acpi_pci_devinfo *dinfo;
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dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO);
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return (&dinfo->ap_dinfo);
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}
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2002-08-26 17:55:42 +00:00
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static int
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acpi_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct acpi_pci_devinfo *dinfo;
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2004-06-30 16:08:03 +00:00
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dinfo = device_get_ivars(child);
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2002-08-26 17:55:42 +00:00
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switch (which) {
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2004-03-31 17:35:28 +00:00
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case ACPI_IVAR_HANDLE:
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2002-08-26 17:55:42 +00:00
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*result = (uintptr_t)dinfo->ap_handle;
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2004-03-31 17:35:28 +00:00
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return (0);
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2004-06-30 16:08:03 +00:00
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case ACPI_IVAR_FLAGS:
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*result = (uintptr_t)dinfo->ap_flags;
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return (0);
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2002-08-26 17:55:42 +00:00
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}
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2004-03-31 17:35:28 +00:00
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return (pci_read_ivar(dev, child, which, result));
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2002-08-26 17:55:42 +00:00
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}
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2004-06-30 16:08:03 +00:00
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static int
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acpi_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
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{
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struct acpi_pci_devinfo *dinfo;
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dinfo = device_get_ivars(child);
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switch (which) {
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case ACPI_IVAR_HANDLE:
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dinfo->ap_handle = (ACPI_HANDLE)value;
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return (0);
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case ACPI_IVAR_FLAGS:
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dinfo->ap_flags = (int)value;
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return (0);
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}
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return (pci_write_ivar(dev, child, which, value));
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}
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|
2016-04-06 04:10:22 +00:00
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static void
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acpi_pci_child_deleted(device_t dev, device_t child)
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{
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struct acpi_pci_devinfo *dinfo = device_get_ivars(child);
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if (acpi_get_device(dinfo->ap_handle) == child)
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AcpiDetachData(dinfo->ap_handle, acpi_fake_objhandler);
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pci_child_deleted(dev, child);
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}
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2004-03-31 17:27:19 +00:00
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static int
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acpi_pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
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size_t buflen)
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{
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struct acpi_pci_devinfo *dinfo = device_get_ivars(child);
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2014-09-20 04:31:12 +00:00
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int pxm;
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char buf2[32];
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2004-03-31 17:35:28 +00:00
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2004-03-31 17:27:19 +00:00
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pci_child_location_str_method(cbdev, child, buf, buflen);
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2014-09-20 04:31:12 +00:00
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2004-03-31 17:35:28 +00:00
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if (dinfo->ap_handle) {
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2014-09-20 04:31:12 +00:00
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strlcat(buf, " handle=", buflen);
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strlcat(buf, acpi_name(dinfo->ap_handle), buflen);
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if (ACPI_SUCCESS(acpi_GetInteger(dinfo->ap_handle, "_PXM", &pxm))) {
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snprintf(buf2, 32, " _PXM=%d", pxm);
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strlcat(buf, buf2, buflen);
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}
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2004-03-31 17:27:19 +00:00
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}
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return (0);
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}
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2002-08-26 17:55:42 +00:00
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/*
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* PCI power manangement
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*/
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static int
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acpi_pci_set_powerstate_method(device_t dev, device_t child, int state)
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{
|
2004-04-14 17:46:21 +00:00
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ACPI_HANDLE h;
|
2004-04-07 19:42:21 +00:00
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ACPI_STATUS status;
|
2004-11-29 18:48:51 +00:00
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int old_state, error;
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2004-04-07 19:42:21 +00:00
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2004-08-13 06:21:58 +00:00
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error = 0;
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2004-11-29 18:48:51 +00:00
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if (state < ACPI_STATE_D0 || state > ACPI_STATE_D3)
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2004-04-07 19:42:21 +00:00
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return (EINVAL);
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2002-08-26 17:55:42 +00:00
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2004-04-07 19:42:21 +00:00
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/*
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* We set the state using PCI Power Management outside of setting
|
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|
|
* the ACPI state. This means that when powering down a device, we
|
|
|
|
* first shut it down using PCI, and then using ACPI, which lets ACPI
|
|
|
|
* try to power down any Power Resources that are now no longer used.
|
|
|
|
* When powering up a device, we let ACPI set the state first so that
|
|
|
|
* it can enable any needed Power Resources before changing the PCI
|
|
|
|
* power state.
|
|
|
|
*/
|
2004-08-13 06:21:58 +00:00
|
|
|
ACPI_SERIAL_BEGIN(pci_powerstate);
|
2004-04-07 19:42:21 +00:00
|
|
|
old_state = pci_get_powerstate(child);
|
2010-10-20 16:47:09 +00:00
|
|
|
if (old_state < state && pci_do_power_suspend) {
|
2004-04-07 19:42:21 +00:00
|
|
|
error = pci_set_powerstate_method(dev, child, state);
|
|
|
|
if (error)
|
2004-08-13 06:21:58 +00:00
|
|
|
goto out;
|
2004-04-07 19:42:21 +00:00
|
|
|
}
|
2004-06-07 21:44:01 +00:00
|
|
|
h = acpi_get_handle(child);
|
2004-11-29 18:48:51 +00:00
|
|
|
status = acpi_pwr_switch_consumer(h, state);
|
2010-10-19 19:53:06 +00:00
|
|
|
if (ACPI_SUCCESS(status)) {
|
|
|
|
if (bootverbose)
|
|
|
|
device_printf(dev, "set ACPI power state D%d on %s\n",
|
|
|
|
state, acpi_name(h));
|
|
|
|
} else if (status != AE_NOT_FOUND)
|
2004-06-07 21:39:15 +00:00
|
|
|
device_printf(dev,
|
2010-10-19 19:53:06 +00:00
|
|
|
"failed to set ACPI power state D%d on %s: %s\n",
|
2004-11-29 18:48:51 +00:00
|
|
|
state, acpi_name(h), AcpiFormatException(status));
|
2010-10-19 18:43:11 +00:00
|
|
|
if (old_state > state && pci_do_power_resume)
|
2004-08-13 06:21:58 +00:00
|
|
|
error = pci_set_powerstate_method(dev, child, state);
|
|
|
|
|
|
|
|
out:
|
|
|
|
ACPI_SERIAL_END(pci_powerstate);
|
|
|
|
return (error);
|
2002-08-26 17:55:42 +00:00
|
|
|
}
|
|
|
|
|
2004-06-23 15:08:40 +00:00
|
|
|
static void
|
|
|
|
acpi_pci_update_device(ACPI_HANDLE handle, device_t pci_child)
|
|
|
|
{
|
|
|
|
ACPI_STATUS status;
|
|
|
|
device_t child;
|
|
|
|
|
|
|
|
/*
|
2011-06-17 21:19:01 +00:00
|
|
|
* Occasionally a PCI device may show up as an ACPI device
|
|
|
|
* with a _HID. (For example, the TabletPC TC1000 has a
|
|
|
|
* second PCI-ISA bridge that has a _HID for an
|
|
|
|
* acpi_sysresource device.) In that case, leave ACPI-CA's
|
|
|
|
* device data pointing at the ACPI-enumerated device.
|
2004-06-23 15:08:40 +00:00
|
|
|
*/
|
|
|
|
child = acpi_get_device(handle);
|
|
|
|
if (child != NULL) {
|
|
|
|
KASSERT(device_get_parent(child) ==
|
|
|
|
devclass_get_device(devclass_find("acpi"), 0),
|
|
|
|
("%s: child (%s)'s parent is not acpi0", __func__,
|
|
|
|
acpi_name(handle)));
|
2011-06-17 21:19:01 +00:00
|
|
|
return;
|
2004-06-23 15:08:40 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update ACPI-CA to use the PCI enumerated device_t for this handle.
|
|
|
|
*/
|
2004-06-24 01:57:31 +00:00
|
|
|
status = AcpiAttachData(handle, acpi_fake_objhandler, pci_child);
|
2004-06-23 15:08:40 +00:00
|
|
|
if (ACPI_FAILURE(status))
|
|
|
|
printf("WARNING: Unable to attach object data to %s - %s\n",
|
|
|
|
acpi_name(handle), AcpiFormatException(status));
|
|
|
|
}
|
|
|
|
|
2002-08-26 17:55:42 +00:00
|
|
|
static ACPI_STATUS
|
|
|
|
acpi_pci_save_handle(ACPI_HANDLE handle, UINT32 level, void *context,
|
|
|
|
void **status)
|
|
|
|
{
|
|
|
|
struct acpi_pci_devinfo *dinfo;
|
2016-04-07 17:15:16 +00:00
|
|
|
device_t child;
|
|
|
|
int func, slot;
|
2002-08-26 17:55:42 +00:00
|
|
|
UINT32 address;
|
|
|
|
|
|
|
|
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
|
|
|
|
|
2016-04-07 17:15:16 +00:00
|
|
|
child = context;
|
2004-03-03 18:34:42 +00:00
|
|
|
if (ACPI_FAILURE(acpi_GetInteger(handle, "_ADR", &address)))
|
2004-05-29 04:32:50 +00:00
|
|
|
return_ACPI_STATUS (AE_OK);
|
2004-09-22 15:46:16 +00:00
|
|
|
slot = ACPI_ADR_PCI_SLOT(address);
|
|
|
|
func = ACPI_ADR_PCI_FUNC(address);
|
2016-04-07 17:15:16 +00:00
|
|
|
dinfo = device_get_ivars(child);
|
|
|
|
if (dinfo->ap_dinfo.cfg.func == func &&
|
|
|
|
dinfo->ap_dinfo.cfg.slot == slot) {
|
|
|
|
dinfo->ap_handle = handle;
|
|
|
|
acpi_pci_update_device(handle, child);
|
|
|
|
return_ACPI_STATUS (AE_CTRL_TERMINATE);
|
2002-08-26 17:55:42 +00:00
|
|
|
}
|
2004-05-29 04:32:50 +00:00
|
|
|
return_ACPI_STATUS (AE_OK);
|
2002-08-26 17:55:42 +00:00
|
|
|
}
|
|
|
|
|
2016-04-07 17:15:16 +00:00
|
|
|
void
|
|
|
|
acpi_pci_child_added(device_t dev, device_t child)
|
|
|
|
{
|
|
|
|
|
2002-08-26 17:55:42 +00:00
|
|
|
/*
|
2016-04-07 17:15:16 +00:00
|
|
|
* PCI devices are added via the bus scan in the normal PCI
|
|
|
|
* bus driver. As each device is added, the
|
|
|
|
* acpi_pci_child_added() callback walks the ACPI namespace
|
|
|
|
* under the bridge driver to save ACPI handles to all the
|
|
|
|
* devices that appear in the ACPI namespace as immediate
|
|
|
|
* descendants of the bridge.
|
2002-08-26 17:55:42 +00:00
|
|
|
*
|
|
|
|
* XXX: Sometimes PCI devices show up in the ACPI namespace that
|
|
|
|
* pci_add_children() doesn't find. We currently just ignore
|
|
|
|
* these devices.
|
|
|
|
*/
|
2016-04-15 03:42:12 +00:00
|
|
|
AcpiWalkNamespace(ACPI_TYPE_DEVICE, acpi_get_handle(dev), 1,
|
|
|
|
acpi_pci_save_handle, NULL, child, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acpi_pci_probe(device_t dev)
|
|
|
|
{
|
2002-08-26 17:55:42 +00:00
|
|
|
|
2016-04-15 03:42:12 +00:00
|
|
|
if (acpi_get_handle(dev) == NULL)
|
|
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "ACPI PCI bus");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
2002-08-26 17:55:42 +00:00
|
|
|
}
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
|
|
|
|
2019-10-15 19:12:09 +00:00
|
|
|
static void
|
|
|
|
acpi_pci_bus_notify_handler(ACPI_HANDLE h, UINT32 notify, void *context)
|
|
|
|
{
|
|
|
|
device_t dev;
|
|
|
|
|
|
|
|
dev = context;
|
|
|
|
|
|
|
|
switch (notify) {
|
|
|
|
case ACPI_NOTIFY_BUS_CHECK:
|
|
|
|
mtx_lock(&Giant);
|
|
|
|
BUS_RESCAN(dev);
|
|
|
|
mtx_unlock(&Giant);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
device_printf(dev, "unknown notify %#x\n", notify);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-15 19:04:39 +00:00
|
|
|
static void
|
|
|
|
acpi_pci_device_notify_handler(ACPI_HANDLE h, UINT32 notify, void *context)
|
|
|
|
{
|
|
|
|
device_t child, dev;
|
|
|
|
ACPI_STATUS status;
|
|
|
|
int error;
|
|
|
|
|
|
|
|
dev = context;
|
|
|
|
|
|
|
|
switch (notify) {
|
|
|
|
case ACPI_NOTIFY_DEVICE_CHECK:
|
|
|
|
mtx_lock(&Giant);
|
|
|
|
BUS_RESCAN(dev);
|
|
|
|
mtx_unlock(&Giant);
|
|
|
|
break;
|
|
|
|
case ACPI_NOTIFY_EJECT_REQUEST:
|
|
|
|
child = acpi_get_device(h);
|
|
|
|
if (child == NULL) {
|
|
|
|
device_printf(dev, "no device to eject for %s\n",
|
|
|
|
acpi_name(h));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
mtx_lock(&Giant);
|
|
|
|
error = device_detach(child);
|
|
|
|
if (error) {
|
|
|
|
mtx_unlock(&Giant);
|
|
|
|
device_printf(dev, "failed to detach %s: %d\n",
|
|
|
|
device_get_nameunit(child), error);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
status = acpi_SetInteger(h, "_EJ0", 1);
|
|
|
|
if (ACPI_FAILURE(status)) {
|
|
|
|
mtx_unlock(&Giant);
|
|
|
|
device_printf(dev, "failed to eject %s: %s\n",
|
|
|
|
acpi_name(h), AcpiFormatException(status));
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
BUS_RESCAN(dev);
|
|
|
|
mtx_unlock(&Giant);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
device_printf(dev, "unknown notify %#x for %s\n", notify,
|
|
|
|
acpi_name(h));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static ACPI_STATUS
|
|
|
|
acpi_pci_install_device_notify_handler(ACPI_HANDLE handle, UINT32 level,
|
|
|
|
void *context, void **status)
|
|
|
|
{
|
|
|
|
ACPI_HANDLE h;
|
|
|
|
|
|
|
|
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
|
|
|
|
|
|
|
|
if (ACPI_FAILURE(AcpiGetHandle(handle, "_EJ0", &h)))
|
|
|
|
return_ACPI_STATUS (AE_OK);
|
|
|
|
|
|
|
|
AcpiInstallNotifyHandler(handle, ACPI_SYSTEM_NOTIFY,
|
|
|
|
acpi_pci_device_notify_handler, context);
|
|
|
|
return_ACPI_STATUS (AE_OK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acpi_pci_attach(device_t dev)
|
|
|
|
{
|
|
|
|
int error;
|
|
|
|
|
|
|
|
error = pci_attach(dev);
|
|
|
|
if (error)
|
|
|
|
return (error);
|
2019-10-15 19:12:09 +00:00
|
|
|
AcpiInstallNotifyHandler(acpi_get_handle(dev), ACPI_SYSTEM_NOTIFY,
|
|
|
|
acpi_pci_bus_notify_handler, dev);
|
2019-10-15 19:04:39 +00:00
|
|
|
AcpiWalkNamespace(ACPI_TYPE_DEVICE, acpi_get_handle(dev), 1,
|
|
|
|
acpi_pci_install_device_notify_handler, NULL, dev, NULL);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static ACPI_STATUS
|
|
|
|
acpi_pci_remove_notify_handler(ACPI_HANDLE handle, UINT32 level, void *context,
|
|
|
|
void **status)
|
|
|
|
{
|
|
|
|
ACPI_HANDLE h;
|
|
|
|
|
|
|
|
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
|
|
|
|
|
|
|
|
if (ACPI_FAILURE(AcpiGetHandle(handle, "_EJ0", &h)))
|
|
|
|
return_ACPI_STATUS (AE_OK);
|
|
|
|
|
|
|
|
AcpiRemoveNotifyHandler(handle, ACPI_SYSTEM_NOTIFY,
|
|
|
|
acpi_pci_device_notify_handler);
|
|
|
|
return_ACPI_STATUS (AE_OK);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acpi_pci_detach(device_t dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
AcpiWalkNamespace(ACPI_TYPE_DEVICE, acpi_get_handle(dev), 1,
|
|
|
|
acpi_pci_remove_notify_handler, NULL, dev, NULL);
|
2019-10-15 19:12:09 +00:00
|
|
|
AcpiRemoveNotifyHandler(acpi_get_handle(dev), ACPI_SYSTEM_NOTIFY,
|
|
|
|
acpi_pci_bus_notify_handler);
|
2019-10-15 19:04:39 +00:00
|
|
|
return (pci_detach(dev));
|
|
|
|
}
|
|
|
|
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
|
|
|
#ifdef ACPI_DMAR
|
2020-05-26 16:40:40 +00:00
|
|
|
bus_dma_tag_t acpi_iommu_get_dma_tag(device_t dev, device_t child);
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
|
|
|
static bus_dma_tag_t
|
|
|
|
acpi_pci_get_dma_tag(device_t bus, device_t child)
|
|
|
|
{
|
|
|
|
bus_dma_tag_t tag;
|
|
|
|
|
|
|
|
if (device_get_parent(child) == bus) {
|
2020-05-26 16:40:40 +00:00
|
|
|
/* try iommu and return if it works */
|
|
|
|
tag = acpi_iommu_get_dma_tag(bus, child);
|
Import the driver for VT-d DMAR hardware, as specified in the revision
1.3 of Intelб╝ Virtualization Technology for Directed I/O Architecture
Specification. The Extended Context and PASIDs from the rev. 2.2 are
not supported, but I am not aware of any released hardware which
implements them. Code does not use queued invalidation, see comments
for the reason, and does not provide interrupt remapping services.
Code implements the management of the guest address space per domain
and allows to establish and tear down arbitrary mappings, but not
partial unmapping. The superpages are created as needed, but not
promoted. Faults are recorded, fault records could be obtained
programmatically, and printed on the console.
Implement the busdma(9) using DMARs. This busdma backend avoids
bouncing and provides security against misbehaving hardware and driver
bad programming, preventing leaks and corruption of the memory by wild
DMA accesses.
By default, the implementation is compiled into amd64 GENERIC kernel
but disabled; to enable, set hw.dmar.enable=1 loader tunable. Code is
written to work on i386, but testing there was low priority, and
driver is not enabled in GENERIC. Even with the DMAR turned on,
individual devices could be directed to use the bounce busdma with the
hw.busdma.pci<domain>:<bus>:<device>:<function>.bounce=1 tunable. If
DMARs are capable of the pass-through translations, it is used,
otherwise, an identity-mapping page table is constructed.
The driver was tested on Xeon 5400/5500 chipset legacy machine,
Haswell desktop and E5 SandyBridge dual-socket boxes, with ahci(4),
ata(4), bce(4), ehci(4), mfi(4), uhci(4), xhci(4) devices. It also
works with em(4) and igb(4), but there some fixes are needed for
drivers, which are not committed yet. Intel GPUs do not work with
DMAR (yet).
Many thanks to John Baldwin, who explained me the newbus integration;
Peter Holm, who did all testing and helped me to discover and
understand several incredible bugs; and to Jim Harris for the access
to the EDS and BWG and for listening when I have to explain my
findings to somebody.
Sponsored by: The FreeBSD Foundation
MFC after: 1 month
2013-10-28 13:33:29 +00:00
|
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} else
|
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tag = NULL;
|
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if (tag == NULL)
|
|
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tag = pci_get_dma_tag(bus, child);
|
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return (tag);
|
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}
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#else
|
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static bus_dma_tag_t
|
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acpi_pci_get_dma_tag(device_t bus, device_t child)
|
|
|
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{
|
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|
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return (pci_get_dma_tag(bus, child));
|
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}
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#endif
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2015-03-01 00:40:09 +00:00
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