Split get_sar_value function for Marvell ArmadaXP and Armada38X
get_sar_value is implemented only for ArmadaXP and Armada38X. Splitting it for two different functions and change registers names result in more generic code. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: andrew Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14736
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=331954
@ -43,11 +43,23 @@ int armada38x_open_bootrom_win(void);
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int armada38x_scu_enable(void);
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int armada38x_win_set_iosync_barrier(void);
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int armada38x_mbus_optimization(void);
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static uint64_t get_sar_value_armada38x(void);
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static int hw_clockrate;
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SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
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&hw_clockrate, 0, "CPU instruction clock rate");
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static uint64_t
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get_sar_value_armada38x(void)
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{
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uint32_t sar_low, sar_high;
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sar_high = 0;
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sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_ARMADA38X);
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return (((uint64_t)sar_high << 32) | sar_low);
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}
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uint32_t
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get_tclk(void)
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{
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@ -57,8 +69,8 @@ get_tclk(void)
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* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
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* Current setting is read from Sample At Reset register.
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*/
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sar = (uint32_t)get_sar_value();
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sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
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sar = (uint32_t)get_sar_value_armada38x();
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sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
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if (sar == 0)
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return (TCLK_250MHZ);
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else
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@ -78,7 +90,7 @@ get_cpu_freq(void)
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1866, 0, 0, 2000
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};
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sar = (uint32_t)get_sar_value();
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sar = (uint32_t)get_sar_value_armada38x();
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sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
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if (sar >= nitems(cpu_frequencies))
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return (0);
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@ -55,6 +55,7 @@ static uint32_t count_l2clk(void);
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void armadaxp_l2_init(void);
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void armadaxp_init_coher_fabric(void);
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int platform_get_ncpus(void);
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static uint64_t get_sar_value_armadaxp(void);
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#define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
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#define ARMADAXP_L2_CTRL 0x100
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@ -124,6 +125,18 @@ static uint16_t cpu_clock_table[] = {
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1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600,
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2133, 2200, 2400 };
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static uint64_t
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get_sar_value_armadaxp(void)
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{
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uint32_t sar_low, sar_high;
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sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_HI);
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sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_LO);
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return (((uint64_t)sar_high << 32) | sar_low);
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}
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uint32_t
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get_tclk(void)
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{
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@ -153,7 +166,7 @@ count_l2clk(void)
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uint8_t sar_cpu_freq, sar_fab_freq, array_size;
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/* Get value of the SAR register and process it */
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sar_reg = get_sar_value();
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sar_reg = get_sar_value_armadaxp();
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sar_cpu_freq = CPU_FREQ_FIELD(sar_reg);
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sar_fab_freq = FAB_FREQ_FIELD(sar_reg);
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@ -2664,28 +2664,3 @@ fdt_pic_decode_t fdt_pic_table[] = {
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NULL
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};
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#endif
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uint64_t
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get_sar_value(void)
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{
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uint32_t sar_low, sar_high;
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#if defined(SOC_MV_ARMADAXP)
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sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_HI);
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sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_LO);
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#elif defined(SOC_MV_ARMADA38X)
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sar_high = 0;
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sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET);
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#else
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/*
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* TODO: Add getting proper values for other SoC configurations
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*/
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sar_high = 0;
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sar_low = 0;
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#endif
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return (((uint64_t)sar_high << 32) | sar_low);
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}
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@ -327,13 +327,10 @@
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#define SAMPLE_AT_RESET 0x10
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#elif defined(SOC_MV_KIRKWOOD)
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#define SAMPLE_AT_RESET 0x30
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#elif defined(SOC_MV_ARMADA38X)
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#define SAMPLE_AT_RESET 0x400
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#endif
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#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_ARMADAXP)
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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#endif
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#define SAMPLE_AT_RESET_ARMADA38X 0x400
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#define SAMPLE_AT_RESET_LO 0x30
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#define SAMPLE_AT_RESET_HI 0x34
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/*
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* Clocks
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@ -344,11 +341,11 @@
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#elif defined(SOC_MV_DISCOVERY)
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#define TCLK_MASK 0x00000180
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#define TCLK_SHIFT 0x07
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#elif defined(SOC_MV_ARMADA38X)
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#define TCLK_MASK 0x00008000
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#define TCLK_SHIFT 15
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#endif
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#define TCLK_MASK_ARMADA38X 0x00008000
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#define TCLK_SHIFT_ARMADA38X 15
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#define TCLK_100MHZ 100000000
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#define TCLK_125MHZ 125000000
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#define TCLK_133MHZ 133333333
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@ -89,7 +89,6 @@ void soc_id(uint32_t *dev, uint32_t *rev);
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void soc_dump_decode_win(void);
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uint32_t soc_power_ctrl_get(uint32_t mask);
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void soc_power_ctrl_set(uint32_t mask);
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uint64_t get_sar_value(void);
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int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
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vm_paddr_t remap);
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