Commit Graph

214 Commits

Author SHA1 Message Date
John Baldwin
84c7fde72e Trust the settings programmed by the BIOS over what the $PIR says.
Specifically, if the BIOS has programmed an IRQ for a device that doesn't
match the list of valid IRQs for the link, use it anyway as some BIOSes
don't correctly list the valid IRQs in the $PIR.  Also, allow the user
to specify an IRQ that $PIR claims is invalid as an override, but emit a
warning in that case.
2005-04-14 18:25:09 +00:00
John Baldwin
5165a17df5 Add code to read the primary PCI bus number out of the Compaq/HP 6010
hotplug Host to PCI bridge.  This is only needed for the non-ACPI case
as the BIOS includes a proper _BBN method in ACPI.
2005-03-25 14:18:50 +00:00
Poul-Henning Kamp
c711aea6ca Make a bunch of malloc types static.
Found by:	src/tools/tools/kernxref
2005-02-10 12:02:37 +00:00
Warner Losh
86cb007f9f /* -> /*- for copyright notices, minor format tweaks as necessary 2005-01-06 22:18:23 +00:00
Scott Long
5662cf3c92 Remove a stray critical_exit().
Submitted by: johan
2004-12-13 07:08:44 +00:00
Scott Long
245e410ba7 Expand the scope of the critical section in the PCIe read and write methods
on the advice of Alan Cox.
2004-12-10 15:44:12 +00:00
Scott Long
568b7ee1b2 Due to a significant addition of code, add my copyright to this file. Also
note that the PCIe work was made possible due to hardware donations from
the FreeBSD Foundation and Intel.  Thanks!
2004-12-06 18:19:32 +00:00
Scott Long
aa2ea23220 Add support for the memory-mapped PCI Express configuration mechanism. This
actually is a property of the northbridge and applies to all PCI/PCI-X/PCIe
devices in the system, though only PCIe devices will respond to registers
higher than 256.  This uses per-CPU pools of temporary mappings so that
the whole 256MB of configuration space doesn't have to be mapped all at
once.  While the sf_buf API was considered for this, the fact that it
requires sleep locks and can return failure made it unsuitable for this use.

For now only the Intel Grantsdale and Lindenhurst (925 and 752x) chipsets are
supported.  Since there doesn't appear to be a compatible way to determine
northbridge support, new chipsets will have to be explicitely added in the
future.
2004-12-06 08:27:10 +00:00
Dag-Erling Smørgrav
b0e1e474f7 Add TUNABLE_LONG and TUNABLE_ULONG, and use the latter for the
hw.pci.host_mem_start tunable.  Add comments to TUNABLE_INT and
TUNABLE_QUAD recommending against their use.

MFC after:	3 weeks
2004-10-31 15:50:33 +00:00
Dag-Erling Smørgrav
38228f7221 Whitespace cleanup 2004-10-31 15:02:53 +00:00
Warner Losh
fd492ee0e6 Make the lower range of the memory area 0x80000000 again. Also
introduce hw.{pci,acpi}.host_mem_start tunable to change this.

MFC: ASAP
2004-10-11 21:10:23 +00:00
Warner Losh
e625cbacaf Add missing 'static' 2004-10-06 15:18:12 +00:00
Warner Losh
0b3a486f21 For legacy PCI bridges, limit memory allocation to the top 32MB of
RAM.  Many older, legacy bridges only allow allocation from this
range.  This only appies to devices who don't have their memory
assigned by the BIOS (since we allocate the ranges so assigned
exactly), so should have minimal impact.

Hoewver, for CardBus bridges (cbb), they rarely get the resources
allocated by the BIOS, and this patch helps them greatly.  Typically
the 'bad Vcc' messages are caused by this problem.
2004-10-06 07:22:58 +00:00
Stefan Farfeleder
5908d366fb Consistently use __inline instead of __inline__ as the former is an empty macro
in <sys/cdefs.h> for compilers without support for inline.
2004-07-04 16:11:03 +00:00
John Baldwin
39981fed82 Trim a few things from the dmesg output and stick them under bootverbose to
cut down on the clutter including PCI interrupt routing, MTRR, pcibios,
etc.

Discussed with:	USENIX Cabal
2004-07-01 07:46:29 +00:00
John Baldwin
092a5c4530 Remove atdevbase and replace it's remaining uses with direct references to
KERNBASE instead.
2004-06-10 20:31:00 +00:00
John Baldwin
4468ab0a61 Allow the pir0 device add to fail since pir0 may already exist. This should
fix the panics in device_set_ivars() that people were seeing on boxes with
multiple Host-PCI bridges but not using ACPI.
2004-06-01 19:51:29 +00:00
Poul-Henning Kamp
41ee9f1c69 Add some missing <sys/module.h> includes which are masked by the
one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
John Baldwin
7a64d8d74c - Create a pir0 psuedo device as a child of legacy0 if we attach a legacy
host-PCI bridge device and find a valid $PIR.
- Make pci_pir_parse() private to pci_pir.c and have pir0's attach routine
  call it instead of having legacy_pcib_attach() call it.
- Implement suspend/resume support for the $PIR by giving pir0 a resume
  method that calls the BIOS to reroute each link that was already routed
  before the machine was suspended.
- Dump the state of the routed flag in the links display code.
- If a link's IRQ is set by a tunable, then force that link to be re-routed
  the first time it is used.
- Move the 'Found $PIR' message under bootverbose as the pir0 description
  line lists the number of entries already.  The pir0 line also only shows
  up if we are actually using the $PIR which is a bonus.
- Use BUS_CONFIG_INTR() to ensure that any IRQs used by a PCI link are
  set to level/low trigger/polarity.
2004-05-04 21:17:52 +00:00
John Baldwin
be16306ad3 Make the legacy_pcib_attach() function static. 2004-05-03 14:49:43 +00:00
John Baldwin
86f4fd6f71 Don't call the BIOS to route a link that has already been routed by the
BIOS during POST as it apparently makes some machines unhappy.

Tested by:	mux
2004-04-16 18:54:05 +00:00
John Baldwin
ccab16610b Add back an include to fix the build for the CPU_ELAN case. 2004-02-19 18:34:26 +00:00
John Baldwin
77fa00fa7c Switch to using the new $PIR interrupt routing code and remove the old
code.  The pci_cfgreg.c file now just controls reading/writing PCI config
registers.
2004-02-18 22:41:53 +00:00
John Baldwin
2e41ba54d6 Rework the $PIR (aka PCIBIOS) PCI interrupt routing code and split it off
into its own file:
- All of the $PIR interrupt routing is now done in a link-centric fashion.
  When a host-PCI bridge that uses the $PIR attaches, it calls pir_parse()
  to parse the table.  This scans for link devices and merges all the masks
  for each link device from the table entries.  It then looks at the intline
  register of PCI devices connected to a link to figure out if the BIOS has
  routed this link and if so to which IRQ.
- The IRQ for any given link can be overridden via a hint like so:
  'hw.pci.link.0x62.irq=10'  Any IRQ set in this matter is treated as if it
  were set that way by the BIOS.
- We only call the BIOS to route each link device once.
- When a PCI device wants to route an interrupt, we look it up in the $PIR
  to find the associated link.  If the link is routed, we simply return the
  IRQ it is using.  If it is not routed, we have to pick one.  This uses a
  different algorithm from the old code.  First off, when we try to pick
  an interrupt from a mask of possible interrupts, we try to pick the one
  that is least loaded as far as PCI devices.  We maintain this weight based
  on the number of devices attached to each link device.  When choosing an
  IRQ, we first attempt to route using any PCI only interrupts (the old
  code did this as well).  If that doesn't work, we try to use the list of
  IRQs that the BIOS has used.  This is a new step that the new code didn't
  do and avoids using IRQ 3 or 4 for every virgin interrupt routing.  If
  none of the IRQs that the BIOS used worked, then we fall back to trying
  anything.
- The fallback mask for !PC98 was fixed to include IRQ 3 and not allow IRQ
  2.
- We don't use the $PIR to route interrupts on a PCI-PCI bridge unless it
  has already been used to route on at least one Host-PCI bridge.  This
  helps to avoid mixing and matching x86 firmware PCI interrupt routing
  methods (which is a Bad Thing(tm)).

Silence on:	current@
2004-02-18 22:40:23 +00:00
John Baldwin
21e25fa607 Replace an outb() during the test for configuration mechanism #1 with a
DELAY(1) instead.  After wading through old commit logs, I found that the
outb() was added not as part of the test but as an intentional delay. In
fact, according to Shanley's PCI book, the configuration 1 data and address
ports should only be accessed using aligned 32-bit accesses (i.e. inl()
and outl()).  Thus, using outb() to just the last byte of the port violates
the PCI spec it would seem.  On at least one box doing so broke the probe
for PCI, whereas changing it to a DELAY(1) fixed the probe.

Reported by:	Sean Welch <welchsm@earthlink.net>
MFC after:	1 week
2003-12-31 16:56:32 +00:00
John Baldwin
6f92bdd0c1 New APIC support code:
- The apic interrupt entry points have been rewritten so that each entry
  point can serve 32 different vectors.  When the entry is executed, it
  uses one of the 32-bit ISR registers to determine which vector in its
  assigned range was triggered.  Thus, the apic code can support 159
  different interrupt vectors with only 5 entry points.
- We now always to disable the local APIC to work around an errata in
  certain PPros and then re-enable it again if we decide to use the APICs
  to route interrupts.
- We no longer map IO APICs or local APICs using special page table
  entries.  Instead, we just use pmap_mapdev().  We also no longer
  export the virtual address of the local APIC as a global symbol to
  the rest of the system, but only in local_apic.c.  To aid this, the
  APIC ID of each CPU is exported as a per-CPU variable.
- Interrupt sources are provided for each intpin on each IO APIC.
  Currently, each source is given a unique interrupt vector meaning that
  PCI interrupts are not shared on most machines with an I/O APIC.
  That mapping for interrupt sources to interrupt vectors is up to the
  APIC enumerator driver however.
- We no longer probe to see if we need to use mixed mode to route IRQ 0,
  instead we always use mixed mode to route IRQ 0 for now.  This can be
  disabled via the 'NO_MIXED_MODE' kernel option.
- The npx(4) driver now always probes to see if a built-in FPU is present
  since this test can now be performed with the new APIC code.  However,
  an SMP kernel will panic if there is more than one CPU and a built-in
  FPU is not found.
- PCI interrupts are now properly routed when using APICs to route
  interrupts, so remove the hack to psuedo-route interrupts when the
  intpin register was read.
- The apic.h header was moved to apicreg.h and a new apicvar.h header
  that declares the APIs used by the new APIC code was added.
2003-11-03 21:53:38 +00:00
John Baldwin
221111f6f2 Lower the priority of the legacy host to pci bridge driver so that other
non-ACPI host-bridge drivers can preempt this driver.
2003-10-31 21:00:37 +00:00
Mike Silbersack
184dcdc7c8 Change all SYSCTLS which are readonly and have a related TUNABLE
from CTLFLAG_RD to CTLFLAG_RDTUN so that sysctl(8) can provide
more useful error messages.
2003-10-21 18:28:36 +00:00
John Baldwin
810cb9ef5e We represent PCI intpin's two different ways. One is the way that the
intpin register is expressed in hardware where 0 means none, 1 means INTA,
2 INTB, etc.  The other way is commonly used in loops where 0 means INTA,
1 means INTB, etc.  The matchpin argument to pci_cfgintr_search() is
supposed to be the first form, but we passsed in a loop index of the
second.  This fix adds one to the loop index to convert to the first form.

Reported by:	Pavlin Radoslavov <pavlin@icir.org>
2003-09-10 06:00:53 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
Warner Losh
19b7ffd1b8 Prefer new location of pci include files (which have only been in the
tree for two or more years now), except in a few places where there's
code to be compatible with older versions of FreeBSD.
2003-08-22 07:20:27 +00:00
Yoshihiro Takahashi
126ef7fcd6 PC98 uses different mask of IRQ. 2003-08-02 05:14:17 +00:00
Warner Losh
353adf7e7f The MI code was modified to filter the devices based on its header
type.  We know about header types 0, 1 and 2.  Ignore the rest in the
MD i386 code when we're looking for bridges.  You cannot look at the
vendor tag.  And if you don't you certainly can't look at function > 0
if the device isn't there.

The new soekris boards' GEODE cpu has issues with the old way.  This
is reported to have fixed it.

MFC After: 2 days
2003-08-01 21:50:09 +00:00
Warner Losh
e86bd39aab Add hw.pci.irq_override_mask, which is a mask of interrupts that are
considered to be good to try when it otherwise has no clue about which
interrupts to try.  This is a band-aide and we really should try to
balance the IRQs that we arbitrarily pick, but it should help some
people that would otherwise get bad IRQs.
2003-08-01 21:31:36 +00:00
John Baldwin
ba40a03417 - Rename nexus_pcib to legacy_pcib. I've been meaning to do this for a
while after the legacy device was added since this driver hangs from
  legacy and not nexus.
- Make several methods non-static so they can be reused in a mptable
  host -> pci bridge driver that will be added at a later date.
- Let legacy_pcib() use pcibios_pcib_route_interrupt() directly instead of
  wrapping it in a private function.  Originally, I thought I was going to
  have the nexus_pcib() driver make a runtime APIC vs. 8259A check and call
  the appropriate routing method (MPTable vs. PIR) that way, but it ended
  up being cleaner to make nexus_pcib() just work with PIR and have a
  separate host -> pci bridge driver for the mptable/apic case.
2003-06-06 17:56:30 +00:00
John Baldwin
cdd83b0ad1 Use the secondary bus number instead of the number of the bus the PCI-PCI
bridge lives on (i.e., the parent bus) when probing the PIR table for a
bus.  This could cause the PCIBIOS PCI-PCI bridge driver to bogusly attach
to bridges that weren't in the PIR but whose parent bus was in the PIR.
2003-06-06 17:27:18 +00:00
David E. O'Brien
71c5a90130 Use __FBSDID(). 2003-06-02 17:01:49 +00:00
Poul-Henning Kamp
d6b602d4b2 Remove unused variable.
Found by:       FlexeLint
2003-05-31 18:55:18 +00:00
Peter Wemm
af3d516f55 Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been
#if'ed out for a while.  Complete the deed and tidy up some other bits.

We need to be able to call this stuff from outer edges of interrupt
handlers for devices that have the ISR bits in pci config space.  Making
the bios code mpsafe was just too hairy.  We had also stubbed it out some
time ago due to there simply being too much brokenness in too many systems.
This adds a leaf lock so that it is safe to use pci_read_config() and
pci_write_config() from interrupt handlers.  We still will use pcibios
to do interrupt routing if there is no acpi.. [yes, I tested this]

Briefly glanced at by:  imp
2003-02-18 03:36:49 +00:00
Poul-Henning Kamp
152e80d952 Outdent the string rather than use concatenation. 2002-12-23 22:12:17 +00:00
Warner Losh
a4bbd12ff1 MFp4:
o Fix small style nit.  This was supposed to be part of the last batch of
  style fixes, but somehow didn't get merged.
2002-11-14 05:22:37 +00:00
Peter Wemm
41f778bb99 Recognize the Serverworks CIOB30 host to pci bridge. 2002-11-13 21:30:44 +00:00
Warner Losh
ce494452fe MFp4:
o It turns out that we always need to try to route the interrupts for
  the case where the $PIR tells us there can be only one.  Some machines
  require this, while others fail when we try to do this (bogusly, imho).
  Since we have no apriori way of knowing which is which, we always try to
  do the routing and hope for the best if things fail.
o Add some additional comments that state the obvious, but amplify it in
  non-obvious ways (judging from the questions I've gotten).

This should un-break older laptops that still have to use PCIBIOS to route
interrupts.

Tested by: sam
2002-11-02 22:35:24 +00:00
Warner Losh
984de797ff Use 0xffffffff instead of -1 for id to compare against.
Use exact width types, since this is a MD file and won't be used elsewhere.
Fix a couple of resulting printf breakages

Bug found by: phk using Flexlint
2002-11-02 22:32:04 +00:00
Poul-Henning Kamp
7f30cdf366 Revert last commit, there actually was a -1 waaaaay down in pcireg_cfgread(). 2002-10-20 17:54:17 +00:00
Poul-Henning Kamp
a67ee49294 "id" is never going to be -1 when it is unsigned.
Spotted by:	FlexeLint
2002-10-20 17:21:43 +00:00
John Baldwin
a73f15c7a8 Use the global pcib devclass instead of our own static copy. 2002-10-16 18:38:35 +00:00
Warner Losh
ea5420299c o go ahead and route the interupt, even if it is supposedly unique.
there are some strange machines that seem to need this.
o delete bogus comment.
o don't use the the bios for read/writing config space.  They interact badly
  with SMP and being called from ISR.  This brings -current in line with
  -stable.

# make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we
# need to go back in a hurry.
2002-10-07 05:15:05 +00:00
Mitsuru IWASAKI
2f00e60504 Add 2 Ids for new ServerWorks host to PCI bridge chipset.
These are still unknown name but these are working as well
as the other ServerWorks chipset.
Description strings should be corrected when the chipsets
are known.

MFC after:	1 week
2002-10-02 17:50:38 +00:00
Poul-Henning Kamp
cb8e433232 Don't call function in return() for a void function. 2002-09-28 17:36:29 +00:00