least the audio codec driver currently in review.
Submitted by: Jared McNeill <jmcneill@invisible.ca>
Differential Revision: https://reviews.freebsd.org/D5050
with this and an Allwinner SoC to power off.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4954
Marvell twsi part, however uses different register locations, as such split
the existing driver into Marvell and Allwinner attachments.
While here clean a few style issues.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4846
* Use the Linux compat string
* Use EARLY_DRIVER_MODULE to attach at the right time
* Add a generic A10 kernel config file
* A20 now use generic_timer
* Add two new dts files for Olimex boards
* Update our custom DTS file for A10 and A20 to use the same compatible
property names as the vendor ones.
Submitted by: Emmanuel Vadot <manu@bidouilliste.com>
Differential Revision: https://reviews.freebsd.org/D4792
which return -1 as well as on tier 1 archs. Remove block_userspace_access
used only in these implementations.
(1) These functions may be called in interrupt context and pcb_onfault
can be already set in this time. Thus, prior pcb_onfault must be saved
and restored afterwards.
(2) The check that an abort came either from nested interrupt or while
in critical section or holding not sleepable lock must be avoided for
this case.
These functions are called only for profiling reason, so there will be
only small gain by making the code more complex.
(1) Move cnt.v_trap increment to the beginning. There is cnt.v_vm_faults
counter in vm_fault(), so a number of hardware emulation aborts may be
get roughly as difference.
(2) Move kdb_reenter() up to not be ignored if pmap_fault() has failed.
(3) Update comments.
It turned out that devmap.c is not only file in which PTE_DEVICE
is used and simultaneously, built for both armv4 and armv6 platforms.
When I tried to build all arm kernels before r295168 commit, it was
hid by some other local changes in my tree. I hope that this is just
temporary workaround before VM_MEMATTR_DEVICE could be used instead of
PTE_DEVICE outside of pmap code for __ARM_ARCH < 6.
instead of hiding behind pmap_map_chunk(). It's not longer needed
after old pmap-v6 code was removed.
For compatibility with __ARM_ARCH < 6, define PTE_DEVICE in devmap.c
file. Certainly, it would be nice if VM_MEMATTR_DEVICE could be used
even for __ARM_ARCH < 6.
do not depend on pmap internals. This is a preparation for hiding
internal pmap definitions as much as possible from the rest of system.
Simultaneously, the protection argument evaluation is fixed. Happily,
it did not effect the mappings. And it's the reason why it was not fixed
earlier.
function is only called from vm_page_startup() and vm_reserv_startup().
I.e. during vm subsystem initialization. As VM_PROT_WRITE is always
used in these calls, the typo did not have any effect. Likely, it's
the reason why it wasn't discovered so long.
Use driver settable callbacks for handling of:
- core post reset
- reading actual port speed
Typically, OTG enabled EHCI cores wants setting of USBMODE register,
but this register is not defined in EHCI specification and different
cores can have it on different offset.
Also, for cores with TT extension, actual port speed must be determinable.
But again, EHCI specification not covers this so this patch provides
function for two most common variant of speed bits layout.
Reviewed by: hselasky
Differential Revision: https://reviews.freebsd.org/D5088
Use per-CPU structure to store HW watchpoints registers state
for each CPU present in the system. Those registers will be restored
upon wake up from the STOP state if requested by the debug_monitor
code. The method is similar to the one introduced to AMD64.
We store all possible 16 registers for HW watchpoints
(maximum allowed by the architecture).
HW breakpoints are not maintained since they are used for single
stepping only.
Pointed out by: kib
Reviewed by: wma
No strong objections from: kib
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4338
POSIX requires these members to be of type void * rather than the
char * inherited from 4BSD. NetBSD and OpenBSD both changed their
fields to void * back in 1998. No new build failures were reported
via an exp-run.
PR: 206503 (exp-run)
Reviewed by: kib
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D5092
Summary:
Migrate to using the semi-opaque type rman_res_t to specify rman resources. For
now, this is still compatible with u_long.
This is step one in migrating rman to use uintmax_t for resources instead of
u_long.
Going forward, this could feasibly be used to specify architecture-specific
definitions of resource ranges, rather than baking a specific integer type into
the API.
This change has been broken out to facilitate MFC'ing drivers back to 10 without
breaking ABI.
Reviewed By: jhb
Sponsored by: Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5075
in elf_cpu_load_file(). The only time when the sync is needed is after
kernel module is loaded and the relocation info is processed. And it's
done in elf_cpu_load_file().
This allows, for example, UEFI pass a memory map with some ram in this
region, but for us to ignore it. This is the case when running under the
qemu virt machine type.
Sponsored by: ABT Systems Ltd
Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.
HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.
Reviewed by: imp
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037
Even if data cache maintenance was done by IO code, the relocation
fixup process creates dirty cache entries that we must write back
before doing icache sync.
Reported by: Thiagarajan Venkatasubramanian <tvenkata at juniper.net>
Reviewed by: ian
pmap implementations on ARM. This way minidump code can be used without
any platform specific modification.
Also, this is the last piece missing for ARM_NEW_PMAP.
Differential Revision: https://reviews.freebsd.org/D5023
* Use the ARM PLATFORM framework
* Use ARM_INTRNG on teh A20 as it has a GICv2
* Add a method to find which Allwinner SoC we are running on
Differential Revision: https://reviews.freebsd.org/D5059
This is a stub for PMSU driver. Note that it cannot be used to set the
secondary core boot address during attach because drivers are attached
later than SI_SUB_CPU sysinit where cores are started.
Setting the boot address should be done manually in platform_mp_start_ap().
SMP is working fine with this commit and was enabled in Armada38x kernel
configuration file.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4427
- Add file sys/arm/mv/armada38x/armada38x_mp.c
- Set mp_maxid and mp_ncpus based on FDT unless SCU register indicates
only one core
- Boot CPU1 in platform_mp_start_ap()
- IPI range defined
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4426
CPU1 is halted in bootROM code while it is waiting to be released.
Memory window to bootROM must be opened before booting the core.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4425
With this commit, watchdog is supported only in case of having
"mrvl,has-wdt" property or dedicated for watchdog compatibility field
("marvell,armada-380-wdt"). There is no need to modify dts files,
as "has-wdt" property already exists.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4424
A38X watchdog support was implemented in sys/arm/mv/timer.c driver.
It required following modifications:
- add "marvell,armada-380-wdt" compatibility, which supports only watchdog
- correct and enhance definitions related to timer control register
- unmask reset capability in RSTOUTn_MASK register
- use dedicated watchdog timer on A38X instead of second timer
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4423
New driver registers RTC as system clock. New RTC resolution is 1 sec.
Settime and gettime functions were implemented.
Reviewed by: andrew, ian
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Jan Dabros <jsd@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4421
Invalid (in FreeBSD) definition of PCI controller was
replaced with another one, working in FreeBSD environment.
PCI controller's entry had to move from its parent node
so as to be recognized properly by FBSD.
PCI was enabled in kernel configuration file.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4379
mv_pci driver omitted slot 0, which can be valid device on Armada38x.
New mechanism detects if device is root link, basing on vendor's
and device's IDs.
It is restricted to Armada38x; on other machines, behaviour remains
the same.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4377
Add conditions corresponding to Armada38x-based SoCs,
enhancing their remap capabilities.
This is required for PCIe to work properly.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4376
With this commit, USB 2.0 works fine on Armada38x platforms.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4375
Add gic_decode_fdt function to fdt_pic_table, allowing to recognize GIC
interrupts on Armada38x. SOC_MV_ARMADA38X ifdef is required because A38X
is the only Marvell's platform in FreeBSD using GIC; lack of ifdef would
lead to linking errors on other platforms.
Reviewed by: andrew, ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4214
Strict compatibility requirement is a root of problems when simplebus'
node has two compatibility strings (i.e. on Armada38x). Removing this
requirement should not interfere with other platforms.
fdt_is_compatible_strict() and fdt_find_compatible() calls were changed
in fdt_common.c and mv_common.c.
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4602
This commit introduces initial support for Marvell Armada38x platform.
Changes:
- Add common DTS files for Armada38x SoCs and DTS file for A388-GP
- Add ARMADA38X kernel configuration
- Add option SOC_MV_ARMADA38X and set MV_PCI_PORTS
- Add list of files to compile
- Implement get_tclk(), get_sar_value(), cpu_reset() functions
- Add CPU ID and SoC numbers
- Correct ifdefs in arm/mv/timer.c
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4210
Including arm/mv/gpio.c now depends on 'gpio' device. 'device gpio' was
added to all kernconf files of Marvell boards, except ARMADAXP (dummy
mv_gpio_res definition was removed) and ARMADA38X (not supported yet).
This commit allows to use generic files.mv on A38X.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4372
underflow when we have small blocks of memory at the start and end of the
32-bit address range.
While here, only insert mappings pointing at a non-zero amount of memory.
Sponsored by: ABT Systems Ltd
problem affects revision 1xx hardware as well as later versions. Also, the
recommended workaround is to set the PDC count register for a 12-byte
transfer when the actual size is less than that, but there is no need to
extend or zero-out the data buffer, because the blklen register contains
the real transfer size and only that many bytes will be transferred.
Also add a sysctl to turn debugging printfs on or off on the fly.
problem that led to this temporary workaround (and also so I can properly
cite the PR in the commit this time).
In general this is intended to be a temporary workaround until we can figure
out why including any ram from the last megabyte of the physical address
space leads to a NULL pointer deref. Debugging that is made trickier by the
fact that I couldn't even get a backtrace in ddb.
PR: 201614
to generate the phys_avail and dump_avail arrays.
This is a partial fix for the kernel side of the problem mentioned in the
PR. This part handles the cases where comparing start and end addresses of
a block would fail because 32-bit wrap caused the end address to come out
zero if the end of the region is the end of the address space (0xffffffff
with 32-bit vm_paddr_t, but now the code should also work right if we ever
support LPAE with 36-bit addresses).
More work is necessary to make systems with ram at the end of the physical
address space usable, but at least initially it's going to be more like a
workaround than a fix, so this non-hacky part is being committed first.
PR: 201614
providing compiled-in static environment data that is used instead of any
data passed in from a boot loader.
Previously 'env' worked only on i386 and arm xscale systems, because it
required the MD startup code to examine the global envmode variable and
decide whether to use static_env or an environment obtained from the boot
loader, and set the global kern_envp accordingly. Most startup code wasn't
doing so. Making things even more complex, some mips startup code uses an
alternate scheme that involves calling init_static_kenv() to pass an empty
buffer and its size, then uses a series of kern_setenv() calls to populate
that buffer.
Now all MD startup code calls init_static_kenv(), and that routine provides
a single point where envmode is checked and the decision is made whether to
use the compiled-in static_kenv or the values provided by the MD code.
The routine also continues to serve its original purpose for mips; if a
non-zero buffer size is passed the routine installs the empty buffer ready
to accept kern_setenv() values. Now if the size is zero, the provided buffer
full of existing env data is installed. A NULL pointer can be passed if the
boot loader provides no env data; this allows the static env to be installed
if envmode is set to do so.
Most of the work here is a near-mechanical change to call the init function
instead of directly setting kern_envp. A notable exception is in xen/pv.c;
that code was originally installing a buffer full of preformatted env data
along with its non-zero size (like mips code does), which would have allowed
kern_setenv() calls to wipe out the preformatted data. Now it passes a zero
for the size so that the buffer of data it installs is treated as
non-writeable.
- Map all 4GB as VA=PA so that args passed in from a bootloader can
be accessed regardless of where they are.
- Figure out the kernel load address by directly masking the PC rather
then by doing pc-relative math on the _start symbol.
- For EARLY_PRINTF support, map device memory as uncacheable (no-op for
ARM_NEW_PMAP because all TEX types resolve to uncacheable).
Current functionality is somewhat limited: driver assumes that there
is only one active IPU unit (IPU1) and that video output is DI0 and
video mode is 1024x768. For more advanced functionality driver requires
proper clock management which is work in progress. At the moment driver
assumes that pixel clock is configured by u-boot for 1026x768 mode.
Reviewed by: andrew, ian, mmel
Differential Revision: https://reviews.freebsd.org/D4168
into a new function that other platforms can share.
This creates a new ofw_reg_to_paddr() function (in a new ofw_subr.c file)
that contains most of the existing ppc implementation, mostly unchanged.
The ppc code now calls the new MI code from the MD code, then creates a
ppc-specific bus_space mapping from the results. The new arm implementation
does the same in an arm-specific way.
This also moves the declaration of OF_decode_addr() from ofw_machdep.h to
openfirm.h, except on sparc64 which uses a different function signature.
This will help all FDT platforms to set up early console access using
OF_decode_addr().
match the physical load address. Remove the *PHYSADDR symbols which are no
longer necessary.
Also remove a bunch of comments, most of which which have been wrong for
quite some time now, and the rest of which are mooted by these changes. All
that's left in this file is assigning a single symbol to its cannonical
value, not much to comment on anymore.
This eliminates the reliance on PHYSADDR and KERNPHYSADDR compile-time
symbols (except when the rom-copy code is enabled) by using the current
PC and the assumption that the entry-point routine is in the first 1MB
section of the text segment.
Other cleanups done:
- Reduce the initarm() stack size back to 2K. It got increased to
4 * 2K when this file was supporting multicore armv6, but that
support is now in locore-v6.S.
- When building the temporary startup page tables, map the entire
4GB address space as VA=PA before mapping the kernel at its loaded
location. This allows access to boot parameters stored somewhere
in ram by the bootloader, regardless of where that may be.
- When building the page table entry for supporting EARLY_PRINTF, map
the section as uncached unbuffered, since it is presumably device
registers.
Note that this restores the ability to use loader(8)/ubldr on armv4/5
kernels. That was broken in r283035, the point at which ubldr started
loading an arm kernel at any 2MB boundary.
Also note that after this, there is no reason to set KERNVIRTADDR to
anything other than 0xc0000000, and no need for PHYSADDR or KERNPHYSADDR
symbols at all.
Some applications (e.g. Kodi) use tvservice APIs to manage HDMI
modes, power state, EDID etc. directly through VideoCore. After
these manipulations VideoCore may loose its state and needs to be
resynced with ARM. Under Linux this problem is worked around using
fbset utility that recreates framebuffer. Since there is no fbset
utility in FreeBSD we provide sysctl for userland apps to get system
back into normal mode.
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
I don't know what alternate universe I was inhabiting when I wrote it
originally, but apparently the basic workings of mathematics were different
than in this universe. I also can't explain how it ever worked, except "by
accident", because completely bogus values were being written into the
divisor register.
(1) The pmap argument passed to the function must be current pmap only.
(2) The process must be single threaded as the function is called either
when a process is exiting or from exec_new_vmspace().
Remove pmap_tlb_flush_ng() which is not used anywhere now.
Approved by: kib (mentor)
in pmap_remove_pages().
Some points were considered:
(1) There is no range TLB flush cp15 function.
(2) There is no target selection for hardware TLB flush broadcasting.
(3) Some memory ranges could be mapped sparsely.
(4) Some memory ranges could be quite large.
Tested by buildworld on RPi2 and Jetson TK1, i.e. 4 core platforms.
It turned out that the buildworld time is faster. On the other hand,
when the postponed TLB flush was also removed from pmap_remove_pages(),
the result was worse. But pmap_remove_pages() is called for removing
all user mapping from a process, thus it's quite expected.
Note that the postponed TLB flushes came here from i386 pmap where
hardware TLB flush broadcasting is not available.
Approved by: kib (mentor)
This fixes an issue observed on Cortex A7 (RPi2) and on Cortex A15
(Jetson TK1) causing various memory corruptions. It turned out that
even L2 page table with no valid mapping might be a subject of such
caching.
Note that not all platforms have intermediate TLB caching implemented.
An open question is if this fix is sufficient for all platforms with
this feature.
Approved by: kib (mentor)
These helper functions can be used to read in or write a buffer from or to
an arbitrary process' address space. Without them, this can only be done
using proc_rwmem(), which requires the caller to fill out a uio. This is
onerous and results in code duplication; the new functions provide a simpler
interface which is sufficient for most existing callers of proc_rwmem().
This change also adds a manual page for proc_rwmem() and the new functions.
Reviewed by: jhb, kib
Differential Revision: https://reviews.freebsd.org/D4245
clock_gettime(2) on ARMv7 and ARMv8 systems which have architectural
generic timer hardware. It is similar how the RDTSC timer is used in
userspace on x86.
Fix a permission problem where generic timer access from EL0 (or
userspace on v7) was not properly initialized on APs.
For ARMv7, mark the stack non-executable. The shared page is added for
all arms (including ARMv8 64bit), and the signal trampoline code is
moved to the page.
Reviewed by: andrew
Discussed with: emaste, mmel
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D4209
Boundary Trace to assembly to reduce the overhead of these checks.
Submitted by: Howard Su <howard0su@gmail.com>
Relnotes: Yes
Differential Revision: https://reviews.freebsd.org/D4266
This fixes detection of root interrupt controller for cases,
when interrupt parent is not defined at all or it's not defined directly
in controller node.
Approved by: kib (mentor)
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
VM_MEMATTR_WRITE_BACK, it's used in DRM code
Note:
Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
WT requests is treated as uncacheable.
Approved by: kib (mentor)
sysent.
sv_prepsyscall is unused.
sv_sigsize and sv_sigtbl translate signal number from the FreeBSD
namespace into the ABI domain. It is only utilized on i386 for iBCS2
binaries. The issue with this approach is that signals for iBCS2 were
delivered with the FreeBSD signal frame layout, which does not follow
iBCS2. The same note is true for any other potential user if
sv_sigtbl. In other words, if ABI needs signal number translation, it
really needs custom sv_sendsig method instead.
Sponsored by: The FreeBSD Foundation
so that code shared between imx5 and imx6 can work with OIDs under that node.
Add last_reset_status (integer) and last_reset_reason (string) OIDs that
provide info about the last chip reset (power-on, software reset, watchdog
timeout).
Replace tlb_flush_local() by tlb_flush() as even not global mappings
could be fetched to TLB(s) on other cores by speculative table walk.
From OS point of view, it was not a problem as either such mappings
were not used anymore or they were flushed from TLB(s) when reused.
However, from hardware point of view, it was a problem. Not flushed
mappings could be a target for speculative reads or prefetches (which
might be quite aggresive on ARM cores). As speculative read can fill
cacheline, it can cause a real problem, when physical page is reused,
but mapped with different memory attributes.
Anyhow, it's good to have only valid mappings in TLB(s).
Approved by: kib (mentor)
of the SRS (software reset) bit in the watchdog control register. Despite
what the manual seems to imply, this bit DOES trigger an immediate reset, as
opposed to simply flagging the type of reset as software-triggered.
created for bus_dma_tag_t tag, bounce pages should be allocated
only if needed.
Before the fix, they were allocated always if BUS_DMA_COULD_BOUNCE flag
was set but BUS_DMA_MIN_ALLOC_COMP not. As bounce pages are never freed,
it could cause memory exhaustion when a lot of such tags together with
their maps were created.
Note that there could be more maps in one tag by current design.
However BUS_DMA_MIN_ALLOC_COMP flag is tag's flag. It's set after
bounce pages are allocated. Thus, they are allocated only for first
tag's map which needs them.
Approved by: kib (mentor)
Drivers can request DMA to buffers that are not in memory represented
in the vm page arrays. Because of this, store KVA of already mapped
buffer to synclist and use it in dma_dcache_sync().
Reviewed by: jah
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4120
This structure must be binary compatible regardless of PMAP
version being used. Create reserved section for NEW_PMAP to
make other variables be placed exactly in the same memory
addresses. This fixes kgdb/gdb behavoiur, which uses pcb.h stuctures.
The NEW_PMAP is kernel flag, so it does not propagate to the buildworld,
what makes the tools using pcb.h unable to parse PCB data.
Reviewed by: mmel, kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4011
Use proper size of exynos_ehci_softc, not the generic one.
Reviewed by: andrew
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4189
Zybo needs its own DTB and has a different PHY, so add it to
the base kernel. Details on building bootable SD images at
http://www.thomasskibo.com/zedbsd/
Submitted By: Thomas Skibo
since it isn't used for my application. Add back the md device since
it's needed for NanoBSD support. Add in many of the small memory
footprint options from the access points.
With these changes we go from having ~8MB to having ~20MB free,
though free + inactive only goes from ~35MB to ~42MB. We can
also boot a nanobsd image mostly (I had to hand tweak what was
built to represent the final goal).
Move the FDT stuff to the top. We're almost ready to pull the trigger
to moving over to FDT, but something in the MCI driver is freaking out
when we do and that needs fixing first.
Allow manipulation with PSR_A bit on ARMv6+.
Remove declaration of unused functions.
This effectively enables asynchronous aborts on early bootstrap stage,
which previously was not enabled due to an error in enable_interrupts().
PR: 201434
Reported by: Gregory Soutade <soutade at gmail.com>
Approved by: kib (mentor)
function which checks an address for privileged (PL1) write access.
The function is inlined so it does not bring any cost, but makes
function set for checking privileged access complete.
Approved by: kib (mentor)
little-endian configuration for 64-bit variant is supported.
Reviewed by: mmel
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D4113
- boot page table is not allocated in data section, so must be
cleared before use
- map only one section (1 MB) for SOCDEV mapping (*)
- DSB must be used for ensuring of finishing TLB operations
- Invalidate BTB when appropriate
PR: 198360
Reported by: Daisuke Aoyama <aoyama at peach.ne.jp> (*)
Approved by: kib (mentor)
as of r288992 use it to manage the CCNT.
Use the CNNT for get_cyclecount() instead of binuptime() when device pmu
is compiled in; if it fails to attach, fall back to the former method.
Enable by default for the BeagleBoneBlack configuration.
Optained from: Cambridge/L41
Sponsored by: DARPA/AFRL
Reviewed by: andrew
Differential Revision: https://reviews.freebsd.org/D3837
variable during mp_start() which is too late. Move this to mp_setmaxid()
where other architectures set it and move x86 assertions to MI code.
Reviewed by: kib (x86 part)
"rmii", use rmii mode for the MAC, otherwise use MII mode. The code is
somewhat duplicated between these drivers for this.
Also, add AT91RM9200 compatibility strings to the ate driver. In the
future, there's a good chance that ate will lose the MACB support and
only attach to the AT91RM9200 EMAC device since the macb works now
that RMII support has been added to it.
driver. This is taken from the MAC at boot, but can be overridden with
'options AT91_MACB_USE_RMII'.
Switch to macb for HL201 and SAM9G20EK boards. It now works both
places. Also start to sneak up on FDT for the SAM9G20EK board, but
leave disabled due to issues with MMC that haven't been resolved.
Add early debug support for the SAM9G20EK since that is required
for FDT to work presently on these SoC.
interrupt status register to process shared interrupts only if the bit
is active and only on core to which they are routed.
Reviewed by: imp, loos
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D3723
- Add bcm2835_mbox_property for generic property request, it accepts
pointer to prepared property chan message and its size, forwards
it to MBOX and copies result back
- Make all bcm2835_mbox_XXX functions that use property channel go
through bcm2835_mbox_property path. Do not accept device_t as
an argument, it's not required: all DMA operatiosn should go
through mbox device, and all API consumers should report errors
on their side.
DEX bit is set to 1 and exception raised whenever vectorized operation is
attempted on the VFP implementation that does not support it (i.e. on Cortex A7)
In the old days, device drivers passed NULL for the parent tag when creating
a new tag, and on arm platforms that resulted in a global tag representing
overall platform constraints being substituted in the busdma code. Now all
drivers use bus_get_dma_tag() and if there is a need to represent overall
platform constraints they will be inherited from a tag supplied by nexus or
some bus driver in the hierarchy.
The only arm platforms still relying on the old global-tag scheme were some
xscale boards with special PCI-bus constraints. This change provides those
constraints through a tag supplied by the xscale PCI bus driver, and
eliminates the few remaining references to the old global var.
Reviewed by: cognet
Previous code supported only "continuous" code without any kind of
branch instructions. To change that, new function was implemented
which parses current instruction and returns an addres where
the jump might happen (alternative addr).
mdthread structure was extended to support two breakpoints
(one directly below current instruction and the second placed
at the alternative location).
One of them must trigger regardless the instruction has or has not been
executed due to condition field.
Upon cleanup, both software breakpoints are removed.
This implementation parses only the most common instructions
that are present in the code (like 99.99% of all), but there
is a chance there are some left, not covered by the parsing routine.
Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2
support is provided.
Reviewed by: kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4021
receives video memory address from VideoCore through property mailbox
channel. Older versions of firmware (and the one that is currently part
of sysutils/u-boot-rpi and sysutils/u-boot-rpi2) returned real physical
address, newer one returns VideoCore bus address, so we need to convert
it to actual physical address. this version works with both older and
newer interface.
point, e.g. on RaspberryPi 2 when control is passed from loader to kernel
it contains garbage. So we use cpsr as a base for new cpsr value: if we
have reached this point it means current value is OK
Reviewed by: andrew
This commit introduces support for etherswitch devices that utilize SMI as
a way of accessing its registers. SMI register is located in address space
of mge -- access to it was exported through MDIO interface.
Attachment functions were enhanced so as to ensure proper initialisation
in both cases: 1) PHYs attached directly to mge, 2) PHYs attached to
switch device and switch attached to mge. Attachment of etherswitch device
depends on dts entry with compatible="mrvl,sw" property. If none is found,
typical PHY attachment procedure follows.
In case of switch attached, PHYs' status and configuration is accessible
via etherswitchcfg, and ifconfig shows always-up, non-configurable mge
interfaces.
Due to the fact that there may be simultaneous accessess to SMI
registers (e.g. from PHY attached to one of mge instances and switch
to the other), SMI access interlock was added. It is SX lock,
because sleep ability is necessary -- busy-waiting would result
in poor performance due to long delays required by hardware.
Underlying switch driver is obliged to use sleepable locks as well.
Reviewed by: adrian
Obtained from: Semihalf
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D3900
is a dcache invalidate to point of coherency just like dcache_inv_poc(), but
a slightly different version specific to dma operations. Elaborate the
comment about how and why it's different.
per-map. The per-tag scheme is not safe, and a mutex can't be used to
protect it because the mapping routines can't sleep. Code brought in
from armv6 implementation.
The goal is to make these two files cosmetically alike so that the actual
implementation differences are visible. The only changes which aren't
spaces<->tabs and rewrapping and reindenting lines are a couple fields
shuffled around in the tag and map structs so that everything is in the same
order in both versions (which should amount to no functional change).
Similar to r286787 for x86, this treats userspace buffers the same as unmapped buffers and no longer borrows the UVA for sync operations.
Submitted by: Svatopluk Kraus <onwahe@gmail.com> (earlier revision)
Tested by: Svatopluk Kraus
Differential Revision: https://reviews.freebsd.org/D3869
represented in 7-bits format in DT files, but system expect it in 8-bit
format. Also, fix two drivers that locally hack around this bug.
Submitted by: Michal Meloun <meloun@miracle.cz>
the not-SMP case. This is safe because arm_irq_next_cpu() will return
the cpuid of the current/only core in the not-SMP case.
Submitted by: Bartosz Szczepanek @ semihalf
Normally this routine is supposed to loop until the PIC returns a "no more
interrupts pending" indication. I had commented that out to do just one
interrupt per invokation to do some timing tests.
Spotted by: Svata Kraus
Pointy Hat: ian
The bits in the aux control register vary based on the processor type. In
the past we've always just set the 'smp' and "broadcast tlb/cache ops' bits,
which worked fine for the first few SoCs we supported. Now that we support
most of the cortex-a series processors, it's important to get the right bits
set based on the processor type.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
The interrupts-extended property is a list of controller-specific
interrupt tuples for more than one controller. The decode routine of
every PIC gets called in the pre-INTRNG code (nexus doesn't know which
device instance belongs to which fdt node), so the GIC code has to
check each FDT node it is asked to decode to ensure it is the owner.
Because in the pre-INTRNG world there can only be one instance of a GIC,
it's safe to cache the results of a positive lookup in a static variable
to avoid the expensive lookups on subsequent calls.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Differential Revision: https://reviews.freebsd.org/D2345
interrupt controller.
The latter is required for INTRNG, because of the hardware erratum
workaround installed by the linux folks into the imx6 FDT data, which remaps
an ethernet interrupt to the gpio device. In the non-INTRNG world we
intercept the call to map the interrupt and map it back to the ethernet
hardware (because we don't need linux's workaround), but in the INTRNG world
we lose the hookpoint where that remapping was happening, but we gain the
ability to work the way linux does by having the gpio driver dispatch the
interrupt.
