Commit Graph

15 Commits

Author SHA1 Message Date
John Baldwin
d320e05ca5 Extend the support for PCI-e memory mapped configuration space access:
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the
  rest of the kernel.  It now also accepts parameters via function
  arguments rather than global variables.
- Add a notion of minimum and maximum bus numbers and reject requests for
  an out of range bus.
- Add more range checks on slot/func/reg/bytes parameters to the cfg reg
  read/write routines.  Don't panic on any invalid parameters, just fail
  the request (writes do nothing, reads return -1).  This matches the
  behavior of the other cfg mechanisms.
- Port the memory mapped configuration space access to amd64.  On amd64
  we simply use the direct map (via pmap_mapdev()) for the memory mapped
  window.
- During acpi_attach() just after loading the ACPI tables, check for a
  MCFG table.  If it exists, call pciereg_cfgopen() on each subtable
  (memory mapped window).  For now we only support windows for domain 0
  that start with bus 0.  This removes the need for more chipset-specific
  quirks in the MD code.
- Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets
  since these machines should all have MCFG tables via ACPI.
- Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen()
  earlier.

MFC after:	2 weeks
2008-08-22 02:14:23 +00:00
Warner Losh
b756200647 Move pc98 specific parts to the pc98 specific file. 2005-04-03 23:27:11 +00:00
Warner Losh
86cb007f9f /* -> /*- for copyright notices, minor format tweaks as necessary 2005-01-06 22:18:23 +00:00
John Baldwin
7a64d8d74c - Create a pir0 psuedo device as a child of legacy0 if we attach a legacy
host-PCI bridge device and find a valid $PIR.
- Make pci_pir_parse() private to pci_pir.c and have pir0's attach routine
  call it instead of having legacy_pcib_attach() call it.
- Implement suspend/resume support for the $PIR by giving pir0 a resume
  method that calls the BIOS to reroute each link that was already routed
  before the machine was suspended.
- Dump the state of the routed flag in the links display code.
- If a link's IRQ is set by a tunable, then force that link to be re-routed
  the first time it is used.
- Move the 'Found $PIR' message under bootverbose as the pir0 description
  line lists the number of entries already.  The pir0 line also only shows
  up if we are actually using the $PIR which is a bonus.
- Use BUS_CONFIG_INTR() to ensure that any IRQs used by a PCI link are
  set to level/low trigger/polarity.
2004-05-04 21:17:52 +00:00
John Baldwin
77fa00fa7c Switch to using the new $PIR interrupt routing code and remove the old
code.  The pci_cfgreg.c file now just controls reading/writing PCI config
registers.
2004-02-18 22:41:53 +00:00
John Baldwin
eb975edd06 Fix a busted constant related to PCI configuration acess method #1. The
reserved bits in the port that must be zero are 24:30, not 20:30.  Bits
16:23 are used to set the bus number.  This meant that when we tested for
config mechanism #1, if the previous PCI configuration transaction sent
used a bus number greater than 15, one of the bits in 20:23 would be
non-zero and we would fail to use config mechanism #1 and thus fail to see
that PCI existed on the machine at all.

Obtained from:	Shanley's PCI System Architecture book
Tested by:	des
Proxied through:	njl
2003-09-18 17:00:03 +00:00
Peter Wemm
af3d516f55 Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been
#if'ed out for a while.  Complete the deed and tidy up some other bits.

We need to be able to call this stuff from outer edges of interrupt
handlers for devices that have the ISR bits in pci config space.  Making
the bios code mpsafe was just too hairy.  We had also stubbed it out some
time ago due to there simply being too much brokenness in too many systems.
This adds a leaf lock so that it is safe to use pci_read_config() and
pci_write_config() from interrupt handlers.  We still will use pcibios
to do interrupt routing if there is no acpi.. [yes, I tested this]

Briefly glanced at by:  imp
2003-02-18 03:36:49 +00:00
John Baldwin
c3ba1376f5 Add a function pci_probe_route_table() that returns true if our PCI BIOS
supports interrupt routing and if the specified PCI bus is present in the
routing table.
2002-09-06 22:15:44 +00:00
John Baldwin
8ab96fd8d0 - Add a pci_cfgintr_valid() function to see if a given IRQ is a valid
IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table.
- Change pci_cfgintr() to except the current IRQ of a device as a fourth
  argument and to use that IRQ for the device if it is valid.
- If an intpin entry in a $PIR entry has a link of 0, it means that that
  intpin isn't connected to anything that can trigger an interrupt.  Thus,
  test the link against 0 to find invalid entries in the table instead of
  implicitly relying on the irqs field to be zero.  In the machines I have
  looked at, intpin entries with a link of 0 often have the bits for all
  possible interrupts for PCI devices set.
2002-09-06 17:08:07 +00:00
John Baldwin
4f99a443f0 Function prototypes don't need 'extern'. 2002-09-04 19:31:09 +00:00
Peter Wemm
573be82757 Detect a certain type of PCIBIOS brain damage. For some reason,
some bios vendors took it apon themselves to "censor" the
host->pci bridges from PCIBIOS callers, even when the caller
explicitly asks for them.  This includes certain Compaq machines
(eg: DL360) and some laptops.

If we detect this, shut down pcibios and revert to using IO
port bashing.

Under -current, apcica does a better job anyway.
2001-08-21 03:10:55 +00:00
Warner Losh
29f0d43398 Add types and prototypes.
Submitted by: msmith
2000-10-16 19:49:30 +00:00
Mike Smith
12a02d6efd Move the i386 PCI attachment code out of i386/isa back into i386/pci.
Split out the configuration space access primitives, as these are needed
elsewhere as well.
2000-10-02 07:11:13 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Stefan Eßer
5bec615793 Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00