Commit Graph

189 Commits

Author SHA1 Message Date
Simon J. Gerraty
ccfb965433 Add META_MODE support.
Off by default, build behaves normally.
WITH_META_MODE we get auto objdir creation, the ability to
start build from anywhere in the tree.

Still need to add real targets under targets/ to build packages.

Differential Revision:       D2796
Reviewed by: brooks imp
2015-06-13 19:20:56 +00:00
Ruslan Bukin
3e0bfdd882 o Rework ARMv7 events list using aliases - same way as we have for arm64.
o Extend it with Cortex A9-specific events.
2015-06-10 12:42:30 +00:00
Simon J. Gerraty
44d314f704 dirdeps.mk now sets DEP_RELDIR 2015-06-08 23:35:17 +00:00
Simon J. Gerraty
98e0ffaefb Merge sync of head 2015-05-27 01:19:58 +00:00
John Baldwin
0ceb54c2cf Use fixed enum values for PMC_CLASSES().
This removes one of the frequent causes of ABI breakage when new CPU
types are added to hwpmc(4).

Differential Revision:	https://reviews.freebsd.org/D2586
Reviewed by:	davide, emaste, gnn (earlier version)
MFC after:	2 weeks
2015-05-19 18:58:18 +00:00
Ruslan Bukin
bc88bb2bf3 Add Performance Monitoring Counters support for AArch64.
Family-common and CPU-specific counters implemented.

Supported CPUs: ARM Cortex A53/57/72.

Reviewed by:	andrew, bz, emaste, gnn, jhb
Sponsored by:	ARM Limited
Differential Revision:	https://reviews.freebsd.org/D2555
2015-05-19 15:25:47 +00:00
Joel Dahl
ac074de850 Minor mdoc fixes. 2015-04-20 21:19:26 +00:00
Justin Hibbits
a745246822 Implement hwpmc(4) for Freescale e500 core.
This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the
performance counters are identical across all, with e500mc having some
additional events.

Relnotes:	Yes
2015-04-18 21:39:17 +00:00
Adrian Chadd
f6e6460dfc Add support for the MIPS74K SoC family performance counters events.
These are similar to the mips24k performance counters - some are
available on perfcnt0/3, some are available on perfcnt1/4.
However, the events aren't all the same.

* Add the events, named the same as from Linux oprofile.
* Verify they're the same as  "MIPS32(R) 74KTM Processor Core Family
  Software User's Manual"; Document Number: MD00519; Revision 01.05.
* Rename INSTRUCTIONS to something else, so it doesn't clash with
  the alias INSTRUCTIONS.  I'll try to tidy this up later; there
  are a few other aliases to add and shuffle around.

Tested:

* QCA9558 SoC (AP135 board) - MIPS74Kc core (no FPU.)
* make universe; where it didn't fail for other reasons.

TODO:

* It'd be nice to support the four performance counters
  in at least this hardware, rather than just two.

Reviewed by:	bsdimp ("looks good; don't break world".)
2015-04-05 02:57:02 +00:00
Ryan Stone
bc0ad9a99d Fix Ivy Bridge+ MEM_UOPS_RETIRED counters
The MEM_UOPS_RETIRED actually work the same way as the Sandy
Bridge counters, but the counters were documented in a different
way and that seemed to cause the Ivy Bridge counters to be
implemented incorrectly.  Use the same counter definitions as
Sandy Bridge.  While I'm here, rename the counters to match
what's documented in the datasheet.

Differential Revision:	https://reviews.freebsd.org/D1590
MFC after:	1 month
Sponsored by:	Sandvine Inc.
2015-03-10 01:24:08 +00:00
Ryan Stone
ae9975db34 Use the correct event table for Haswell Xeon events
Differential Revision:	https://reviews.freebsd.org/D1588
MFC after:	1 month
Sponsored by:	Sandvine Inc.
2015-03-10 01:23:55 +00:00
Ryan Stone
9e60f3acd2 Fix Sandy Bridge+ hwpmc branch counters
On Sandy Bridge and later, to count branch-related events you
have to or together a mask indicating the type of branch
instruction to count (e.g. direct jump, branch, etc) and a bits
indicating whether to count taken and not-taken branches.  The
current counter definitions where defining this bits individually,
so the counters never worked and always just counted 0.

Fix the counter definitions to instead contain the proper
combination of masks.  Also update the man pages to reflect the
new counters.

Differential Revision:	https://reviews.freebsd.org/D1587
MFC after:	1 month
Sponsored by:	Sandvine Inc.
2015-03-10 01:23:47 +00:00
Ryan Stone
f1ec0939ec Add manpage for Haswell Xeon pmc implementation
Differential Revision:	https://reviews.freebsd.org/D1584
Reviewed by:	gnn
MFC After:	1 month
Sponsored by:	Sandvine Inc
2015-03-10 01:22:43 +00:00
Ruslan Bukin
6411d14d62 Add ARMv7 performance monitoring counters.
Differential Revision:	https://reviews.freebsd.org/D1687
Reviewed by:	rpaulo
Sponsored by:	DARPA, AFRL
2015-01-28 16:08:07 +00:00
Randall Stewart
d95b3509e1 Update the hwpmc driver to have the new type HASWELL_XEON. Also
go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE
to straighten out all the missing PMCs. We also add a new pmc tool
pmcstudy, this allows one to run the various formulas from
the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for
IB/SB and Haswell. The tool also allows one to postulate your own
formulas with any of the various PMC's. At some point I will enahance
this to work with Brendan Gregg's flame-graphs so we can flamegraph
various PMC interactions. Note the manual page also needs some
work (lots of work) but gnn has committed to help me with that ;-)
Reviewed by: gnn
MFC after:1 month
Sponsored by:	Netflix Inc.
2015-01-14 12:46:58 +00:00
Joel Dahl
73461c24c4 mdoc: sort SEE ALSO. 2015-01-04 12:38:00 +00:00
Simon J. Gerraty
ee7b0571c2 Merge head from 7/28 2014-08-19 06:50:54 +00:00
George V. Neville-Neil
56e397023c Update the list of cross references to include the more modern set of
processors that we now support.
2014-07-28 10:17:41 +00:00
Joel Dahl
df2d82e003 mdoc: remove superfluous paragraph macros. 2014-06-23 18:40:21 +00:00
Baptiste Daroussin
2b7af31cf5 use .Mt to mark up email addresses consistently (part3)
PR:		191174
Submitted by:	Franco Fichtner  <franco at lastsummer.de>
2014-06-23 08:23:05 +00:00
Konstantin Belousov
49fe48ab0c For Xeon 7500 and 48XX (Nehalem EX and Westmere EX) variants of the
Core i7 and Westmere processors, the uncore PMC subsystem is
completely different from the uncore PMC on smaller versions of CPUs.
Disable existing uncore hwpmc code for EX, otherwise non-existing MSRs
are accessed.

The cores PMCs seems to be identical for non-EX and EX, according to
the SDM.

Reviewed by:	davide, fabient
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
2014-06-04 16:06:38 +00:00
Simon J. Gerraty
fae50821ae Updated dependencies 2014-05-16 14:09:51 +00:00
Simon J. Gerraty
76b28ad6ab Updated dependencies 2014-05-10 05:16:28 +00:00
Simon J. Gerraty
9d2ab4a62d Merge head 2014-04-27 08:13:43 +00:00
Hiren Panchasara
e8f021a3f7 Update hwpmc to support core events for Atom Silvermont microarchitecture.
(Model 0x4D as per Intel document 330061-001 01/2014)

Tested by:	Olivier Cochard-Labbe <olivier@cochatrd.me>
MFC after:	4 weeks
2014-03-20 20:51:08 +00:00
Justin Hibbits
169dd953b0 Add hwpmc(4) support for the PowerPC 970 class processors, direct events.
This also fixes asserts on removal of the module for the mpc74xx.

The PowerPC 970 processors have two different types of events: direct events
and indirect events.  Thus far only direct events are supported.  I included
some documentation in the driver on how indirect events work, but support is
for the future.

MFC after:	1 month
2014-02-01 02:03:50 +00:00
Ryan Stone
9b605dd32e pmc(3) does not document a dependency on <sys/types.h> but <pmc.h>
requires it, so include it explicitly from <pmc.h>.

MFC after:	1 month
2013-11-25 18:31:13 +00:00
Simon J. Gerraty
d1d0158641 Merge from head 2013-09-05 20:18:59 +00:00
Ulrich Spörlein
4bbdf74796 Always install pmc.foo(3) manpages.
There is no point in hiding, e.g. pmc.xscale(3) from a developer running
on amd64, when the target arch in question will probably never have
manual pages installed at all.

Reviewed by:	sbruno, hiren
2013-05-03 08:20:10 +00:00
Simon J. Gerraty
69e6d7b75e sync from head 2013-04-12 20:48:55 +00:00
Joel Dahl
4a121e0748 Remove EOL whitespace. 2013-03-29 08:32:49 +00:00
Sean Bruno
cc0c1555d3 Update hwpmc to support Haswell class processors.
0x3C:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2013-03-28 19:15:54 +00:00
Bryan Venteicher
a83639a2e6 Add missing space
MFC after:	3 days
2013-03-27 07:11:29 +00:00
Simon J. Gerraty
7cf3a1c6b2 Updated dependencies 2013-03-11 17:21:52 +00:00
Alexander Motin
1af19ee4a2 Add support for good old 8192Hz profiling clock to software PMC.
Reviewed by:	fabient
2013-02-26 18:13:42 +00:00
Simon J. Gerraty
f5f7c05209 Updated dependencies 2013-02-16 01:23:54 +00:00
David E. O'Brien
d9a447559b Sync with HEAD. 2013-02-08 16:10:16 +00:00
Sean Bruno
3f929d8cdd Update hwpmc to support the Xeon class of Ivybridge processors.
case 0x3E:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

No support for uncore events at this time.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	davide, jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2013-01-31 22:09:53 +00:00
Simon J. Gerraty
7cd2dcf076 Updated/new Makefile.depend 2012-11-08 21:24:17 +00:00
Dimitry Andric
f0bbe9aa78 Fix a few warnings from newer clang 3.2 in libpmc, about comparing enum
pmc_event values against integer constants which fall outside the enum
range.

Reviewed by:	fabient, sbruno
MFC after:	3 days
2012-11-05 18:49:21 +00:00
Simon J. Gerraty
23090366f7 Sync from head 2012-11-04 02:52:03 +00:00
Sean Bruno
cdfd0cc862 Cleanup and rename some variables in libpmc and hwpmc.
Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris@ sbruno@
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
2012-10-24 01:26:29 +00:00
Joel Dahl
ad2f1898bc Remove trailing whitespace. 2012-10-19 18:30:50 +00:00
Sean Bruno
29f79bb342 Update man page crossreferences to sandybridge xeon class
MFC after:	2 weeks
2012-10-19 17:21:10 +00:00
Sean Bruno
fabe02f5f3 Update hwpmc to support the Xeon class of Sandybridge processors.
(Model 0x2D     /* Per Intel document 253669-044US 08/2012. */)

Add manpage to document all the goodness that is available in this
processor model.

No support for uncore events at this time.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris@ fabient@
Obtained from:	Yahoo! Inc.
MFC after:	  2 weeks
2012-10-19 17:01:27 +00:00
Tim Kientzle
5847daf4c2 Fix "make install"
Also make arm the same as other platforms:  Install man
pages for all CPUs in the family.
2012-10-06 17:54:42 +00:00
Joel Dahl
4c7c24efe0 Remove trailing whitespace. 2012-09-06 19:24:48 +00:00
Joel Dahl
a619d8f7a1 Minor mdoc fix. 2012-09-06 19:14:02 +00:00
Fabien Thomas
1e862e5ad0 Add Intel Ivy Bridge support to hwpmc(9).
Update offcore RSP token for Sandy Bridge.
Note: No uncore support.

Will works on Family 6 Model 3a.

MFC after: 1 month
Tested by: bapt, grehan
2012-09-06 13:54:01 +00:00
Marcel Moolenaar
7750ad47a9 Sync FreeBSD's bmake branch with Juniper's internal bmake branch.
Requested by: Simon Gerraty <sjg@juniper.net>
2012-08-22 19:25:57 +00:00