Commit Graph

143 Commits

Author SHA1 Message Date
Davide Italiano
f39e915e19 Disable hwpmc(4) support for Intel Xeon Sandy Bridge (Model 0x2D).
Due to some differences in MSRs between Xeon Sandy Bridge and Core Sandy
Bridge (Model 0x2A), wrmsr() may generate in a GP# fault exception and so a
panic of the machine.

Approved by:		gnn (mentor)
MFC after:		3 days
2012-06-17 13:48:39 +00:00
Fabien Thomas
790fb4edf2 Add ARM callchain support for hwpmc.
Sponsored by: NETASQ
MFC after:	3 days
2012-06-13 06:38:25 +00:00
Fabien Thomas
4cc50ab413 Soft PMC support for ARM.
Callgraph is not captured, only current location.

Sample system wide profiling: "pmcstat -Sclock.hard -T"
2012-05-23 13:23:40 +00:00
Fabien Thomas
eecb732d59 Remove out of date KASSERT that fire with soft PMC.
MFC after:	1 week
2012-05-10 14:27:49 +00:00
George V. Neville-Neil
03963ef8d1 Fix so that ,usr and ,os work correctly with fixed function (IAF)
counters.

MFC after:	1 week
2012-05-02 16:23:36 +00:00
Fabien Thomas
5df02332df Fix class malloc init for mips and powerpc that was not converted
by r233628.

Found by: monthadar, adrian
MFC after:	1 week
2012-04-23 08:58:01 +00:00
Fabien Thomas
f5f9340b98 Add software PMC support.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).

Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.

Sponsored by: NETASQ
MFC after:	1 month
2012-03-28 20:58:30 +00:00
Oleksandr Tymoshenko
ef902782ef Fix crash on VirtualBox (and probably on some real hardware):
- Do not cover error returned by pmc_core_initialize with the
    result of pmc_uncore_initialize, fail right away.
- Give a user something to report instead failing silently

Reported by:	Alexandr Kovalenko <never@nevermind.kiev.ua>
2012-03-27 18:22:14 +00:00
Fabien Thomas
6f33c108f7 Fix random deadlock on pmcstat exit:
- Exit the thread when soft shutdown is requested
- Wakeup owner thread.

Reproduced/tested by looping pmcstat measurement:
pmcstat -S instructions -O/tmp/test ls

MFC after:	1 week
2012-03-27 14:02:22 +00:00
Oleksandr Tymoshenko
4db6447467 Add Octeon PMC hardware backend 2012-03-23 00:09:27 +00:00
Oleksandr Tymoshenko
370df5bc87 Add list of Octeon's PMC counters obtained from cvmx-core.h 2012-03-23 00:04:09 +00:00
Oleksandr Tymoshenko
1b930fb786 Rework MIPS PMC code:
- Replace MIPS24K-specific code with more generic framework that will
    make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
    HWPMC_MIPS_BACKTRACE to override this limitation
2012-03-22 18:01:23 +00:00
Oleksandr Tymoshenko
d43022a1b3 - Remove unncessary type casts
- Make kernel backtrace routine more robust by refusing to backtrace
    further when encountered function that is possibly modifies SP
    value
2012-03-14 23:46:07 +00:00
Adrian Chadd
6a77ff29ff This header file no longer exists when doing cross builds, so remove it.
mips24k hwpmc now compiles again.
2012-03-12 17:25:35 +00:00
Oleksandr Tymoshenko
5fca32c865 Implement pmc_save_user_callchain and pmc_save_kernel_callchain for MIPS 2012-03-12 01:19:41 +00:00
George V. Neville-Neil
a7ef8bbb2f Properly mask off bits that are not supported in the IAP counters.
This fixes a bug where users would see massively large counts, near
to 2**64 -1, due to the bits not being cleared.

MFC after:	3 weeks
2012-03-06 17:17:03 +00:00
Davide Italiano
78d763a29b - Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events)
- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture

Reviewed by:	attilio, brueffer, fabient
Approved by:	gnn (mentor)
MFC after:	3 weeks
2012-03-01 21:23:26 +00:00
Ed Maste
158c4475c8 pmc_*_initialize may return NULL if the CPU is not supported, so check
that md is not null before dereferencing it.

PR:		kern/156540
2012-01-28 01:38:48 +00:00
George V. Neville-Neil
ad71f089ab Clean up a switch statement for uncore events on Westmere processors.
Submitted by:	Davide Italiano
Reviewed by:	gnn
MFC after:	1 week
2012-01-13 17:13:46 +00:00
Fabien Thomas
ba89031aea Update PMC events from October 2011 Intel documentation.
Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	3 days
2012-01-04 07:58:36 +00:00
Fabien Thomas
3444c31af6 Add missing MSR programming for some events.
Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	3 days
2012-01-04 07:33:06 +00:00
Dimitry Andric
b38c0519c5 In sys/dev/hwpmc/hwpmc_amd.c, fix a clang warning about invalid enum
conversions.

Reviewed by:	jkoshy
MFC after:	1 week
2011-12-31 12:37:07 +00:00
Bjoern A. Zeeb
d9667fc69e Quite the tinderbox for the holidays. Remove the assert[1].
Suggested by:	jhibbits [1]
MFC after:	3 days
2011-12-25 14:29:36 +00:00
Justin Hibbits
7b25dcca76 Implement hwpmc counting PMC support for PowerPC G4+ (MPC745x/MPC744x).
Sampling is in progress.

Approved by:	nwhitehorn (mentor)
MFC after:	9.0-RELEASE
2011-12-24 19:34:52 +00:00
Eitan Adler
53113e4db9 - Remove extra space
Submitted by:	Davide Italiano <davide.italiano@gmail.com>
Approved by:	brucec
2011-12-21 17:51:49 +00:00
Fabien Thomas
2dde521a9a There's a small set of events on Nehalem, that are not supported in
processors with CPUID signature 06_1AH, 06_1EH, and 06_1FH.

Refuse to allocate them on unsupported model.

Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	1 month
2011-12-12 13:12:55 +00:00
Fabien Thomas
d2b58b22b5 Update Westmere uncore event exception list.
Submitted by:	Davide Italiano <davide italiano at gmail com>
MFC after:	1 week
2011-12-02 10:02:49 +00:00
Adrian Chadd
009d7740fc Flip on processing interrupt profile events for mips24k.
This is a bit hackish and should be made more generic (ie, support more than
two hard-coded performance counter+config register pairs) so it can be used
for mips74k and other chips.

All this does is process the initial interrupt event. It doesn't (yet) handle
callgraph events, so even if you route the exception/interrupt to this routine
and flip the bit on, it will hang and crash pmc unless you disable callgraph
support when you enable a sample based PMC.
2011-11-09 17:38:27 +00:00
Fabien Thomas
dceed24a7c Add a flush of the current PMC log buffer before displaying the next top.
As the underlying block is 4KB if the PMC throughput is low the measurement
will be reported on the next tick. pmcstat(8) use the modified flush API to
reclaim current buffer before displaying next top.

MFC after:	1 month
2011-10-18 15:25:43 +00:00
Adrian Chadd
cdb59558b9 Begin implementing correct MIPS24K sampling mode behaviour.
* Add the interrupt bit in the configuration register
* Correctly set the counter register for the sampling overflow
  interrupt. The interrupt is asserted when bit 31 is set.
  So set the overflow value at 0x80000000 and subtract the
  programmed value as appropriate.
2011-10-07 06:13:38 +00:00
Kip Macy
8451d0dd78 In order to maximize the re-usability of kernel code in user space this
patch modifies makesyscalls.sh to prefix all of the non-compatibility
calls (e.g. not linux_, freebsd32_) with sys_ and updates the kernel
entry points and all places in the code that use them. It also
fixes an additional name space collision between the kernel function
psignal and the libc function of the same name by renaming the kernel
psignal kern_psignal(). By introducing this change now we will ease future
MFCs that change syscalls.

Reviewed by:	rwatson
Approved by:	re (bz)
2011-09-16 13:58:51 +00:00
Robert Watson
a9d2f8d84f Second-to-last commit implementing Capsicum capabilities in the FreeBSD
kernel for FreeBSD 9.0:

Add a new capability mask argument to fget(9) and friends, allowing system
call code to declare what capabilities are required when an integer file
descriptor is converted into an in-kernel struct file *.  With options
CAPABILITIES compiled into the kernel, this enforces capability
protection; without, this change is effectively a no-op.

Some cases require special handling, such as mmap(2), which must preserve
information about the maximum rights at the time of mapping in the memory
map so that they can later be enforced in mprotect(2) -- this is done by
narrowing the rights in the existing max_protection field used for similar
purposes with file permissions.

In namei(9), we assert that the code is not reached from within capability
mode, as we're not yet ready to enforce namespace capabilities there.
This will follow in a later commit.

Update two capability names: CAP_EVENT and CAP_KEVENT become
CAP_POST_KEVENT and CAP_POLL_KEVENT to more accurately indicate what they
represent.

Approved by:	re (bz)
Submitted by:	jonathan
Sponsored by:	Google Inc
2011-08-11 12:30:23 +00:00
Attilio Rao
71a19bdc64 Commit the support for removing cpumask_t and replacing it directly with
cpuset_t objects.
That is going to offer the underlying support for a simple bump of
MAXCPU and then support for number of cpus > 32 (as it is today).

Right now, cpumask_t is an int, 32 bits on all our supported architecture.
cpumask_t on the other side is implemented as an array of longs, and
easilly extendible by definition.

The architectures touched by this commit are the following:
- amd64
- i386
- pc98
- arm
- ia64
- XEN

while the others are still missing.
Userland is believed to be fully converted with the changes contained
here.

Some technical notes:
- This commit may be considered an ABI nop for all the architectures
  different from amd64 and ia64 (and sparc64 in the future)
- per-cpu members, which are now converted to cpuset_t, needs to be
  accessed avoiding migration, because the size of cpuset_t should be
  considered unknown
- size of cpuset_t objects is different from kernel and userland (this is
  primirally done in order to leave some more space in userland to cope
  with KBI extensions). If you need to access kernel cpuset_t from the
  userland please refer to example in this patch on how to do that
  correctly (kgdb may be a good source, for example).
- Support for other architectures is going to be added soon
- Only MAXCPU for amd64 is bumped now

The patch has been tested by sbruno and Nicholas Esborn on opteron
4 x 12 pack CPUs. More testing on big SMP is expected to came soon.
pluknet tested the patch with his 8-ways on both amd64 and i386.

Tested by:	pluknet, sbruno, gianni, Nicholas Esborn
Reviewed by:	jeff, jhb, sbruno
2011-05-05 14:39:14 +00:00
Attilio Rao
5d991209fd Fix a typo/error. 2011-04-30 22:34:44 +00:00
Attilio Rao
5c5b0e93fa Remove unnecessary usage of memory barriers when dealing with
pmc_cpumask.

Discussed with:	fabient
2011-04-30 22:33:11 +00:00
George V. Neville-Neil
51c070572e Fix two aliases that had the same name but were pointing to different
events.  These are now disamiguated.

MFC after:	1 week
2010-10-04 17:22:18 +00:00
Fabien Thomas
2aef9dd6d3 Fix invalid class removal when IAF is not the last class.
Keep IAF class with 0 PMC and change the alias in libpmc to IAP.

MFC after:	1 week
2010-09-05 13:31:14 +00:00
George V. Neville-Neil
ee6a02813b Make sure that we clear the correct bits when we turn off
a PMC.  It was possible that we could have turned a bit on but
never cleared it.

Extend the calls to rdmsr() to all necessary functions, not
just those which previously caused a panic.

Pointed out by: jhb@
MFC after:	1 week
2010-07-29 17:52:23 +00:00
George V. Neville-Neil
f4a9c30419 Fix a panic brought about by writing an MSR without a proper mask.
All of the necessary wrmsr calls are now preceded by a rdmsr
and we leave the reserved bits alone.
Document the bits in the relevant registers for future reference.

Tested by:	mdf
MFC after:	1 week
2010-07-13 19:37:45 +00:00
Fabien Thomas
8b85d75511 Convert pm_runcount to int to correctly check for negative value.
Remove uncessary check for error.

Found with:	Coverity Prevent(tm)
MFC after:	1 month
2010-06-05 23:05:08 +00:00
Ryan Stone
04001891bb When configuring a system-wide couting PMC, hwpmc was incorrectly logging process mappings for that PMC. Nothing ever reads pmc logs out of a counting PMC, so the log buffers were leaked when the PMC was deconfigured. The process mappings are only useful for sampling PMCs anyway, so only log the mappings if the PMC is a sampling PMC.
This bug would cause allocating sample-mode PMCs to fail with ENOMEM after allocating several counting-mode PMCs.

Approved by:	jkoshy (mentor)
MFC after:	2 weeks
2010-05-01 22:04:58 +00:00
Fabien Thomas
5d0848e9c6 - Fix a typo OFFCORE_REQUESTS.ANY.RFO is B0H10H and not 80H10H.
- Enable missing PARTIAL_ADDRESS_ALIAS for Core i7.

MFC after: 3 days
2010-04-15 19:45:03 +00:00
Fabien Thomas
1fa7f10bac - Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
Fabien Thomas
0e03140400 If there is multiple PMCs for the same interrupt ignore new post.
This will indirectly fix a bug where the thread will be pinned
forever if the assert is not compiled.

MFC after: 3days
2010-03-31 20:00:44 +00:00
Fabien Thomas
662cf71968 Handling SIGPIPE will cause deadlock/crash.
Return an error immediatly in case of hard shutdown.

MFC after: 3days
2010-03-26 14:35:48 +00:00
Fabien Thomas
b44906e506 Change the way shutdown is handled for log file.
pmc_flush_logfile is now non-blocking and just ask the kernel
to shutdown the file. From that point, no more data is
accepted by the log thread and when the last buffer is flushed
the file is closed.

This will remove a deadlock between pmcstat asking for
flush while it cannot flush the pipe itself.

MFC after: 3 days
2010-03-08 19:58:00 +00:00
George V. Neville-Neil
660df75e8b Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.

Reviewed by:	jkoshy rpaulo fabien imp
MFC after:	1 month
2010-03-03 15:05:58 +00:00
Joseph Koshy
e9b5dc16ef Use VFS_{LOCK,UNLOCK}_GIANT() around the call to vrele().
Reviewed by:	 kib
2009-12-29 02:35:50 +00:00
Joseph Koshy
8ca7958478 * Support the L1D_CACHE_LD event on Core2 processors.
* Correct a group of typos: for Core2 programmable events, check
  user supplied umask values against the correct event descriptor
  field.

Submitted by:	Ryan Stone <rysto32 at gmail dot com>
2009-12-26 14:39:23 +00:00
Joseph Koshy
bf792d68c7 Log process mappings for existing processes at PMC start time.
Submitted by:	Marc Unangst <mju at panasas dot com> [original patch]
Tested by:	fabient
2009-12-26 13:58:52 +00:00