specifies the instruction's operation size. GCC will default to 32-bit
operands reguardless of the prototype (ie, formal parameters' type)
of an inline function.
same functionality. Sharing code should help cache issues.
Remove in_cksum_partial, since its not being used, and we now have
a way to compute partial checksums on mbuf chains.
- Add support for using the PCI BIOS functions for configuration space
accesses, and make this the default.
- Make PNPBIOS the default (obsoletes the PNPBIOS config option).
- Add two new boot-time tunables to disable each of the above.
via sysctl. It's done pretty simply but it should be quite adequate.
Also move SHMMAXPGS from $machine/include/vmparam.h as the comments that
went with it were wrong... we don't allocate KVM space for the pages so
that comment is bogus.. The only practical limit is how much physical
ram you want to lock up as this stuff isn't paged out or swap backed.
caused some headers not to fit in MHLEN any more. This matches the
current size on the alpha, so it shouldn't cause problems.
Problem observed by: Geoff Rehmet <geoff@is.co.za>
Originally suggested by: shin
includes one of bus_at386.h and bus_pc98.h. Becuase only bus_pc98.h
supports indirect pio and bus_at386.h is identical to old bus.h, there
is no functional change in PC-AT's kernels. That is, it cannot cause
performance loss.
Submitted by: nyan
Reviewed by: imp
bde and luoqi provided useful comments for earlier version.
syscall path inward. A system call may select whether it needs the MP
lock or not (the default being that it does need it).
A great deal of conditional SMP code for various deadended experiments
has been removed. 'cil' and 'cml' have been removed entirely, and the
locking around the cpl has been removed. The conditional
separately-locked fast-interrupt code has been removed, meaning that
interrupts must hold the CPL now (but they pretty much had to anyway).
Another reason for doing this is that the original separate-lock for
interrupts just doesn't apply to the interrupt thread mechanism being
contemplated.
Modifications to the cpl may now ONLY occur while holding the MP
lock. For example, if an otherwise MP safe syscall needs to mess with
the cpl, it must hold the MP lock for the duration and must (as usual)
save/restore the cpl in a nested fashion.
This is precursor work for the real meat coming later: avoiding having
to hold the MP lock for common syscalls and I/O's and interrupt threads.
It is expected that the spl mechanisms and new interrupt threading
mechanisms will be able to run in tandem, allowing a slow piecemeal
transition to occur.
This patch should result in a moderate performance improvement due to
the considerable amount of code that has been removed from the critical
path, especially the simplification of the spl*() calls. The real
performance gains will come later.
Approved by: jkh
Reviewed by: current, bde (exception.s)
Some work taken from: luoqi's patch
for generating /boot/kernel.conf. Since this structure is shared, move
its definition out to a header file, just as struct isa_device was defined
in a header file. This fixes the sysinstall breakage in -current.
- Microsoft IntelliMouse Explorer: 2 buttons on top, 2 side buttons
and a wheel which also acts as the middle button. The mouse is
recognized as "IntelliMouse Explorer".
- Genius NetScroll Optical: 2 buttons on top, 2 side buttons and a
wheel which also acts as the middle button. The mouse is recognized
as "NetMouse/NetScroll Optical".
- MouseSystems SmartScroll Mouse (OEM from Genius?): 3 buttons on top,
1 side button and a wheel. The mouse is recognized as Genius
"NetScroll".
- IBM ScrollPoint: 2 buttons on top and a stick between the buttons.
The stick can perform "horizontal scroll" in W*ndows environment.
The horizontal movement of the stick is detected. It is currently
mapped to the Z axis movement in the same way as the first wheel.
The mouse is recognized as "MouseMan+", as it is considered to be
a variation of MouseMan.
- A4 Tech 4D and 4D+ mice. These mice have two wheels! The movement
of the second wheel is reported as the Z axis movement in the
same way as the first wheel. These mice are recognized as "4D
Mouse" and "4D+ Mouse".
- Tweak IntelliMouse support code a bit so that less-than-compatible
wheel mice can work properly with the psm driver.
- Add driver configuration flags which correspond to the kernel
options PSM_HOOKRESUME and PSM_RESETAFTERSUSPEND, so that we don't
need to recompile the kernel when we need these functions.
- Properly keep track of the irq resource.
- Add a watchdog timer in case interrupts are lost (experimental).
- Add `detach' function (experimental).
was using them exits.
Don't allow a user process to cause the kernel to take a TRCTRAP on a
user space address.
Reviewed by: jlemon, sef
Approved by: jkh
Also update wicontrol to enable/disable encryption, set WEP keys and set the
TX key index. Silver cards only have 40-bit keys. This is something of a quick
hack, but it works well enough for me to commit this from the LinuxWorld
exhibit floor.
The WEP support only shows up if you have a card that supports it.
Would have been approved by: jkh, if he hadn't wandered off somewhere
Approved in his place by: msmith, who's standing right here
the low level interrupt handler number should be used. Change
setup_apic_irq_mapping() to allocate low level interrupt handler X (Xintr${X})
for any ISA interrupt X mentioned in the MP table.
Remove an assumption in the driver for the system clock (clock.c) that
interrupts mentioned in the MP table as delivered to IOAPIC #0 intpin Y
is handled by low level interrupt handler Y (Xintr${Y}) but don't assume
that low level interrupt handler 0 (Xintr0) is used.
Don't allocate two low level interrupt handlers for the system clock.
Reviewed by: NOKUBI Hirotaka <hnokubi@yyy.or.jp>
is an application space macro and the applications are supposed to be free
to use it as they please (but cannot). This is consistant with the other
BSD's who made this change quite some time ago. More commits to come.
The UPAGES have not been there since Jan '96, but the hole was preserved
for BSD/OS binary compatability. This has been fixed other ways (%ebx
now has a pointer to PS_STRINGS), and the stack is nowhere near where
it used to be so this hack isn't required anymore.
and extend. The new function containing the code is named schedclock()
as in NetBSD, but it has slightly different semantics (it already handles
incrementation of p->p_cpticks, and it should handle any calling frequency).
Agreed with in principle by: dufault
- Convert to new bus attachment scheme. Thanks to Blaz Zupan for doing
the initial work here. One thing I changed was to have the attach
and detach routines work like the PCI drivers, which means that in
theory you should be able to load and unload the driver like the PCI
NIC drivers, however the pccard support for this hasn't settled down
yet so it doesn't quite work. Once the pccard work is done, I'll have
to revisit this.
- Add device wi0 to PCCARD. If we're lucky, people should be able to
install via their WaveLAN cards now.
- Add support for signal strength caching. The wicontrol utility has
also been updated to allow zeroing and displaying the signal strength
cache.
- Add a /sys/modules/wi directory and fix a Makefile to builf if_wi.ko.
Currently this module is only built for the i386 platform, though once
the pccard stuff is done it should be able to work on the alpha too.
(Theoretically you should be able to plug one of the WaveLAN/IEEE ISA
cards into an alpha with an ISA slot, but we'll see how that turns out.
- Update LINT to use only device wi0. There is no true ISA version of
the WaveLAN/IEEE so we'll never use an ISA attachment.
- Update files.i386 so that if_wi is dependent on card.
to use a locked cmpexg when unlocking a lock that we already hold, since
nobody else can touch the lock while we hold it. Second, it is not
necessary to use a locked cmpexg when locking a lock that we already
hold, for the same reason. These changes will allow MP locks to be used
recursively without impacting performance.
Modify two procedures that are called only by assembly and are already
NOPROF entries to pass a critical argument in %edx instead of on the
stack, removing a significant amount of code from the critical path
as a consequence.
Reviewed by: Alfred Perlstein <bright@wintelcom.net>, Peter Wemm <peter@netplex.com.au>
to use a locked cmpexg when unlocking a lock that we already hold, since
nobody else can touch the lock while we hold it. Second, it is not
necessary to use a locked cmpexg when locking a lock that we already
hold, for the same reason. These changes will allow MP locks to be used
recursively without impacting performance.
Modify two procedures that are called only by assembly and are already
NOPROF entries to pass a critical argument in %edx instead of on the
stack, removing a significant amount of code from the critical path
as a consequence.
Reviewed by: Alfred Perlstein <bright@wintelcom.net>, Peter Wemm <peter@netplex.com.au>
Historically, the documentation of extended asm was lacking, namely you
should NOT specify the same register as an input, and a clobber.
If the register is clobbered, it should be specified as an output as well,
e.g., by linking input and output through the "number" notation.
(Beware of lvalues, some local variables needed...)
URL:http://egcs.cygnus.com/faq.html
In versions up to egcs-1.1.1, the compiler did not even warn about it,
but it was liable to output bad code. Newer egcs are pickier and simply
refuse to swallow such code.
Note, since *addr changes, it needs to be an output operand.
We might be excessive in saying that all memory has changed.
Obtained from: OpenBSD
w/extra thanks to Marc Espie <Marc.Espie@liafa.jussieu.fr>
