7 Commits

Author	SHA1	Message	Date
Marcel Moolenaar	b17249b1ec	Fix disassembly of the invala, itc, itr and hint instructions ... by fixing the opcode ordering. MFC after: 1 week	2007-10-16 02:49:40 +00:00
Marcel Moolenaar	0705941372	Update to SDM 2.2: ... o Add tf (test feature) instruction, o Add vmsw (VM switch) instruction. While here, update copyright. MFC after: 1 week	2006-06-24 19:21:11 +00:00
Marcel Moolenaar	a4b606cd18	Sync up with SDM 2.1: ... o Add nop/hint formats F16, I18, M48 and X5, o Add format M47 for ptc.e, o Add hint instruction, o Fix decoding of cmp8xchg16.	2006-06-24 01:19:52 +00:00
Warner Losh	86cb007f9f	/* -> /*- for copyright notices, minor format tweaks as necessary	2005-01-06 22:18:23 +00:00
Arun Sharma	646c6dd2c0	ITC.{i,d} instructions use format M41 not M42. ... reviewed by: marcel@	2004-08-16 18:41:24 +00:00
Marcel Moolenaar	3fc58f92dc	Remove two unused fields in the operand structure (o_read & o_write).	2003-10-24 02:05:53 +00:00
Marcel Moolenaar	b9eabb421b	Add a new disassembler that improves over the previous disassembler ... in that it provides an abstract (intermediate) representation for instructions. This significantly improves working with instructions such as emulation of instructions that are not implemented by the hardware (e.g. long branch) or enhancing implemented instructions (e.g. handling of misaligned memory accesses). Not to mention that it's much easier to print instructions. Functions are included that provide a textual representation for opcodes, completers and operands. The disassembler supports all ia64 instructions defined by revision 2.1 of the SDM (Oct 2002).	2003-10-23 06:01:52 +00:00