(HDMI and HBR bits set) and needed (AC3 format used with 8 channels).
This should allow DTS-HD/TrueHD pass-through with rates above 6.144Mbps.
MFC after: 2 months
Sponsored by: iXsystems, Inc.
widgets. I am not sure if S/PDIF supports 32bit samples, but my Marantz
SR4001 doesn't, producing only single clicks on playback start/stop.
Because HDA controller requires 32bit alignment for all samples above 16bit,
we can't handle this situation in regular way and have to set 32bit format
in sound(4) for anything above 16bit. To workaround the problem, prefer
to setup hardware to use 24/20bit samples when 32bit format requested. Add
dev.pcm.X.play.32bit and dev.pcm.X.rec.32bit sysctls to control what format
really use for 32bit samples.
MFC after: 2 months
Sponsored by: iXsystems, Inc.
maximal from 64K to 256K.
We usually don't need 750 sound interrupts per second (1.3ms latency)
when playing 192K/24/8 stream. 187 should be better. On usual 48K/16/2
it is just enough for hw.snd.latency=9 at hw.snd.latency_profile=1 with
23 and 6 interrupts per second.
MFC after: 2 weeks
Sponsored by: iXsystems, Inc.
Previous code was relatively dumb. During CODEC probe it was tracing signals
and statically binding amplifier controls to the OSS mixer controls. To set
volume it just set all bound amplifier controls proportionally to mixer
level, not looking on their hierarchy and amplification levels/offsets.
New code is much smarter. It also traces signals during probe, but mostly
to find out possible amplification control rages in dB for each specific
signal. To set volume it retraces each affected signal again and sets
amplifiers controls recursively to reach desired amplification level in dB.
It would be nice to export values in dB to user, but unluckily our OSS mixer
API is too simple for that.
As result of this change:
- cascaded amplifiers will work together to reach maximal precision.
If some input has 0/+40dB preamplifier with 10dB step and -10/+10dB mixer
with 1dB step after it, new code will use both to provide 0/+40dB control
with 1dB step! We could even get -10/+50dB range there, but that is
intentionally blocked for now.
- different channels of multichannel associations on non-uniform CODECs
such as VIA VT1708S will have the same volume, not looking that control
ranges are different. It was not good when fronts were 12dB louder.
- for multiplexed recording, when we can record from only one source at
a time, we can now use recording amplifier controls to set different
volume levels for different inputs if they have no own controls of they
are less precise. If recording source change, amplifiers will be
reconfigured.
To improve out-of-the-box behavior, ignore default volume levels set by
sound(4) and use own, more reasonable: +20dB for mics, -10dB for analog
output volume and 0dB for the rest of controls. sound(4) defaults of 75%
mean absolutely random things for different controls of different CODECs
because of very different control ranges.
Together with further planned automatic recording source selection this
should allow users to get fine playback and recording without touching
mixer first.
Note that existing users should delete /var/db/mixer*-state and reboot
or trigger CODEC reconfiguration to get new default values.
MFC after: 2 months
Sponsored by: iXsystems, Inc.
64bit and 32bit ABIs. As a side-effect, it enables AVX on capable
CPUs.
In particular:
- Query the CPU support for XSAVE, list of the supported extensions
and the required size of FPU save area. The hw.use_xsave tunable is
provided for disabling XSAVE, and hw.xsave_mask may be used to
select the enabled extensions.
- Remove the FPU save area from PCB and dynamically allocate the
(run-time sized) user save area on the top of the kernel stack,
right above the PCB. Reorganize the thread0 PCB initialization to
postpone it after BSP is queried for save area size.
- The dumppcb, stoppcbs and susppcbs now do not carry the FPU state as
well. FPU state is only useful for suspend, where it is saved in
dynamically allocated suspfpusave area.
- Use XSAVE and XRSTOR to save/restore FPU state, if supported and
enabled.
- Define new mcontext_t flag _MC_HASFPXSTATE, indicating that
mcontext_t has a valid pointer to out-of-struct extended FPU
state. Signal handlers are supplied with stack-allocated fpu
state. The sigreturn(2) and setcontext(2) syscall honour the flag,
allowing the signal handlers to inspect and manipilate extended
state in the interrupted context.
- The getcontext(2) never returns extended state, since there is no
place in the fixed-sized mcontext_t to place variable-sized save
area. And, since mcontext_t is embedded into ucontext_t, makes it
impossible to fix in a reasonable way. Instead of extending
getcontext(2) syscall, provide a sysarch(2) facility to query
extended FPU state.
- Add ptrace(2) support for getting and setting extended state; while
there, implement missed PT_I386_{GET,SET}XMMREGS for 32bit binaries.
- Change fpu_kern KPI to not expose struct fpu_kern_ctx layout to
consumers, making it opaque. Internally, struct fpu_kern_ctx now
contains a space for the extended state. Convert in-kernel consumers
of fpu_kern KPI both on i386 and amd64.
First version of the support for AVX was submitted by Tim Bird
<tim.bird am sony com> on behalf of Sony. This version was written
from scratch.
Tested by: pho (previous version), Yamagi Burmeister <lists yamagi org>
MFC after: 1 month
Currently the code is not built by any modules. That will
be fixed later. The Atmel ARM bus interface file part of this
commit is just for sake of example. All registers and bits are
declared like macros and not C-structures like in official
Synopsis header files. This driver mostly origins from the
musb_otg.c driver in FreeBSD except that the chip specific
programming has been replaced by the one for DWC 2.0 USB OTG.
Some parts related to system suspend and resume have been left
like empty functions for the future. USB suspend and resume is
fully supported.
versions derived from /usr/ports/audio/oss.
The particular headers used were taken from the
attic/drv/oss_allegro directory and are mostly identical
to the previous files.
The Maestro3 driver is now free from the GPL.
NOTE: due to lack of testers this driver is being
considered for deprecation and removal.
PR: kern/153920
Approved by: jhb (mentor)
MFC after: 2 weeks
pci_get_vpd_readonly_method(). Previously the loop was always running
to completion and falling through to failing with ENXIO.
PR: kern/164313
Submitted by: Chuck Tuffli chuck tuffli net
MFC after: 1 week
frightening "unknown" word. In most cases we don't need to know chips
to properly handle them, but having IDs in logs may simplify debugging.
MFC after: 2 weeks
Sponsored by: iXsystems, Inc.
1. correct the initialization of RDT when there is an ixgbe_init()
while a netmap client is active. This code was previously
in ixgbe_initialize_receive_units() but RDT is overwritten
shortly afterwards in ixgbe_init_locked()
2. add code (not active yet) to disable CRCSTRIP while in netmap mode.
From all evidence i could gather, it seems that when the 82599 has to
write a data block that is not a full cache line, it first reads
the line (64 bytes) and then writes back the updated version.
This hurts reception of min-sized frames, which are only 60 bytes
if the CRC is stripped: i could never get above 11Mpps
(received from one queue) with CRCSTRIP enabled, whyle 64+4-byte
packets reach 14.2 Mpps (the theoretical maximum).
Leaving the CRC in gets us 14.88Mpps for 60+4 byte frames,
(and penalizes 64+4). The min-size case is important not just because
it looks good in benchmarks, but also because this is the size
of pure acks.
Note we cannot leave CRCSTRIP on by default because it is
incompatible with some other features (LRO etc.)
of HDA bus. Handle that from two directions:
- Add support for "striping" (using several SDO lines), if supported.
- Account HDA bus utilization and return error on new stream allocation
attempt if remaining bandwidth is unsifficient.
Most of HDA controllers have one SDO line with 46Mbps output bandwidth.
NVIDIA GF210 has 2 lines - 92Mbps. NVIDIA GF520 has 4 lines - 184Mbps!
MFC after: 2 months
Sponsored by: iXsystems, Inc.
- Enable and handle unsolicited responses from digital display pins,
reporting connection and EDID-Like Data (ELD) validity status changes.
- Fetch ELD data, describing connected digital display device audio
capabilities. These data not really used at the moment (user is not
denied to use audio formats not supported by the device), only printed to
verbose logs. But they are useful for debugging. The fact that ELD was
received tells that HDMI link was established and video driver enabled
HDMI audio passthrough. Some old chips may not return ELD, so lack of it
is not necessary a problem.
- Add some more points to CODEC configuration sequence:
- For converter widgets, supporting more then two channels (HDMI/DP
converter widgets support 8), set number of channels to handle.
- For digital display pins (HDMI/DP) fill audio infoframe, reporting
connected device about number of channels and speakers allocation.
- For digital display pins (HDMI/DP) set mapping between channels seen
by software and channels transferred via HDMI/DisplayPort.
- Allow more audio formats, not used for analog connections because of
stereo pairs orientation, but easily applicable to HDMI/DisplayPort: 2.1,
3.0, 3.1, 4.1, 5.0, 6.0, 6.1, 7.0. That list may be filtered later using
info from ELD.
- Disable MSI interrupts for NVIDIA HDA controllers before GT520.
At this point I can successfully play audio over HDMI from NVIDIA GT210
and GT520 cards with nvidia-driver-290.10 driver to Marantz SR4001
receiver in 2.0, 2.1, 3.0, 4.0, 4.1, 5.0 and 5.1 PCM formats at 44, 48,
88 and 96KHz at 16 and 24 bits, same as do AC3/DTS passthrough.
6.0, 6.1, 7.0 and 7.1 PCM formats are not working for me, but I think
it is because of receiver age.
MFC after: 2 months
Sponsored by: iXsystems, Inc.
to being more generic.
Other embedded SoCs also throw the configuration/PCI register
info into flash.
For now I'm just hard-coding the AR9280 option (for on-board AR9220's on
AP94 and commercial designs (eg D-Link DIR-825.))
TODO:
* Figure out how to support it for all 11n SoC NICs by doing it in
ar5416InitState();
* Don't hard-code the EEPROM size - add another field which is set
by the relevant chip initialisation code.
* 'owl_eep_start_loc' may need to be overridden in some cases to 0x0.
I need to do some further digging.
- Huge old hdac driver was split into three independent pieces: HDA
controller driver (hdac), HDA CODEC driver (hdacc) and HDA sudio function
driver (hdaa).
- Support for multichannel recording was added. Now, as specification
defines, driver checks input associations for pins with sequence numbers
14 and 15, and if found (usually) -- works as before, mixing signals
together. If it doesn't, it configures input association as multichannel.
- Signal tracer was improved to look for cases where several DACs/ADCs in
CODEC can work with the same audio signal. If such case found, driver
registers additional playback/record stream (channel) for the pcm device.
- New controller streams reservation mechanism was implemented. That
allows to have more pcm devices then streams supported by the controller
(usually 4 in each direction). Now it limits only number of simultaneously
transferred audio streams, that is rarely reachable and properly reported
if happens.
- Codec pins and GPIO signals configuration was exported via set of
writable sysctls. Another sysctl dev.hdaa.X.reconfig allows to trigger
driver reconfiguration in run-time.
- Driver now decodes pins location and connector type names. In some cases
it allows to hint user where on the system case connectors, related to the
pcm device, are located. Number of channels supported by pcm device,
reported now (if it is not 2), should also make search easier.
- Added workaround for digital mic on some Asus laptops/netbooks.
MFC after: 2 months
Sponsored by: iXsystems, Inc.
1. as reported by Alexander Fiveg, the allocator was reporting
half of the allocated memory. Fix this by exiting from the
loop earlier (not too critical because this code is going
away soon).
2. following a discussion on freebsd-current
http://lists.freebsd.org/pipermail/freebsd-current/2012-January/031144.html
turns out that (re)loading the dmamap was expensive and not optimized.
This operation is in the critical path when doing zero-copy forwarding
between interfaces.
At least on netmap and i386/amd64, the bus_dmamap_load can be
completely bypassed if the map is NULL, so we do it.
The latter change gives an almost 3x improvement in forwarding
performance, from the previous 9.5Mpps at 2.9GHz to the current
line rate (14.2Mpps) at 1.733GHz. (this is for 64+4 byte packets,
in other configurations the PCIe bus is a bottleneck).
