Commit Graph

61 Commits

Author SHA1 Message Date
Adrian Chadd
0d2041a08b Add a description here. 2014-03-02 07:39:37 +00:00
Adrian Chadd
dd846bddbf Set all of the ports into the same vlangroup; there's only one vlangroup
(pvid=1) and we already configure them to send to other ports.

Setting pvid=portnum would mean that there were separate vlangroups
for each ports, but 'leaking' into other ports.  The result? All port
traffic flooded to all other port traffic.

Tested:

* DB120, AR9344 + AR8327 switch
2014-03-02 07:10:43 +00:00
Adrian Chadd
4ff2f60db6 Add ATU flush support.
The OpenWRT AR8xxx switch support flushes the ATU (address translation
unit) after each port link 'up' status change.  I've modified this to
just flush on any port transition.

Whilst here, bump the number of ports on the AR8327 to 6, rather than
the default of 5.  It's DB120 specific; I'll go and make this configurable
later.

There's some debugging code in here still; I am still debugging whether
this is or isn't working fully.

Tested:

* DB120, AR9344 + AR8327 switch

Obtained from:	OpenWRT
2014-03-02 05:48:56 +00:00
Adrian Chadd
93f5e67e02 Add AR8216 era ATU management/configuration register definitions.
Obtained from:	OpenWRT
2014-03-02 05:47:05 +00:00
Adrian Chadd
03b5d8277b (I think!) make the AR8327 switch correctly handle traffic.
This patch does four things:

* it globally disables mirroring;
* it globally sets the mirroring on each port to be disabled;
* the initial port setup now programs a portmask for the port to allow
  transmission (forwarding) to all other ports bar itself;
* the vlan setup path now programs the portmask for the port to
  allow transmission (forwarding) to all other ports bar itself.

Before this, I hard-coded the portmask to 0x3f which would mean all
ports (bar port 6, which currently isn't hooked up to anything.)
This means that traffic would be duplicated back out the port it
received it.  I bet this wasn't .. optimal.

In any case, this _seems_ to make DHCP from my macosx laptop
work through this access point.  I'll do some further testing
to ensure it's actually working correctly on all my devices.

Tested:

* DB120, AR8327 switch
2014-03-01 10:04:31 +00:00
Adrian Chadd
ddea319180 Be paranoid about bit operations here. 2014-03-01 00:11:45 +00:00
Adrian Chadd
093c756e0e Remove now dead code. 2014-03-01 00:02:09 +00:00
Christian Brueffer
4170452de3 Add missing includes and remove two unused ones.
Reviewed by:	loos
MFC after:	1 week
2014-02-27 21:01:10 +00:00
Adrian Chadd
b67ba111e9 Add LED setup support for the AR8327.
Tested:

* DB120

Obtained from:	OpenWRT
2014-02-26 02:00:37 +00:00
Adrian Chadd
810bdedd75 Add in the SGMII configuration code. The DB120 doesn't use it, so I
have no way to evaluate it.

Obtained from:	OpenWRT
2014-02-26 01:46:42 +00:00
Adrian Chadd
f9950f9ac8 Undo the DB120 hard-coded values in the AR8327 code and fetch it from
the hints environment.

Tested:

* DB120
2014-02-26 01:32:06 +00:00
Adrian Chadd
9ab21e32fb Add in port0/port6 configuration as part of the platform data code path.
It's still hardcoded (for db120) but it is now hardcoded in all the
same place (ie, the pdata path.)  The port config/status code now checks
port0/port6 as appropriate to configure things.

Tested:

* Qualcomm Atheros DB120, AR8327 switch.
2014-02-24 05:55:00 +00:00
Adrian Chadd
482d268d49 Link the AR8327 to the build. 2014-02-24 04:47:27 +00:00
Adrian Chadd
7330dd0bb4 Add initial AR8327 support.
This is (almost!) enough to actually probe, attach, configure a default
port group and do some basic work.  It's also totally hard-coded for
the Qualcomm Atheros DB120 board - it doesn't yet have any of the code
from OpenWRT which parses extra configuration data to know how to program
the switch.  The LED stuff is also missing.

But, it's enough to facilitate board, PHY, switch and VLAN bringup,
so I am committing it now.

Tested:

* Qualcomm Atheros DB120

Obtained from:	OpenWRT
2014-02-24 04:47:16 +00:00
Adrian Chadd
6dcbabd7d6 Methodize the arswitch VLAN routines.
These differ per chipset family in subtle and evil ways.

It becomes very noticable on the AR8327 where the layout is just plain
wrong.
2014-02-24 04:44:28 +00:00
Adrian Chadd
570c21252c * Ensure enough ports/phys are available for both the AR8327 and previous
switches.

* Add some new VLAN HAL methods that will be used by the VLAN configuration
  code.  The AR933x and later switches use slightly different register
  layouts (even though the driver currently doesn't support it.)
2014-02-24 04:43:23 +00:00
Adrian Chadd
a9ad42220a Extract out the port VLAN flags/setup code and throw it into two new
HAL methods.

This allows the AR8327 code to override it as appropriate.

Tested:

* DB120 - AR8327 and AR9340 on-board switch; only running 'etherswitchcfg'
  to check configs.  The actual VLAN programming wasn't tested.
2014-02-19 06:43:52 +00:00
Adrian Chadd
2bddba6a60 Add methods for the VLAN port set/get routines.
The registers (and perhaps the flags) are different for the AR8327, so
I'll stub those out until they're written.

Tested:

* DB120 - both on-chip AR9340 and AR8327 switches.
2014-02-19 06:35:17 +00:00
Adrian Chadd
ddbc44200a Turn the port init function into a HAL method and initialise it to the
default port init code.

This needs to be overridden for the AR8327.
2014-02-19 06:03:58 +00:00
Adrian Chadd
e765499eed Teach the PHY register path about the different MDIO bus address
for the AR8327.

Tested:

* AR8327, DB120
2014-02-19 06:02:47 +00:00
Adrian Chadd
e3ba3a89ab Add a new method to set up the individual port in question.
The AR8327 requires some different setup code.
2014-02-19 06:01:40 +00:00
Adrian Chadd
df892897a2 Change arswitch_ports_init() to arswitch_port_init(), and teach it to take
a single port to setup.

This may end up later being used as part of some logic to program
the PHY for a single port, rather than having to reinitialise them
all at once.

Tested:

* DB120
2014-02-19 05:35:41 +00:00
Adrian Chadd
0e67bf94fc Add in the AR8327 probe/attach code and switch type.
It detects fine, but (as expected) it won't attach just yet, let alone
pass traffic.

Tested:

* DB120, AR8327 switch
2014-02-19 05:09:47 +00:00
Adrian Chadd
dd843f87d3 Store away the chip version and revision; some AR8327 code depends upon
the chip revision.
2014-02-19 04:30:53 +00:00
Adrian Chadd
26ca36d4ca Add in a flag to control whether the low or high data word of a register access
is latched in first.

The AR8327 apparently requires the low data word be latched in first.

Obtained from:	Linux OpenWRT
2014-02-19 04:23:01 +00:00
Adrian Chadd
7307fbd10b The MDIO control register for the AR8327 has a different address to
previous chipsets.

Obtained from:	AR8327 datasheet
2014-02-17 05:54:24 +00:00
Adrian Chadd
1ee69b7d79 Add mmd declaration. 2014-02-17 05:51:37 +00:00
Adrian Chadd
7e1a619d03 Implement PHY bus MMD writes for arswitch.
This is used by the AR8327 PHY setup path.

Obtained from:	OpenWRT
2014-02-17 02:24:58 +00:00
Eitan Adler
7a22215c53 Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
2013-11-30 22:17:27 +00:00
Luiz Otavio O Souza
3d02237c46 Fix the build of TP-WN1043ND kernel. Provide necessary includes and remove
unnecessary includes for rtl8366rb.

Approved by:	adrian (mentor)
2013-10-29 15:45:11 +00:00
Gleb Smirnoff
66e01d73cd - Provide necessary includes.
- Remove unnecessary includes.

Sponsored by:	Netflix
Sponsored by:	Nginx, Inc.
2013-10-29 11:17:49 +00:00
Gleb Smirnoff
104dc21415 - Provide necessary includes, that before came via if.h pollution.
- Remove unnecessary ones.

Sponsored by:	Netflix
Sponsored by:	Nginx, Inc.
2013-10-28 22:26:03 +00:00
Adrian Chadd
db4ff7db8c Add a big, big note to the vlan code that it needs to be taught
about the new VLAN options for the AR9340 and AR8327 chips.
2013-10-16 04:15:35 +00:00
Adrian Chadd
b215216171 Add support for the AR9340 switch to the switch framework.
* Do the hardware setup in the right order!
* Modify/improve the chip probe check so it can actually
  probe the 7240/9340 directly (although it's not yet used..)
* Initialise and fetch the is_mii option
* Fix some debugging whilst I'm here.

This is enough to get things off the ground.

Tested:

* AR9344 SoC
2013-10-16 04:15:03 +00:00
Adrian Chadd
657b84792c Prepare to link in the AR934x SoC switch support.
* Add an AR9340 switch version entry;
* Support the switch being connected via MII;
* Add a flag to note that a switch is actually an internal
  switch rather than an external switch.

Now:

* The ar9340 switch can interconnect via MII;
* Since some slightly different phy/switch register access methods
  and quirks appear for the internal versus external switch,
  we will need a flag to mark it as an "internal" switch.

Tested:

* AR9344 (internal switch)
* AR9331 (internal switch)

TODO:

* Test the AR8316 switch!
2013-10-16 03:19:05 +00:00
Adrian Chadd
fc80af8857 Initial commit of AR9340 switch SoC support.
This is just the chip initialisation code (for now.)

It's not linked into the main build as it requires a bunch of other code
to be tidied up and committed.  But it indeed does function as advertised.

Tested:

* AR9344 SoC
2013-10-16 03:15:52 +00:00
Adrian Chadd
7e57b3ad31 Add AR934x, AR8327 register definitions.
Obtained from:	Linux/OpenWRT
2013-10-15 00:26:02 +00:00
Luiz Otavio O Souza
b9f07b864b Add the support for 802.1q and port based vlans for arswitch.
Tested on: RB450G (standalone ar8316), RSPRO (standalone ar8316) and
TPLink MR-3220 (ar724x integrated switch).

Approved by:	adrian (mentor)
Obtained from:	zrouter
2013-07-23 14:24:22 +00:00
Luiz Otavio O Souza
9604b6ac4a Fix the arswitch instability problem. It turns out that the
arswitch_writereg() routine was writing the registers in the wrong order.

Revert -r241918 as the root problem is now fixed. Remove another workaround
from arswitch_ar7240.c.

Simplify and fix the code on arswitch_writephy() by using
arswitch_writereg().

While here remove a redundant declaration from arswitchvar.h.

Approved by:	adrian (mentor)
2013-07-23 14:02:38 +00:00
Luiz Otavio O Souza
cc320e372e Add a new flag (ETHERSWITCH_VID_VALID) to say what vlangroups are in use.
This fix the case when etherswitch is printing the information of port 0
vlan group (in port based vlan mode) with no member ports.

Add the ETHERSWITCH_VID_VALID support to ip17x driver.

Add the ETHERSWITCH_VID_VALID support to rt8366 driver.

arswitch doesn't need to be updated as it doesn't support vlans management
yet.

Approved by:	adrian (mentor)
2013-07-23 13:56:38 +00:00
Adrian Chadd
248dd6039d Bring in a basic ethernet switch driver for the IP17x series of
switches.

These are notably found on some AR71xx based Mikrotik boards.

Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by:	ray
2013-05-08 20:58:41 +00:00
Adrian Chadd
1ead288f8d Fix the ukswitch code to work with the new vlan changes:
* Fix API changes;
* remove unused code;
* Allow some switches to be used that don't expose a set of PHY
  registers for the CPU facing port (eg the ADM6996 for the Ubiquiti
  Routerstation.)

Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by:	ray
2013-05-08 20:56:43 +00:00
Adrian Chadd
f47857dc3d Correctly mark the CPU port.
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by:	ray
2013-05-08 20:54:59 +00:00
Adrian Chadd
a48a9355ef Add the ability to change the vlan operation mode.
This adds a vlan capability field to etherswitch_info structure and some
definitions of ports flags.

It adds the support to global config parameters which right now is used
only to switch between the vlan modes, but it is intended to be extended
to support the setup of others parameters (STP, mirror, etc.).

Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by:	ray
2013-05-08 20:46:54 +00:00
Adrian Chadd
03d48af292 Update arswitch to the new API. 2013-04-22 18:58:12 +00:00
Adrian Chadd
a321935999 Convert over the etherswitch framework to use VLAN IDs per port, rather
than VLAN groups.

Some chips (eg this rtl8366rb) has a VLAN group per port - you first
define a set of VLANs in a vlan group, then you assign a VLAN group
to a port.

Other chips (eg the AR8xxx switch chips) have a VLAN ID array per
port - there's no group per se, just a list of vlans that can be
configured.

So for now, the switch API will use the latter and rely on drivers
doing the heavy lifting if one wishes to use the VLAN group method.
Maybe later on both can be supported.

PR:		kern/177878
PR:		kern/177873
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by:	ray
2013-04-22 05:52:18 +00:00
Adrian Chadd
7b796c4039 Implement a very basic multi-PHY aware switch device.
This is intended to be used as a stop-gap for switch devices
which expose multiple ethernet PHYs but we don't have a driver
for - here, etherswitchcfg and the general switch configuration
API can be used to interface to said PHYs.

Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
2013-04-19 17:50:38 +00:00
Aleksandr Rybalko
dc9c386cd0 Disable automatic attachment of arswitch. It can't be auto-detected (like PHYs
do) and cause a problems trying to attach another instance to child mdio.

Submitted by:	Luiz Otavio O Souza
Approved by:	adrian (menthor)
2012-11-07 22:43:09 +00:00
Adrian Chadd
68629cc4f1 Don't try to cache the page setting - always set the page before
doing a switch register read/write.

PR:		kern/172968
2012-10-22 22:32:52 +00:00
Aleksandr Rybalko
26aff2abad Mask data to only 16 bits to be sure on write into switch reg.
Submitted by:	Luiz Otavio O Souza
Approved by:	adrian (mentor)
2012-10-15 12:28:14 +00:00