Commit Graph

118 Commits

Author SHA1 Message Date
Fabien Thomas
2dde521a9a There's a small set of events on Nehalem, that are not supported in
processors with CPUID signature 06_1AH, 06_1EH, and 06_1FH.

Refuse to allocate them on unsupported model.

Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	1 month
2011-12-12 13:12:55 +00:00
Fabien Thomas
d2b58b22b5 Update Westmere uncore event exception list.
Submitted by:	Davide Italiano <davide italiano at gmail com>
MFC after:	1 week
2011-12-02 10:02:49 +00:00
Adrian Chadd
009d7740fc Flip on processing interrupt profile events for mips24k.
This is a bit hackish and should be made more generic (ie, support more than
two hard-coded performance counter+config register pairs) so it can be used
for mips74k and other chips.

All this does is process the initial interrupt event. It doesn't (yet) handle
callgraph events, so even if you route the exception/interrupt to this routine
and flip the bit on, it will hang and crash pmc unless you disable callgraph
support when you enable a sample based PMC.
2011-11-09 17:38:27 +00:00
Fabien Thomas
dceed24a7c Add a flush of the current PMC log buffer before displaying the next top.
As the underlying block is 4KB if the PMC throughput is low the measurement
will be reported on the next tick. pmcstat(8) use the modified flush API to
reclaim current buffer before displaying next top.

MFC after:	1 month
2011-10-18 15:25:43 +00:00
Adrian Chadd
cdb59558b9 Begin implementing correct MIPS24K sampling mode behaviour.
* Add the interrupt bit in the configuration register
* Correctly set the counter register for the sampling overflow
  interrupt. The interrupt is asserted when bit 31 is set.
  So set the overflow value at 0x80000000 and subtract the
  programmed value as appropriate.
2011-10-07 06:13:38 +00:00
Kip Macy
8451d0dd78 In order to maximize the re-usability of kernel code in user space this
patch modifies makesyscalls.sh to prefix all of the non-compatibility
calls (e.g. not linux_, freebsd32_) with sys_ and updates the kernel
entry points and all places in the code that use them. It also
fixes an additional name space collision between the kernel function
psignal and the libc function of the same name by renaming the kernel
psignal kern_psignal(). By introducing this change now we will ease future
MFCs that change syscalls.

Reviewed by:	rwatson
Approved by:	re (bz)
2011-09-16 13:58:51 +00:00
Robert Watson
a9d2f8d84f Second-to-last commit implementing Capsicum capabilities in the FreeBSD
kernel for FreeBSD 9.0:

Add a new capability mask argument to fget(9) and friends, allowing system
call code to declare what capabilities are required when an integer file
descriptor is converted into an in-kernel struct file *.  With options
CAPABILITIES compiled into the kernel, this enforces capability
protection; without, this change is effectively a no-op.

Some cases require special handling, such as mmap(2), which must preserve
information about the maximum rights at the time of mapping in the memory
map so that they can later be enforced in mprotect(2) -- this is done by
narrowing the rights in the existing max_protection field used for similar
purposes with file permissions.

In namei(9), we assert that the code is not reached from within capability
mode, as we're not yet ready to enforce namespace capabilities there.
This will follow in a later commit.

Update two capability names: CAP_EVENT and CAP_KEVENT become
CAP_POST_KEVENT and CAP_POLL_KEVENT to more accurately indicate what they
represent.

Approved by:	re (bz)
Submitted by:	jonathan
Sponsored by:	Google Inc
2011-08-11 12:30:23 +00:00
Attilio Rao
71a19bdc64 Commit the support for removing cpumask_t and replacing it directly with
cpuset_t objects.
That is going to offer the underlying support for a simple bump of
MAXCPU and then support for number of cpus > 32 (as it is today).

Right now, cpumask_t is an int, 32 bits on all our supported architecture.
cpumask_t on the other side is implemented as an array of longs, and
easilly extendible by definition.

The architectures touched by this commit are the following:
- amd64
- i386
- pc98
- arm
- ia64
- XEN

while the others are still missing.
Userland is believed to be fully converted with the changes contained
here.

Some technical notes:
- This commit may be considered an ABI nop for all the architectures
  different from amd64 and ia64 (and sparc64 in the future)
- per-cpu members, which are now converted to cpuset_t, needs to be
  accessed avoiding migration, because the size of cpuset_t should be
  considered unknown
- size of cpuset_t objects is different from kernel and userland (this is
  primirally done in order to leave some more space in userland to cope
  with KBI extensions). If you need to access kernel cpuset_t from the
  userland please refer to example in this patch on how to do that
  correctly (kgdb may be a good source, for example).
- Support for other architectures is going to be added soon
- Only MAXCPU for amd64 is bumped now

The patch has been tested by sbruno and Nicholas Esborn on opteron
4 x 12 pack CPUs. More testing on big SMP is expected to came soon.
pluknet tested the patch with his 8-ways on both amd64 and i386.

Tested by:	pluknet, sbruno, gianni, Nicholas Esborn
Reviewed by:	jeff, jhb, sbruno
2011-05-05 14:39:14 +00:00
Attilio Rao
5d991209fd Fix a typo/error. 2011-04-30 22:34:44 +00:00
Attilio Rao
5c5b0e93fa Remove unnecessary usage of memory barriers when dealing with
pmc_cpumask.

Discussed with:	fabient
2011-04-30 22:33:11 +00:00
George V. Neville-Neil
51c070572e Fix two aliases that had the same name but were pointing to different
events.  These are now disamiguated.

MFC after:	1 week
2010-10-04 17:22:18 +00:00
Fabien Thomas
2aef9dd6d3 Fix invalid class removal when IAF is not the last class.
Keep IAF class with 0 PMC and change the alias in libpmc to IAP.

MFC after:	1 week
2010-09-05 13:31:14 +00:00
George V. Neville-Neil
ee6a02813b Make sure that we clear the correct bits when we turn off
a PMC.  It was possible that we could have turned a bit on but
never cleared it.

Extend the calls to rdmsr() to all necessary functions, not
just those which previously caused a panic.

Pointed out by: jhb@
MFC after:	1 week
2010-07-29 17:52:23 +00:00
George V. Neville-Neil
f4a9c30419 Fix a panic brought about by writing an MSR without a proper mask.
All of the necessary wrmsr calls are now preceded by a rdmsr
and we leave the reserved bits alone.
Document the bits in the relevant registers for future reference.

Tested by:	mdf
MFC after:	1 week
2010-07-13 19:37:45 +00:00
Fabien Thomas
8b85d75511 Convert pm_runcount to int to correctly check for negative value.
Remove uncessary check for error.

Found with:	Coverity Prevent(tm)
MFC after:	1 month
2010-06-05 23:05:08 +00:00
Ryan Stone
04001891bb When configuring a system-wide couting PMC, hwpmc was incorrectly logging process mappings for that PMC. Nothing ever reads pmc logs out of a counting PMC, so the log buffers were leaked when the PMC was deconfigured. The process mappings are only useful for sampling PMCs anyway, so only log the mappings if the PMC is a sampling PMC.
This bug would cause allocating sample-mode PMCs to fail with ENOMEM after allocating several counting-mode PMCs.

Approved by:	jkoshy (mentor)
MFC after:	2 weeks
2010-05-01 22:04:58 +00:00
Fabien Thomas
5d0848e9c6 - Fix a typo OFFCORE_REQUESTS.ANY.RFO is B0H10H and not 80H10H.
- Enable missing PARTIAL_ADDRESS_ALIAS for Core i7.

MFC after: 3 days
2010-04-15 19:45:03 +00:00
Fabien Thomas
1fa7f10bac - Support for uncore counting events: one fixed PMC with the uncore
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
2010-04-02 13:23:49 +00:00
Fabien Thomas
0e03140400 If there is multiple PMCs for the same interrupt ignore new post.
This will indirectly fix a bug where the thread will be pinned
forever if the assert is not compiled.

MFC after: 3days
2010-03-31 20:00:44 +00:00
Fabien Thomas
662cf71968 Handling SIGPIPE will cause deadlock/crash.
Return an error immediatly in case of hard shutdown.

MFC after: 3days
2010-03-26 14:35:48 +00:00
Fabien Thomas
b44906e506 Change the way shutdown is handled for log file.
pmc_flush_logfile is now non-blocking and just ask the kernel
to shutdown the file. From that point, no more data is
accepted by the log thread and when the last buffer is flushed
the file is closed.

This will remove a deadlock between pmcstat asking for
flush while it cannot flush the pipe itself.

MFC after: 3 days
2010-03-08 19:58:00 +00:00
George V. Neville-Neil
660df75e8b Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.

Reviewed by:	jkoshy rpaulo fabien imp
MFC after:	1 month
2010-03-03 15:05:58 +00:00
Joseph Koshy
e9b5dc16ef Use VFS_{LOCK,UNLOCK}_GIANT() around the call to vrele().
Reviewed by:	 kib
2009-12-29 02:35:50 +00:00
Joseph Koshy
8ca7958478 * Support the L1D_CACHE_LD event on Core2 processors.
* Correct a group of typos: for Core2 programmable events, check
  user supplied umask values against the correct event descriptor
  field.

Submitted by:	Ryan Stone <rysto32 at gmail dot com>
2009-12-26 14:39:23 +00:00
Joseph Koshy
bf792d68c7 Log process mappings for existing processes at PMC start time.
Submitted by:	Marc Unangst <mju at panasas dot com> [original patch]
Tested by:	fabient
2009-12-26 13:58:52 +00:00
Rui Paulo
0ce207d2af Intel XScale hwpmc(4) support.
This brings hwpmc(4) support for 2nd and 3rd generation XScale cores.
Right now it's enabled by default to make sure we test this a bit.
When the time comes it can be disabled by default.
Tested on Gateworks boards.

A man page is coming.

Obtained from:	//depot/user/rpaulo/xscalepmc/...
2009-12-23 23:16:54 +00:00
Joseph Koshy
68c3e04122 Recognize Intel CPUs with Family 0x6, Models 0x1E and 0x1F.
Submitted by:	Marc Unangst <mju at panasas dot com>
2009-12-18 15:01:46 +00:00
Joseph Koshy
c66e06a2f6 Use a better check for a valid kernel stack address when capturing
kernel call chains.

Submitted by:	Mark Unangst <mju at panasas.com>
Tested by:	fabient
2009-12-03 14:59:42 +00:00
Ed Maste
1a12d24be0 Fix parenthesis typo -- copy full frame pointer for userland callchain,
not just one byte.

Submitted by:	Ryan Stone	rysto32 at gmail dot com
2009-12-01 21:54:53 +00:00
Ed Maste
e182dffce4 Use switch out (SWO) instead of switch in (SWI) debug log mask in csw_out. 2009-11-30 20:41:30 +00:00
Fabien Thomas
5eaf27d8ff - fix a LOR between process lock and pmc thread mutex
- fix a system deadlock on process exit when the sample buffer
is full (pmclog_loop blocked in fo_write) and pmcstat exit.

Reviewed by: jkoshy
MFC after: 3 weeks
2009-11-24 19:26:53 +00:00
Joseph Koshy
27be5d5888 Only claim that the PMC_CLASS_IAF PMCs are supported by a CPU if
there are PMCs on the CPU that belong to the class.

Review and testing by:	fabient
2009-10-24 01:58:10 +00:00
Fabien Thomas
fa630f3569 Handle the case where there is only one PMC in the system.
Approved by: jkoshy (mentor)
MFC after: 3 days
2009-10-21 18:46:36 +00:00
Rui Paulo
e5087dd893 Fix KASSERT string to include the real module name. 2009-10-18 13:51:49 +00:00
Rui Paulo
f0fda3a508 Reserve events for XScale.
Reviewed by:	jkoshy, gnn
MFC after:	1 week
2009-09-22 17:45:28 +00:00
George V. Neville-Neil
2e7de50933 Add counters for the i7 architecture which were accidentally left
out of the original commit of i7 support.  These are all the counters
on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures
Software Developer's Manual Vol 3B_, June 2009.  Almost all
of these counters relate to operations on the L2 cache.

Reviewed by:	jkoshy
MFC after:	1 month
2009-09-01 17:55:37 +00:00
John Baldwin
21157ad3b1 Adjust the handling of the local APIC PMC interrupt vector:
- Provide lapic_disable_pmc(), lapic_enable_pmc(), and lapic_reenable_pmc()
  routines in the local APIC code that the hwpmc(4) driver can use to
  manage the local APIC PMC interrupt vector.
- Do not enable the local APIC PMC interrupt vector by default when
  HWPMC_HOOKS is enabled.  Instead, the hwpmc(4) driver explicitly
  enables the interrupt when it is succesfully initialized and disables
  the interrupt when it is unloaded.  This avoids enabling the interrupt
  on unsupported CPUs which may result in spurious NMIs.

Reported by:	rnoland
Reviewed by:	jkoshy
Approved by:	re (kib)
MFC after:	2 weeks
2009-08-14 21:05:08 +00:00
Attilio Rao
ca2d94bef7 Fix a LOR between pmc_sx and proctree/allproc when creating a new thread
for the pmclog.

Reported by:	Ryan Stone <rstone at sandvine dot com>
Tested by:	Ryan Stone <rstone at sandvine dot com>
Sponsored by:	Sandvine Incorporated
2009-06-25 20:59:37 +00:00
Jeff Roberson
597979c4b7 - Add support for nehalem/corei7 cpus. This supports all of the core
counters defined in the reference manual.  It does not support the
   'uncore' events.

Reviewed by:	jkoshy
Sponsored by:	Nokia
2009-01-27 07:29:37 +00:00
Joseph Koshy
8d8b174004 Bug fixes:
- Initialize variables before use.
- Remove a KASSERT() that could falsely trigger if there are other sources
  of NMIs in the system.

Efficiency tweak:
- When checking PMCs that overflowed, ignore PMCs that were not configured for
  sampling.
2008-12-16 11:04:02 +00:00
Joseph Koshy
1ad08c6ac1 - Disambiguate a few panic messages.
- Style fixes: wrap long lines, parenthesize return values.
2008-12-15 14:41:55 +00:00
Joseph Koshy
6fe00c7876 - Bug fix: prevent a thread from migrating between CPUs between the
time it is marked for user space callchain capture in the NMI
  handler and the time the callchain capture callback runs.

- Improve code and control flow clarity by invoking hwpmc(4)'s user
  space callchain capture callback directly from low-level code.

Reviewed by:	jhb (kern/subr_trap.c)
Testing (various patch revisions): gnn,
		Fabien Thomas <fabien dot thomas at netasq dot com>,
		Artem Belevich <artemb at gmail dot com>
2008-12-13 13:07:12 +00:00
Joseph Koshy
b4d091f3a4 Fixes for Core2 Extreme support.
Submitted by:	 "Artem Belevich" <artemb at gmail dot com>
2008-12-03 17:30:36 +00:00
Joseph Koshy
a10c6ee6bd Add aliases that map architectural event names to fixed function counters. 2008-12-03 15:23:08 +00:00
Joseph Koshy
dfd9bc23c9 - Efficiency tweak: when checking for PMC overflows, only go to
hardware for PMCs that have been configured for sampling.

- Bug fix: acknowledge PMC hardware overflows irrespective of the
  the (software) PMC's state.
2008-12-02 10:46:35 +00:00
Joseph Koshy
cb2394085d Improve a comment. 2008-11-30 05:10:14 +00:00
Joseph Koshy
0cfab8ddc1 - Add support for PMCs in Intel CPUs of Family 6, model 0xE (Core Solo
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
  model 0x1C (Atom).

  In these CPUs, the actual numbers, kinds and widths of PMCs present
  need to queried at run time.  Support for specific "architectural"
  events also needs to be queried at run time.

  Model 0xE CPUs support programmable PMCs, subsequent CPUs
  additionally support "fixed-function" counters.

- Use event names that are close to vendor documentation, taking in
  account that:
  - events with identical semantics on two or more CPUs in this family
    can have differing names in vendor documentation,
  - identical vendor event names may map to differing events across
    CPUs,
  - each type of CPU supports a different subset of measurable
    events.

  Fixed-function and programmable counters both use the same vendor
  names for events.  The use of a class name prefix ("iaf-" or
  "iap-" respectively) permits these to be distinguished.

- In libpmc, refactor pmc_name_of_event() into a public interface
  and an internal helper function, for use by log handling code.

- Minor code tweaks: staticize a global, freshen a few comments.

Tested by:	gnn
2008-11-27 09:00:47 +00:00
Jung-uk Kim
5113aa0af3 Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by:	jhb, peter (early amd64 version)
2008-11-26 19:25:13 +00:00
Joseph Koshy
c85e8dcf18 Unbreak LINT. 2008-11-22 12:34:49 +00:00
Joseph Koshy
7dada26401 Print PMC widths in the initialization announcement. 2008-11-16 04:21:59 +00:00