controllers (PDC203** PDC206**).
This also adds preliminary support for the Promise SX4/SX4000 but *only*
as a "normal" Promise ATA controller (ATA RAID's are supported though
but only RAID0, RAID1 and RAID0+1).
This cuts off yet another 5-8% of the command overhead on promise controllers,
making them the fastest we have ever had support for.
Work is now continuing to add support for this in ATA RAID, to accellerate
ATA RAID quite a bit on these controllers, and especially the SX4/SX4000
series as they have quite a few tricks in there..
This commit also adds a few fixes to the SATA code needed for proper support.
This adds support for cardbus ATA/SATA controllers. I get roughly the
same transfer speeds as on true PCI controllers. Nice to be able to add
a couble of "real" disks to a laptop :)
instead of taskqueue_swi. This shaves from 1 to 10% of the overhead.
Overhaul the locking once more, there was a few possible races that
are now closed.
This gives +10% performance on simple tests, so definitly worth it.
A few percent more could be had by not using M_ZERO'd alloc's, but
we then need to clear fields all over the place to be safe, and
that was deemed not worth the trouble (and it makes life dangerous).
of the leftovers from the old version that really doesn't work anymore.
Add a reset function for host-end of the ATA channel. This is needed
for the SiI3112 in order to whack it back to reality if a device
locks up the SATA interface (thereby preventing that we can reset the
device). The result is that ATA now recovers from the timeouts that
happens with the SiI3112A and more or less all disks based on old
PATA electronics with a Marvell PATA->SATA converter. This includes
lots of the popular SATA dongles and the WDC Raptor disks..
in connection with Marvell based SATA->PATA dongles.
The problem was caused by a combination of things working
together to make it hard to spot...
The ATA driver has always started the ATA command, then build
the SG list for DMA and then finally started the DMA engine.
While this is according to specs, it poses a potential
problem as some controllers apparently do not allow for unlimitted
time between starting the ATA command and starting the DMA engine.
At about the same time as ATAng was committed there were lots
of other changes applied, some of which was locking in parts
that causes the busdma load functions to take significantly
longer to load the SG list.
This pushed the time spent between starting the ATA command and
starting the DMA engine over the hill for some controllers
(especially the Silicon Image DS3112a) and caused what looked
like lost interrupts.
The solution is to get all the SG list work or rather all
busdma related stuff done before we even try to start anything.
This has the nice side effect of seperating busdma out the
way it should be, so the working of the ATA machinery is not
cluttered up with busdma droppings, making the code easier
to read and understand.
Restructure the way ATA/ATAPI commands are processed, use a common
ata_request structure for both. This centralises the way requests
are handled so locking is much easier to handle.
The driver is now layered much more cleanly to seperate the lowlevel
HW access so it can be tailored to specific controllers without touching
the upper layers. This is needed to support some of the newer
semi-intelligent ATA controllers showing up.
The top level drivers (disk, ATAPI devices) are more or less still
the same with just corrections to use the new interface.
Pull ATA out from under Gaint now that locking can be done in a sane way.
Add support for a the National Geode SC1100. Thanks to Soekris engineering
for sponsoring a Soekris 4801 to make this support.
Fixed alot of small bugs in the chipset code for various chips now
we are around in that corner anyways.
Clean up the DMA interface too much unneeded stuff crept in with
the busdma code back when.
Modify the ATA_IN* / ATA_OUT* macros so that resource and offset
are gotten from a table. That allows for new chipsets that doesn't
nessesarily have things ordered the good old way. This also removes
the need for the wierd PC98 resource functions.
Tested on: i386, PC98, Alpha, Sparc64
This moves all chipset specific code to a new file 'ata-chipset.c'.
Extensive use of tables and pointers to avoid having the same switch
on chipset type in several places, and to allow substituting various
functions for different HW arch needs.
Added PIO mode setup and all DMA modes.
Support for all known SiS chipsets. Thanks to Christoph Kukulies for
sponsoring a nice ASUS P4S8X SiS648 based board for this work!
Tested on: i386, PC98, alpha and sparc64
Properly handle the newer Promise SuperSwap 1000 enclosures.
Print out what kind of enclosure was found in the probe.
Misc cleanups in the enclosure handling code.
Sponsored by: Advanis Inc.
This mostly consists of functionality to serialize accesses to
the two ATA channels (which can also be used to "fix" certain
PCI based controllers).
Add support for Acard controllers.
Enable the ATA driver in PC98 GENERIC, and add device hints.
Update man page with latest support.
The PC98 core team has kindly provided me with a PC98
machine that made this all possible, thanks to all that
contributed to that effort, without that this would
probably newer have been possible..
Approved by: re@
Overhaul of the attach/detach code and structures, there were some nasty
bugs in the old implementation. This made it possible to collapse the
ATA/ATAPI device control structures into one generic structure.
A note here, the kernel is NOT ready for detach of active devices,
it fails all over in random places, but for inactive devices it works.
However for ATA RAID this works, since the RAID abstration layer
insulates the buggy^H^H^H^H^H^Hfragile device subsystem from the
physical disks.
Proberly detect the RAID's from the BIOS, and mark critical RAID1
arrays as such, but continue if there is enough of the mirror left
to do so.
Properly fail arrays on a live system. For RAID0 that means return EIO,
and for RAID1 it means continue on the still working part of the mirror
if possible, else return EIO.
If the state changes, log this to the console.
Allow for Promise & Highpoint controllers/arrays to coexist on the
same machine. It is not possible to distribute arrays over different
makes of controllers though.
If Promise SuperSwap enclosures are used, signal disk state on the
status LED on the front.
Misc fixes that I had lying around for various minor bugs.
Sponsored by: Advanis Inc.
Add tagged queueing support for new IBM drives.
Add support for Yet Another Promise ATA 100 chip.
Flush disk cache on close.
Dont flush the disk cache on BIO_ORDERED anymore.
Cleanup the tests for DMA on ATAPI devices.
Allow to share ALL irq's even the std irg 14 & 15.
Fix calculation bug in end of media code on CD's.
Add REZERO on opening a CDR/CDRW.
Cleanup ataioctl a bit.
see atacontrol(8) for more.
Also the ATA_ENABLE_ATAPI_DMA, ATA_ENABLE_WC and ATA_ENABLE_TAGS
options are gone, use the tuneables listed in ata.4 instead from
the loader (this makes it possible to switch off DMA before the
driver has to touch the devices on broken hardware).
Proberly fail outstanding bio requests on devices that are detached.
This makes it possible to change between disk/cdrom/dvd/whathaveyou
in a notebook, just by suspending it, changing the device in the
bay (or what you model calls it), unsuspend and the ATA driver
will figure out what disappeared and properly fail those, and attach
any new devices found.
This is due to a bug that has been in there since Warneer did the
PCCARD stuff, the altioaddr is not offset 8 its offset 14 from
the base address.
Also only probe the master device, no known PCCARD ATA thingies
has a slave AFAIK..
IBM's DPTA and DTLA series of drives (no other disk vendors are known
to support this) on non-Promise controllers (promise controllers lockup
when given the tagged queuing specific commands).
It gives especially master/slave comboes about 5% better performance.
Add support for the Promise ATA100 OEM chip (pdc20265)
Add support for the Cyrix 5530
Change the way status is read from the drives, use the alternate
status reg when possible.
Better support for DEVFS, the acdXtY devices are now created when needed.
Lots of little cleanups.
Promise Ultra100 / Fasttrak100
HighPoint HPT370 controllers (fx Abit KA7-100 onboard ctrl, Abit HotRod 100)
Intel ICH2 (Intel 815E based motherboards)
So far I can read >90MB/s on the Promise and the HPT370.
I can write >64MB/s on the promise and >50MB/s on the HPT370 so it seems
writing is still done in ATA66 mode :(
The ICH2 support is untested as of yet...
