Commit Graph

465 Commits

Author SHA1 Message Date
Alexander Motin
e887c1dedf Add IOMMU PCI subclass, found on Tyan S8236 motherboard.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2014-05-20 14:39:22 +00:00
Steven Hartland
8197f45b6a Make uninteresting PCI devices with no attached drivers only print out
on a verbose boot

MFC after:	2 weeks
2014-04-30 16:42:12 +00:00
Ryan Stone
c8912fcbdf Correct a PCI enumeration bug introduced in r264011
Ensure that first_func is set to 0 on every iteration of the PCI slot
enumeration loop after the first.  There is a continue statement that would
cause first_func to stay at 1 any PCI device where slot 0 has no functions
until we find a slot that does have a function.  This would cause us to
not enumerate the first PCI function on the device.

Credit to markj@ for spotting the bug.

X-MFC-With: r264011
2014-04-03 22:32:12 +00:00
Ryan Stone
55d3ea1731 Add support for PCIe ARI
PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions.  It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number.  Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.

This is enabled by default, but it's expected to be a no-op on currently
supported hardware.  It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.

Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
2014-04-01 16:02:02 +00:00
Ryan Stone
5605a99e36 Add a method to get the PCI RID for a device.
Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
2014-04-01 15:47:24 +00:00
Ryan Stone
7036ae46bf Revert PCI RID changes.
My PCI RID changes somehow got intermixed with my PCI ARI patch when I
committed it.  I may have accidentally applied a patch to a non-clean
working tree.  Revert everything while I figure out what went wrong.

Pointy hat to: rstone
2014-04-01 15:06:03 +00:00
Ryan Stone
d773f48b1e Add a method to get the PCI Routing ID for a device
Reviewed by:	kib
Sponsored by:	Sandvine, Inc
2014-04-01 14:49:25 +00:00
John Baldwin
4edef187b8 Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge
I/O windows, the default is to preserve the firmware-assigned resources.
PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture
defines a PCI_RES_BUS resource type.
- Add a helper API to create top-level PCI bus resource managers for each
  PCI domain/segment.  Host-PCI bridge drivers use this API to allocate
  bus numbers from their associated domain.
- Change the PCI bus and CardBus drivers to allocate a bus resource for
  their bus number from the parent PCI bridge device.
- Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the
  full range of bus numbers from secbus to subbus from their parent bridge.
  The drivers also always program their primary bus register.  The bridge
  drivers also support growing their bus range by extending the bus resource
  and updating subbus to match the larger range.
- Add support for managing PCI bus resources to the Host-PCI bridge drivers
  used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib).
- Define a PCI_RES_BUS resource type for amd64 and i386.

Reviewed by:	imp
MFC after:	1 month
2014-02-12 04:30:37 +00:00
John Baldwin
0070c94be9 Add two tunables to ignore certain firmware-assigned resources. These
are mostly useful for debugging.
- hw.pci.clear_bars ignores all firmware-assigned ranges for BARs when
  set.
- hw.pci.clear_pcib ignores all firmware-assigned ranges for PCI-PCI
  bridge I/O windows when set.

MFC after:	1 week
2014-02-05 20:52:12 +00:00
John Baldwin
b986a7ec18 Simplify pci_reserve_map() by calling resource_list_reserve() to allocate
the resource after creating a resource list entry rather than reimplementing
it by hand.

MFC after:	1 week
2014-02-05 20:47:49 +00:00
John Baldwin
8d280bcbfc Properly set the alignment flags when allocating the initial range for a
BAR.  This only really matters when pci_do_realloc_bars is enabled and
the initial allocation of a specific range fails.

MFC after:	1 week
2014-02-05 19:24:16 +00:00
John Baldwin
84b755dfe5 Add support for displaying VPD for PCI devices via pciconf.
- Store the length of each read-only VPD value since not all values are
  guaranteed to be ASCII values (though most are).
- Add a new pciio ioctl to fetch VPD for a single PCI device.  The values
  are returned as a list of variable length records, one for the device
  name and each keyword.
- Add a new -V flag to pciconf's list mode which displays VPD data for
  each device.

MFC after:	1 week
2014-01-20 20:56:09 +00:00
Konstantin Belousov
c54a713f6a Make pci_get_dma_tag() non-static. Since the function is only
referenced by pointer, making it non-static should not have even the
negligible impact on the existing code.

Reviewed by:	jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2013-10-24 20:29:29 +00:00
Konstantin Belousov
feb96b46a2 Move the PCI_DMA_BOUNDARY definition into the pcivar.h.
Reviewed by:	jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2013-10-24 20:21:37 +00:00
John Baldwin
c825d4dc50 Properly handle I/O windows in bridges with the ISA enable bit set. These
beasts still exist unfortunately.  More details can be found in other
references, but the short version is that bridges with this bit set ignore
I/O port ranges that alias to valid ISA I/O port ranges.  In the driver
this requires not allocating these alias regions from the parent device
(so they are free to be acquired by ISA devices), and ensuring no child
devices use resources from these alias regions.
- Change the pcib_window structure to allow for an array of backing
  resources rather than a single resource and update the existing code
  to cope with this.  Some of the coping requires using the saved
  base and limit values in pcib_window instead of using rman operations
  on the backing resource.
- Add special handling for allocating and adjusting the I/O port window
  of an ISA-enabled bridge to only allocate the non-alias ranges and
  add those to the associated resource manager.
- Reject I/O port allocations for a fixed request that conflicts with an
  ISA alias range.
- Remove the "no prefected decode" verbose printf during boot.  The absence
  of a "prefetched decode" line is sufficient.
- Replace the "subtractively decoded bridge" verbose printf with a single
  printf that lists all the "special" decoding modes of a bridge: ISA,
  subtractive, and VGA.
- Add a custom bus_release_resource() method to the PCI bus driver so that
  it can properly free resources for I/O windows of PCI-PCI bridges.
  (These resources are not stored in the bridge device's resource list.)

PR:		misc/179033
MFC after:	2 weeks
2013-07-18 15:17:11 +00:00
Marius Strobl
68e9cbd385 - As it turns out, not only MSI-X is broken for devices passed through by
VMware up to at least ESXi 5.1. Actually, using INTx in that case instead
  may still result in interrupt storms, with MSI being the only working
  option in some configurations. So introduce a PCI_QUIRK_DISABLE_MSIX quirk
  which only blacklists MSI-X but not also MSI and use it for the VMware
  PCI-PCI-bridges. Note that, currently, we still assume that if MSI doesn't
  work, MSI-X won't work either - but that's part of the internal logic and
  not guaranteed as part of the API contract. While at it, add and employ
  a pci_has_quirk() helper.
  Reported and tested by: Paul Bucher
- Use NULL instead of 0 for pointers.

Submitted by:	jhb (mostly)
Approved by:	jhb
MFC after:	3 days
2013-07-09 23:12:26 +00:00
John Baldwin
e35ce1f271 Make detaching drivers from PCI devices more robust. While here, fix a
bug where a PCI device would be powered down if it failed to probe, but
not when its driver was detached (e.g. via kldunload).
- Add a new helper method resource_list_release_active() which forcefully
  releases any active resources of a specified type from a resource list.
- Add a bus_child_detached method for the PCI bus driver which forces any
  active resources to be released (and whines to the console if it finds
  any) and then powers the device down.
- Call pci_child_detached() if we fail to probe a device when a driver
  is kldloaded.  This isn't perfect but can avoid leaking resources
  from a probe() routine in the kldload case.

Reviewed by:	imp, brooks
MFC after:	1 month
2013-06-27 20:21:54 +00:00
John Baldwin
19e1c4d115 Disable hw.pci.realloc_bars by default. It wasn't needed for the original
tester of this fix, and realloc_bars breaks some other cases as a small
BAR that is reallocated can end up grabbing space needed by a much larger
BAR in the existing window of a PCI-PCI bridge.

MFC after:	3 days
2013-06-24 18:30:44 +00:00
John Baldwin
5569a8b8df Revision 233677 broke certain machines. Specifically, if the firmware/BIOS
assigned conflicting ranges to BARs then leaving the BARs alone could
result in one device stealing mmio accesses intended to go to a second
device.  Prior to 233677 the PCI bus driver attempted to handle this case
by clearing the BAR to 0 depending on BARs based at 0 not decoding (which
is not guaranteed to be true).  Now when a conflicting BAR is detected the
following steps are taken:

 1) If hw.pci.realloc_bars (a new tunable) is enabled (default is enabled),
    then ignore the current BAR setting from the firmware and attempt to
    allocate a fresh resource range for the BAR.

 2) If 1) failed (or was disabled), disable decoding for the relevant
    BAR type (e.g. disable mem decoding for a memory BAR) and emit a
    warning if booting verbose.

Tested by:	Alex Keda <admin@lissyara.su>
MFC after:	1 week
2013-05-09 19:24:50 +00:00
Marius Strobl
4495286fb2 - Complete r231621 by also blacklisting the bridge used by VMware for PCIe
devices. While at it, update the comment now that we know that MSI-X
  doesn't work with ESXi 5.1 for Intel 82576 either and the underlying issue
  is a bug in the MSI-X allocation code of the hypervisor.
  Reported by: Harald Schmalzbauer
- Make the nomatch table const.

MFC after:	1 week
2013-03-02 15:54:02 +00:00
Neel Natu
5bf80db676 Remove the quirk to allow use of MSI when the guest is running inside bhyve.
This became redundant after the hostbridge presented to the guest started
advertising the PCI-E capability (r246846).

Obtained from:	NetApp
2013-02-28 01:00:32 +00:00
Neel Natu
a61359a9a6 Add quirk to indicate that the bhyve hostbridge is capable of supporting
MSI and MSI-X even though it does not advertise the PCI-E capability
itself.

Obtained from:	NetApp
2013-01-05 18:48:23 +00:00
Dimitry Andric
29658c96ce Remove duplicate const specifiers in many drivers (I hope I got all of
them, please let me know if not).  Most of these are of the form:

static const struct bzzt_type {
	[...list of members...]
} const bzzt_devs[] = {
	[...list of initializers...]
};

The second const is unnecessary, as arrays cannot be modified anyway,
and if the elements are const, the whole thing is const automatically
(e.g. it is placed in .rodata).

I have verified this does not change the binary output of a full kernel
build (except for build timestamps embedded in the object files).

Reviewed by:	yongari, marius
MFC after:	1 week
2012-11-05 19:16:27 +00:00
Gavin Atkinson
3cdfd8d3b2 The correct generic term for PCIS_STORAGE_NVM is "NVM" not "NVM Express".
Submitted by:	jimharris
MFC after:	6 days
2012-09-20 08:30:17 +00:00
Gavin Atkinson
a5c5eaae8c Recognise NVM Express devices and pretty-print their name.
MFC after:	1 week
2012-09-19 18:22:14 +00:00
Gavin Atkinson
389c8bd51e Align the PCI Express #defines with the style used for the PCI-X
#defines.  This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
  s/PCIR_EXPRESS_/PCIER_/g
  s/PCIM_EXP_/PCIEM_/g
  s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with:	jhb
MFC after:	1 week
2012-09-18 22:04:59 +00:00
John Baldwin
d79a477554 Only check to see if a memory resource is a PCI ROM BAR when activating
and deactivating PCI resources.  Previously, if a device had more than
48 MSI interrupts, then activating message 48 (which has a rid == PCIR_BIOS)
would incorrectly try to enable the PCI ROM BAR.

Tested by:	Olivier Cinquin  ocinquin uci edu
MFC after:	3 days
2012-05-23 13:41:12 +00:00
Jung-uk Kim
64d87e5bf2 Fix couple of style nits. 2012-03-29 19:29:24 +00:00
Jung-uk Kim
5757b18266 Revert r233662 and generalize the hack. Writing zero to BAR actually does
not disable it and it is even harmful as hselasky found out.  Historically,
this code was originated from (OLDCARD) CardBus driver and later leaked into
PCI driver when CardBus was newbus'ified and refactored with PCI driver.
However, it is not really necessary even for CardBus.

Reviewed by:	hselasky, imp, jhb
2012-03-29 19:26:39 +00:00
John Baldwin
0d95597ca9 Use a more proper fix for enabling HT MSI mapping windows on Host-PCI
bridges.  Rather than blindly enabling the windows on all of them, only
enable the window when an MSI interrupt is enabled for a device behind
the bridge, similar to what already happens for HT PCI-PCI bridges.

To implement this, each x86 Host-PCI bridge driver has to be able to
locate it's actual backing device on bus 0.  For ACPI, use the _ADR
method to find the slot and function of the device.  For the non-ACPI
case, the legacy(4) driver already scans bus 0 looking for Host-PCI
bridge devices.  Now it saves the slot and function of each bridge that
it finds as ivars that the Host-PCI bridge driver can then use in its
pcib_map_msi() method.

This fixes machines where non-MSI interrupts were broken by the previous
round of HT MSI changes.

Tested by:	bapt
MFC after:	1 week
2012-03-29 19:03:22 +00:00
Hans Petter Selasky
0e8542711a Fix for boot issue: Don't disable BARs on AGP devices. In general:
Don't disable BARs on any PCI display devices, because doing that can
sometimes cause the main memory bus to stop working, causing all
memory reads to return nothing but 0xFFFFFFFF, even though the memory
location was previously written.  After a while a privileged
instruction fault will appear and then nothing more can be debugged.
The reason for this behaviour is unknown.

MFC after:	1 week
2012-03-29 15:33:44 +00:00
Jung-uk Kim
96ec27d42b Add a PCI quirk to ignore PCI map registers from configuration space.
For example, some BIOS for AMD SB600 south bridge may map HPET MMIO base
address as a memory BAR for SMBus controller depending on a PM register
configuration.  Before r231161 (and r232086, subsequent MFC to stable/9),
it was not fatal but hpet(4) just failed to attach.  Since we probe and
attach HPET earlier than PCI devices now, it caused unfortunate hard lockup.
With this patch, it does not hang any more and HPET works at the same time.
Clean up some style nits while I am in the neighborhood.

PR:		kern/165647
Reviewed by:	jhb
MFC after:	3 days
2012-03-14 23:25:46 +00:00
Alexander Kabaev
6e9dcee4ca Save more of config space for PCI Express and PCI-X devices.
Expand pci_save_state and pci_restore_state to save more of
the config state for PCI Express and PCI-X devices. Various
writable control registers are present in PCI Express that
can potentially be lost over suspend/resume cycle.

This change is modeled after similar functionality in Linux.

Reviewed by: wlosh,jhb
MFC after:  1 month
2012-03-08 21:09:34 +00:00
John Baldwin
e80cc28c1d Remove the PAE-specific 2GB DMA boundary since HEAD now supports a proper 4G
boundary for PAE.
2012-03-07 18:57:09 +00:00
John Baldwin
8766350924 Simplify the PCI bus dma tag code a bit. First, don't create a tag at
all for platforms that only have 32-bit bus addresses.  Second, remove
the 'tag_valid' flag from the softc.  Instead, if we don't create a
tag in pci_attach_common(), just cache the value of our parent's tag
so that we always have a valid tag to return.
2012-03-07 18:50:33 +00:00
John Baldwin
c668000b69 Expand the set of APIs available for locating PCI capabilities:
- pci_find_extcap() is repurposed to be used for fetching PCI-express
  extended capabilities (PCIZ_* constants in <dev/pci/pcireg.h>).
- pci_find_htcap() can be used to locate a specific HyperTransport
  capability (PCIM_HTCAP_* constants in <dev/pci/pcireg.h>).
- Cache the starting location of the PCI-express capability for PCI-express
  devices in PCI device ivars.
2012-03-03 18:08:57 +00:00
John Baldwin
180aa2f0fc Fix a typo. 2012-03-03 14:24:39 +00:00
John Baldwin
1b1596a3b3 - Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge.
The tag enforces a single restriction that all DMA transactions must not
  cross a 4GB boundary.  Note that while this restriction technically only
  applies to PCI-express, this change applies it to all PCI devices as it
  is simpler to implement that way and errs on the side of caution.
- Add a softc structure for PCI bus devices to hold the bus_dma tag and
  a new pci_attach_common() routine that performs actions common to the
  attach phase of all PCI bus drivers.  Right now this only consists of
  a bootverbose printf and the allocate of a bus_dma tag if necessary.
- Adjust all PCI bus drivers to allocate a PCI bus softc and to call
  pci_attach_common() from their attach routines.

MFC after:	2 weeks
2012-03-02 20:38:04 +00:00
John Baldwin
9415d1e0ac Add pci_save_state() and pci_restore_state() wrappers around
pci_cfg_save() and pci_cfg_restore() for device drivers to use when
saving and restoring state (e.g. to handle device-specific resets).

Reviewed by:	imp
MFC after:	2 weeks
2012-03-01 20:20:55 +00:00
John Baldwin
49329d2825 Use pci_printf() instead of a home-rolled version in the VPD parsing code. 2012-02-29 22:06:44 +00:00
Marius Strobl
bb631bf94d - As it turns out, MSI-X is broken for at least LSI SAS1068E when passed
through by VMware so blacklist their PCI-PCI bridge for MSI/MSI-X here.
  Note that besides currently there not being a quirk type that disables
  MSI-X only and there's no evidence that MSI doesn't work with the VMware
  pass-through, it's really questionable whether MSI generally works in
  that setup as VMware only mention three know working devices [1, p. 4].
  Also not that this quirk entry currently doesn't affect the devices
  emulated by VMware in any way as these don't claim support MSI/MSI-X to
  begin with. [2]
  While at it, make the PCI quirk table const and static.
- Remove some duplicated empty lines.
- Use DEVMETHOD_END.

PR:		163812, http://forums.freebsd.org/showthread.php?t=27899 [2]
Reviewed by:	jhb
MFC after:	3 days
2012-02-14 00:18:35 +00:00
John Baldwin
df4ce32fcb Properly return success once a matching VPD entry is found in
pci_get_vpd_readonly_method().  Previously the loop was always running
to completion and falling through to failing with ENXIO.

PR:		kern/164313
Submitted by:	Chuck Tuffli  chuck tuffli net
MFC after:	1 week
2012-01-19 21:38:19 +00:00
Hans Petter Selasky
ff11fd7fa7 Add missing XHCI early takeover code. The XHCI takeover code
is supposed to disable the BIOS from using the XHCI controller
after bootup.

Approved by:	re (kib)
Reported by:	Mike Tancsa
MFC after:	1 week
2011-07-22 15:37:23 +00:00
Marius Strobl
eb06e7719b PCIB_ALLOC_MSIX() may already fail on the first pass, f.e. when the PCI-PCI
bridge is blacklisted. In that case just return from pci_alloc_msix_method(),
otherwise we continue without a single MSI-X resource, causing subsequent
attempts to use the seemingly available resource to fail or when booting
verbose a NULL-pointer dereference of rle->start when trying to print the
IRQ in pci_alloc_msix_method().

Reviewed by:	jhb
MFC after:	1 week
2011-07-13 18:35:47 +00:00
Konstantin Belousov
141c08f9c0 Implement pci_find_class(9), the function to find a pci device by its class.
Sponsored by:	The FreeBSD Foundation
Reviewed by:	jhb
MFC after:	1 week
2011-07-09 14:30:13 +00:00
John Baldwin
35d200101a Minor whitespace and style fixes. 2011-06-21 19:31:31 +00:00
John Baldwin
0d439b5f93 More properly handle Cardbus cards that that store their CIS in a BAR after
the recent changes to track BAR state explicitly.  The code would now
attempt to add the same BAR twice in this case.  Instead, change this so
that it recognizes this case and only adds it once and do not delete the
BAR outright after parsing the CIS.

Tested by:	bschmidt
2011-06-06 13:21:11 +00:00
John Baldwin
83c41143ca Reimplement how PCI-PCI bridges manage their I/O windows. Previously the
driver would verify that requests for child devices were confined to any
existing I/O windows, but the driver relied on the firmware to initialize
the windows and would never grow the windows for new requests.  Now the
driver actively manages the I/O windows.

This is implemented by allocating a bus resource for each I/O window from
the parent PCI bus and suballocating that resource to child devices.  The
suballocations are managed by creating an rman for each I/O window.  The
suballocated resources are mapped by passing the bus_activate_resource()
call up to the parent PCI bus.  Windows are grown when needed by using
bus_adjust_resource() to adjust the resource allocated from the parent PCI
bus.  If the adjust request succeeds, the window is adjusted and the
suballocation request for the child device is retried.

When growing a window, the rman_first_free_region() and
rman_last_free_region() routines are used to determine if the front or
end of the existing I/O window is free.  From using that, the smallest
ranges that need to be added to either the front or back of the window
are computed.  The driver will first try to grow the window in whichever
direction requires the smallest growth first followed by the other
direction if that fails.

Subtractive bridges will first attempt to satisfy requests for child
resources from I/O windows (including attempts to grow the windows).  If
that fails, the request is passed up to the parent PCI bus directly
however.

The PCI-PCI bridge driver will try to use firmware-assigned ranges for
child BARs first and only allocate a "fresh" range if that specific range
cannot be accommodated in the I/O window.  This allows systems where the
firmware assigns resources during boot but later wipes the I/O windows
(some ACPI BIOSen are known to do this) to "rediscover" the original I/O
window ranges.

The ACPI Host-PCI bridge driver has been adjusted to correctly honor
hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge
makes a wildcard request for an I/O window range.

The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option
is enabled.  This is a transition aide to allow platforms that do not
yet support bus_activate_resource() and bus_adjust_resource() in their
Host-PCI bridge drivers (and possibly other drivers as needed) to use the
old driver for now.  Once all platforms support the new driver, the
kernel option and old driver will be removed.

PR:		kern/143874 kern/149306
Tested by:	mav
2011-05-03 17:37:24 +00:00
John Baldwin
d2c9344ff9 Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver,
generic PCI-PCI bridge driver, x86 nexus driver, and x86 Host to PCI bridge
drivers.
2011-05-02 14:13:12 +00:00
John Baldwin
8adcbaed13 Only align MSI message groups based on the number of messages being
allocated, not the maximum number of messages the device supports.  The
spec only requires the former, and I believe I implemented the latter due
to misunderstanding an e-mail.  In particular, this fixes an issue where
having several devices that all support 16 messages can run out of
IDT vectors on x86 even though the driver only uses a single message.

Submitted by:	Bret Ketchum  bcketchum of gmail
MFC after:	1 week
2011-04-27 20:08:44 +00:00