Commit Graph

465 Commits

Author SHA1 Message Date
John Baldwin
589d604bf9 Disable decoding of BARs by devices before we trash the value in the BAR
by writing all 1's to it to determine its length.  This fixes issues with
MCFG on at least some machines where a trashed BAR claimed subsequent
attempts at PCI config transactions because the addresses in the MCFG
window fell in the decoding range of the BAR.

In general it is a bad idea to leave the BARs enabled while we are
frobbing with them in this manner.

Sleuthing by:  tegge
MFC after:     1 week
2009-01-16 22:22:30 +00:00
Alexander Motin
2e013ce0e3 Add ADMA, SATA and SAS mass storage subclasses reporting. 2008-11-13 19:57:33 +00:00
Alexander Motin
c5343d0981 Add HDA multimedia subclass. 2008-10-21 21:53:55 +00:00
Alexander Motin
a9217b5f74 Add "SD host controller" subclass name. 2008-10-21 20:55:41 +00:00
Warner Losh
696771ee0a Cope with errors from device_get_children(). These errors can happen
only in low memory situations, so the error fork of these fixes is
lightly tested, but they should do the least-wrong thing...

Submitted by:	Hans Petter Selasky
2008-08-23 07:23:52 +00:00
Warner Losh
de5d443f0f Cosmetic nit. 2008-08-23 07:18:30 +00:00
Warner Losh
e33abcc50c Change -1 to 0xfffffffful since the interface returns uint32_t. 2008-08-09 03:54:12 +00:00
John Baldwin
73492bc0b1 Remove the second check for a 64-bit BAR value on a 32-bit system in
pci_add_map().  First, this condition is already handled earlier in
the function.  Second, as written the check would never fire as the
'start' value was overwritten with a long value (rman_get_start() returns
long) before the comparison was done.

Discussed with:	imp
MFC after:	2 weeks
2008-08-05 21:04:00 +00:00
John Baldwin
e29bfa9ed9 If the kernel fails to allocate resources for the initial value of a BAR
for a PCI device during the boot-time probe of the parent PCI bus, then
zero the BAR and clear the resource list entry for that BAR.  This forces
the PCI bus driver to request a valid resource range from the parent bridge
driver when the device driver tries to allocate the BAR.  Similarly, if the
initial value of a BAR is a valid range but it is > 4GB and the current OS
only has 32-bit longs, then do a full teardown of the initial value of the
BAR to force a reallocation.

Reviewed by:	imp
MFC after:	1 week
2008-08-05 18:24:41 +00:00
Luoqi Chen
4522ac77de SATA device on some nForce based boards could get confused if MSI is not
used but MSI to HyperTransport IRQ mapping is enabled, and would act as
if MSI is turned on, resulting in interrupt loss.

This commit will,
1. enable MSI mapping on a device only when MSI is enabled for that
   device and the MSI address matches the HT mapping window.
2. enable MSI mapping on a bridge only when a downstream device is
   allocated an MSI address in the mapping window

PR:		kern/118842
Reviewed by:	jhb
MFC after:	1 week
2008-07-23 09:44:36 +00:00
John Baldwin
138e8d08b0 Relax the check for a PCI-express chipset by assuming the system is a
PCI-express chipset (and thus has functional MSI) if there are any
PCI-express devices in the system, not requiring a root port device.

With PCI-X the chipset detection has to be very conservative because there
are known systems with PCI-X devices that do not appear to have PCI-X
chipsets.  However, with PCI-express I'm not sure it is possible to have
a PCI-express device in a system with a non-PCI-express chipset.  If we
assume that is the case then this change is valid.  It is also required
for at least some PCI-express systems that don't have any devices with
a root port capability (some ICH9 systems).

MFC after:	1 week
Reported by:	jfv
2008-02-01 20:31:09 +00:00
Jung-uk Kim
4ea603ec6b Make VPD register access more robust:
- Implement timing out of VPD register access.[1]
- Fix an off-by-one error of freeing malloc'd space when checksum is invalid.
- Fix style(9) bugs, i.e., sizeof cannot be followed by space.
- Retire now obsolete 'hw.pci.enable_vpd' tunable.

Submitted by:	cokane (initial revision)[1]
Reviewed by:	marius (intermediate revision)
Silence from:	jhb, jmg, rwatson
Tested by:	cokane, jkim
MFC after:	3 days
2007-11-16 20:49:34 +00:00
Marius Strobl
55aaf894e8 Make the PCI code aware of PCI domains (aka PCI segments) so we can
support machines having multiple independently numbered PCI domains
and don't support reenumeration without ambiguity amongst the
devices as seen by the OS and represented by PCI location strings.
This includes introducing a function pci_find_dbsf(9) which works
like pci_find_bsf(9) but additionally takes a domain number argument
and limiting pci_find_bsf(9) to only search devices in domain 0 (the
only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are
changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order
to no longer report false positives when searching for siblings and
dupe devices in the same domain respectively.
Along with this change the sole host-PCI bridge driver converted to
actually make use of PCI domain support is uninorth(4), the others
continue to use domain 0 only for now and need to be converted as
appropriate later on.
Note that this means that the format of the location strings as used
by pciconf(8) has been changed and that consumers of <sys/pciio.h>
potentially need to be recompiled.

Suggested by:	jhb
Reviewed by:	grehan, jhb, marcel
Approved by:	re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
Marcel Moolenaar
7f67bed625 In pci_alloc_map(), restore the original value of the BAR for
the duration of the function.  The device we would otherwise
have left in an useless state may just as well be the low-level
console. When booting verbose, we do need it addressable if we
want to avoid a MCA.

Approved by: re (kensmith)
2007-07-29 02:44:41 +00:00
John Baldwin
81c8102c4c Don't completely skip pci_cfg_save() in the PCI nomatch routine if
the power_nodriver tunable is off.  pci_cfg_save() already checks the
tunable internally, and no other callers of pci_cfg_save() check the
tunable.

Reviewed by:	imp
2007-05-16 23:42:04 +00:00
John Baldwin
f11825148f Fix a typo in a bootverbose printf.
MFC after:	3 days
Submitted by:	yongari
2007-05-07 18:29:37 +00:00
John Baldwin
e706f7f0c7 Revamp the MSI/MSI-X code a bit to achieve two main goals:
- Simplify the amount of work that has be done for each architecture by
  pushing more of the truly MI code down into the PCI bus driver.
- Don't bind MSI-X indicies to IRQs so that we can allow a driver to map
  multiple MSI-X messages into a single IRQ when handling a message
  shortage.

The changes include:
- Add a new pcib_if method: PCIB_MAP_MSI() which is called by the PCI bus
  to calculate the address and data values for a given MSI/MSI-X IRQ.
  The x86 nexus drivers map this into a call to a new 'msi_map()' function
  in msi.c that does the mapping.
- Retire the pcib_if method PCIB_REMAP_MSIX() and remove the 'index'
  parameter from PCIB_ALLOC_MSIX().  MD code no longer has any knowledge
  of the MSI-X index for a given MSI-X IRQ.
- The PCI bus driver now stores more MSI-X state in a child's ivars.
  Specifically, it now stores an array of IRQs (called "message vectors" in
  the code) that have associated address and data values, and a small
  virtual version of the MSI-X table that specifies the message vector
  that a given MSI-X table entry uses.  Sparse mappings are permitted in
  the virtual table.
- The PCI bus driver now configures the MSI and MSI-X address/data
  registers directly via custom bus_setup_intr() and bus_teardown_intr()
  methods.  pci_setup_intr() invokes PCIB_MAP_MSI() to determine the
  address and data values for a given message as needed.  The MD code
  no longer has to call back down into the PCI bus code to set these
  values from the nexus' bus_setup_intr() handler.
- The PCI bus code provides a callout (pci_remap_msi_irq()) that the MD
  code can call to force the PCI bus to re-invoke PCIB_MAP_MSI() to get
  new values of the address and data fields for a given IRQ.  The x86
  MSI code uses this when an MSI IRQ is moved to a different CPU, requiring
  a new value of the 'address' field.
- The x86 MSI psuedo-driver loses a lot of code, and in fact the separate
  MSI/MSI-X pseudo-PICs are collapsed down into a single MSI PIC driver
  since the only remaining diff between the two is a substring in a
  bootverbose printf.
- The PCI bus driver will now restore MSI-X state (including programming
  entries in the MSI-X table) on device resume.
- The interface for pci_remap_msix() has changed.  Instead of accepting
  indices for the allocated vectors, it accepts a mini-virtual table
  (with a new length parameter).  This table is an array of u_ints, where
  each value specifies which allocated message vector to use for the
  corresponding MSI-X message.  A vector of 0 forces a message to not
  have an associated IRQ.  The device may choose to only use some of the
  IRQs assigned, in which case the unused IRQs must be at the "end" and
  will be released back to the system.  This allows a driver to use the
  same remap table for different shortage values.  For example, if a driver
  wants 4 messages, it can use the same remap table (which only uses the
  first two messages) for the cases when it only gets 2 or 3 messages and
  in the latter case the PCI bus will release the 3rd IRQ back to the
  system.

MFC after:	1 month
2007-05-02 17:50:36 +00:00
John Baldwin
361cf3bd02 Use more specific local variable pointers to narrow some expressions.
MFC after:	1 week
2007-05-02 16:21:18 +00:00
John Baldwin
d68b1825b7 - HT 2.00b added a new flag to the MSI mapping HT capability to indicate
that the MSI mapping window is fixed at 0xfee00000 and the capability
  does not include two more dwords used to program the address.  Supporting
  this mostly results in quieting spurious warnings during boot about
  non-default MSI mapping windows.
- HT 2.00b also added a new HT capability type, so support that in pciconf.

MFC after:	3 days
Tested by:	jmg
2007-04-25 14:45:46 +00:00
John Baldwin
4dc5078f81 Add constants for the fields in a BAR. Also, add two new macros
PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR
is for an IO or memory BAR, respectively.

Reviewed by:	imp
2007-03-31 21:39:02 +00:00
John Baldwin
657d9f9f55 - Add missing constants for subclasses.
- Add a few progif constants as well.
2007-03-31 20:41:00 +00:00
John Baldwin
b2bfac4c06 Change the VPD code to read the VPD data on-demand when a driver asks for
it via pci_get_vpd_*() rather than always reading it for each device during
boot.  I've left the tunable so that it can still be turned off if a device
driver causes a lockup via a query to a broken device, but devices whose
drivers do not use VPD (the vast majority) should no longer result in
lockups during boot, and most folks should not need to tweak the tunable
now.

Tested on:	bge(4)
Silence from:	jmg
2007-03-26 20:18:52 +00:00
John Baldwin
d8a4c26cde - Use constants for VPD capability register offsets.
- Add missing ()'s around return values.
2007-03-05 16:21:59 +00:00
Søren Schmidt
cfaed55fd5 Add support for chipsets that has NULL'd BAR's for legacy ports.
This allows DMA to be used on a fine little geode system I got here and
most like on lots of older systems like that.

HW donated by:  Paul Ghering
2007-02-17 16:56:39 +00:00
John Baldwin
f13fc7c893 Adjust the global MSI blacklisting strategy so we don't have to explicitly
blacklist a bunch of old chipsets.  If a system contains a PCI-PCI bridge
that supports PCI-X, assume the chipset supports PCI-X.  If a system
contains a PCI-express root port, assume the chipset supports PCI-express.
If the chipset doesn't support either PCI-X or PCI-express, then blacklist
it by default.  We should now only need to explicitly blacklist PCI-X or
PCI-express chipsets that don't properly handle MSI.
2007-02-14 22:36:27 +00:00
John Baldwin
ea3f508362 - Fix an off by one error in pci_remap_msix_method() that effectively
broke the method as all the MSI-X table indices were off by one in
  the backend MD code.
- Fix a cosmetic nit in the bootverbose printf in pci_alloc_msix_method().
2007-02-14 22:32:55 +00:00
John Baldwin
8474d26b81 Add missing 'break' that in this case is harmless. 2007-02-14 17:02:15 +00:00
Robert Watson
7222b40265 As VPD support still causes hard hangs on boot with some hardware, add a
tunable allowing automatic parsing of VPD data to be disabled.  The
default is left as-is; if you are having problems with hard hangs at boot
due to VPD, try setting hw.pci.enable_vpd=0.  A proper architectural
solution has been under discussion for some time, but this allows me to
boot my test machines in the mean time.

Submitted by:	bz
Head nod:	jmg
2007-02-08 14:33:07 +00:00
John Baldwin
5fe82bca57 Expand the MSI/MSI-X API to address some deficiencies in the MSI-X support.
- First off, device drivers really do need to know if they are allocating
  MSI or MSI-X messages.  MSI requires allocating powerof2() messages for
  example where MSI-X does not.  To address this, split out the MSI-X
  support from pci_msi_count() and pci_alloc_msi() into new driver-visible
  functions pci_msix_count() and pci_alloc_msix().  As a result,
  pci_msi_count() now just returns a count of the max supported MSI
  messages for the device, and pci_alloc_msi() only tries to allocate MSI
  messages.  To get a count of the max supported MSI-X messages, use
  pci_msix_count().  To allocate MSI-X messages, use pci_alloc_msix().
  pci_release_msi() still handles both MSI and MSI-X messages, however.
  As a result of this change, drivers using the existing API will only
  use MSI messages and will no longer try to use MSI-X messages.
- Because MSI-X allows for each message to have its own data and address
  values (and thus does not require all of the messages to have their
  MD vectors allocated as a group), some devices allow for "sparse" use
  of MSI-X message slots.  For example, if a device supports 8 messages
  but the OS is only able to allocate 2 messages, the device may make the
  best use of 2 IRQs if it enables the messages at slots 1 and 4 rather
  than default of using the first N slots (or indicies) at 1 and 2.  To
  support this, add a new pci_remap_msix() function that a driver may call
  after a successful pci_alloc_msix() (but before allocating any of the
  SYS_RES_IRQ resources) to allow the allocated IRQ resources to be
  assigned to different message indices.  For example, from the earlier
  example, after pci_alloc_msix() returned a value of 2, the driver would
  call pci_remap_msix() passing in array of integers { 1, 4 } as the
  new message indices to use.  The rid's for the SYS_RES_IRQ resources
  will always match the message indices.  Thus, after the call to
  pci_remap_msix() the driver would be able to access the first message
  in slot 1 at SYS_RES_IRQ rid 1, and the second message at slot 4 at
  SYS_RES_IRQ rid 4.  Note that the message slots/indices are 1-based
  rather than 0-based so that they will always correspond to the rid
  values (SYS_RES_IRQ rid 0 is reserved for the legacy INTx interrupt).
  To support this API, a new PCIB_REMAP_MSIX() method was added to the
  pcib interface to change the message index for a single IRQ.

Tested by:	scottl
2007-01-22 21:48:44 +00:00
John Baldwin
abc007f085 Disable MSI for the Intel 845 and 865 chipsets and update comment for
E7210 to note it is the same devid as the 875 chipset.
2007-01-16 19:44:45 +00:00
John Baldwin
8bbeb21223 Fix the subvendor ID for PCI-PCI bridges.
- Retire the PCI_SUB*_1 constants and don't try to read a subvendor ID out
  of them.  There isn't a standard subvendor ID field for PCI-PCI bridges.
  Instead, the dword at offset 0x34 is actually mostly reserved except for
  the LSB which is the capabilities pointer.
- Add support for the PCI-PCI bridge subvendor ID capability (13) and use
  it to set the subvendor ID for PCI-PCI bridges.

MFC after:	 1 month
2007-01-16 17:04:42 +00:00
John Baldwin
22bf1c7fb0 - Add a new flag to the PCI-PCI driver to disable MSI on devices behind the
bridge if it doesn't pass MSI messages up correctly.  We set the flag
  in pcib_attach() if the device ID is disabled via a PCI quirk.
- Disable MSI for devices behind the AMD 8131 HT-PCIX bridge.  Linux has
  the same quirk.

Tested by:	no one despite repeated calls for testers
2007-01-13 04:57:37 +00:00
John Baldwin
77312b5673 Disable MSI for two ServerWorks chipsets. The first is based on a user
report.  The second is blacklisted in Linux.
2007-01-12 21:37:51 +00:00
John Baldwin
854923ae86 Blacklist a few more Intel chipsets re: MSI based on user reports:
E7500 and 855.
2007-01-12 21:30:25 +00:00
John Baldwin
af07bd5661 - Condense the comment for Intel chipset MSI blacklist entries.
- Blacklist the E7210.

PR:		kern/105768 (2)
Reported by:	marcus (2)
2007-01-12 13:33:56 +00:00
John Baldwin
9d1f363daf Disable MSI on the Intel E7505 chipset. It is reported broken on a Tyan
S2665ANF motherboard.

Reported by:	"Eugene M. Kim" <blue at white lv>
2006-12-28 06:14:42 +00:00
John Baldwin
cc4f30e1a5 Disable MSI for the Intel E7501 chipset.
Reported by:	jdp
2006-12-14 19:59:29 +00:00
John Baldwin
e31182d9ca Add a first pass at a way to blacklist MSI on systems where it doesn't
work:
- A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table.
- A new pci_msi_device_blacklisted() determines if a passed in device
  matches an MSI quirk in the quirk table.  This can be overridden (all
  quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0.
- A global blacklist check is performed in the MI PCI bus code by checking
  to see if the device at 0:0:0 is blacklisted.

Tested by:	jdp
2006-12-14 19:57:06 +00:00
John Baldwin
2bbf9462ad Replace #define<space> with #define<tab> so the code is consistent with
style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
John Baldwin
3dcca30330 - Add constants for HT PCI capability registers including the various
subtypes of HT capabilities.
- Add constants for the MSI mapping window HT PCI capability.
- On i386 and amd64, enable the MSI mapping window on any HT bridges we
  encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
John Baldwin
0003a3f074 Give the WREG() macro the same lifetime as the REG() macro. 2006-12-12 19:30:40 +00:00
John Baldwin
310756939c Add some bootverbose printf's to detail how many MSI messages are allocated
and to which IRQs.

Requested by:	scottl
2006-12-12 19:29:01 +00:00
John-Mark Gurney
b318e84967 don't mark the cksum as invalid here... off is incorrect when we get
here, it's either unset, or it's valid, so we don't need to do anything
different...

Reported by:	Neterion (via rwatson)
2006-11-21 05:46:09 +00:00
John Baldwin
3bea4efeb1 Look for capabilities in PCI-PCI bridges using the same CAP PTR register
as for type 0 devices.

Submitted by:	grehan
MFC after:	1 week
2006-11-16 17:31:33 +00:00
John Baldwin
9bf4c9c1b0 First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
  to provide the device driver visible API:
  - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI().  '*count'
    here is an in and out parameter.  The driver stores the desired number
    of messages in '*count' before calling the function.  On success,
    '*count' holds the number of messages allocated to the device.  Also on
    success, the driver can access the messages as SYS_RES_IRQ resources
    starting at rid 1.  Note that the legacy INTx interrupt resource will
    not be available when using MSI.  Note that this function will allocate
    either MSI or MSI-X messages depending on the devices capabilities and
    the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  Also note
    that the driver should activate the memory resource that holds the
    MSI-X table and pending bit array (PBA) before calling this function
    if the device supports MSI-X.
  - pci_release_msi(dev) backed by PCI_RELEASE_MSI().  This function
    releases the messages allocated for this device.  All of the
    SYS_RES_IRQ resources need to be released for this function to succeed.
  - pci_msi_count(dev) backed by PCI_MSI_COUNT().  This function returns
    the maximum number of MSI or MSI-X messages supported by this device.
    MSI-X is preferred if present, but this function will honor the
    'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  This function
    should return the largest value that pci_alloc_msi() can return
    (assuming the MD code is able to allocate sufficient backing resources
    for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
  PCI bus driver.  (The various other PCI bus drivers such as for ACPI and
  OFW will inherit these default implementations.)  This default
  implementation depends on 4 new pcib_if methods that bubble up through
  the PCI bridges to the MD code to allocate IRQ values and perform any
  needed MD setup code needed:
  - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
  - PCIB_RELEASE_MSI() releases a group of MSI messages.
  - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
  - PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
  request up to the parent bus's parent bridge driver and use the
  default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
  interrupts:
  - pci_enable_msi(dev, address, data) programs the MSI capability address
    and data registers for a group of MSI messages
  - pci_enable_msix(dev, index, address, data) initializes a single MSI-X
    message in the MSI-X table
  - pci_mask_msix(dev, index) masks a single MSI-X message
  - pci_unmask_msix(dev, index) unmasks a single MSI-X message
  - pci_pending_msix(dev, index) returns true if the specified MSI-X
    message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
  block in a PCI devices ivars and restore the values when a device is
  resumed.  Note that the MSI-X table is not currently restored during
  resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
  across in the pci_cfgreg block in the ivars for PCI devices.

Tested on:	em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by:	scottl, grehan, jfv
MFC after:	2 months
2006-11-13 21:47:30 +00:00
John-Mark Gurney
ee03a332df fix hanging on invalid data... (This doesn't fix hanging due to broken
hardware)...

Tested by:	Ian Dowse, Adam K Kirchhoff and Vladimir Kushnir
2006-11-09 21:05:32 +00:00
John Baldwin
d65926888d Various whitespace cleanups. 2006-11-07 18:55:51 +00:00
Warner Losh
8e6c8e8c0c Doh! Actually commit checking against NULL for res.
Noticed by: dougb@
2006-11-04 06:56:51 +00:00
Warner Losh
a12fb4e632 Assign start to the value we were able to allocate and use that to
write out the BAR.  Otherwise, we were trying to shift a 32-bit
quantity on 32-bit platforms.  Also, 'start' check sanity to where it
is known.
2006-10-30 22:46:33 +00:00
Warner Losh
b0a2d4b8a9 More fully support 64-bit bars. Prior to this commit, we supported
only those bars that had addresses assigned by the BIOS and where the
bridges were properly programmed.  Now even unprogrammed ones work.
This was needed for sun4v.  We still only implement up to 2GB memory
ranges, even for 64-bit bars.  PCI standards at least through 2.2 say
that this is the max (or 1GB is, I only know it is < 32bits).

o Always define pci_addr_t as uint64_t.  A pci address is always 64-bits,
  but some hosts can't address all of them.
o Preserve the upper half of the 64-bit word during resource probing.
o Test to make sure that 64-bit values can fit in a u_long (true on some
  platforms, but not others).  Don't use those that can't.
o minor pedantry about data sizes.
o Better bridge resource reporting in bootverbose case.
o Minor formatting changes to cope with different data types on different
  platforms.

Submitted by: jmg, with many changes by me to fully support 64-bit
addresses.
2006-10-30 19:18:46 +00:00
John-Mark Gurney
8946c28270 fix tab indentation for CP and RV...
If the length is zero, catch this early, instead of making dflen go negative
and letting bad things happen...  We also check to see if RV (checksum) is
0, and handle that has a checksum failure...

Properly handle checksum failures by not processing read-write VPD data,
and removing all the found read-only data...

Tested by:	oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
John-Mark Gurney
667dc26e71 provide routines to access VPD data at the PCI layer...
remove sk's own implementation, and use the new calls to get the data...

Reviewed by:	-arch
2006-10-09 16:15:56 +00:00
John-Mark Gurney
b70c1daf97 spell PCIS_CRYPTO_ENTERTAIN properly...
MFC after:	3 days
2006-09-20 06:47:14 +00:00
John Baldwin
19e9205a23 Simplify the pager support in DDB. Allowing different db commands to
install custom pager functions didn't actually happen in practice (they
all just used the simple pager and passed in a local quit pointer).  So,
just hardcode the simple pager as the only pager and make it set a global
db_pager_quit flag that db commands can check when the user hits 'q' (or a
suitable variant) at the pager prompt.  Also, now that it's easy to do so,
enable paging by default for all ddb commands.  Any command that wishes to
honor the quit flag can do so by checking db_pager_quit.  Note that the
pager can also be effectively disabled by setting $lines to 0.

Other fixes:
- 'show idt' on i386 and pc98 now actually checks the quit flag and
  terminates early.
- 'show intr' now actually checks the quit flag and terminates early.
2006-07-12 21:22:44 +00:00
John Baldwin
70bc2d3f4f Fixup some comments to allow for the fact that PCI domains are not specific
to Alpha hoses.
2006-05-11 22:13:21 +00:00
Marcel Moolenaar
d95bd0c34a The size of I/O ranges can be anything from 16 bytes to 2G bytes.
Lower the minimum for memory mapped I/O from 32 bytes to 16 bytes.
This fixes bus enumeration on ia64 now that the Diva auxiliary
serial port is attached to.
2006-04-27 04:53:18 +00:00
John Baldwin
5aa58b3e8f Make the 'pci_devclass' pointer variable private (drivers really shouldn't
share devclass pointers, a mistake I've encouraged in the past) and
move the declaration of the pci_driver kobj class from cardbus.c to
pci_private.h so that other drivers can inherit from pci_driver.
2006-01-20 22:00:50 +00:00
Warner Losh
a48895a77e Use __HAVE_ACPI and __PCI_REROUTE_INTERRUPT as appropriate rather than
the complicated #ifdefs.
2006-01-01 21:04:31 +00:00
Warner Losh
98b7810732 Remove stray debug from p4 integration. 2006-01-01 08:26:39 +00:00
Warner Losh
0c4246bd98 Remove debug now that I've looped back the big changes into my p4 tree. 2005-12-30 19:36:29 +00:00
Warner Losh
a9883bc8c4 Expose pci_add_resources to the outside world, add a 'force' flag to
force allocation of unallocated BARs (cardbus uses this to preallocate
everything).  Add a prefetchmask to allow for busses that get prefetch
hints to set them.  Addjust pci_add_map and pci_ata_maps to take a new
force flag which pci_add_resources will pass in.  Implement 'force' in
pci_add_map.  Write new value of allocated resource into the bar, if
the allocation succeeded (we should have done this before, but with
the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
John Baldwin
4f9795b9fe Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used
to search for a specific extended capability.  If the specified capability
is found for the given device, then the function returns success and
optionally returns the offset of that capability.  If the capability is
not found, the function returns an error.
2005-12-20 19:57:47 +00:00
Warner Losh
24ea970aff Improve diagnostic message. 2005-11-09 03:37:52 +00:00
Warner Losh
e5baeed6a6 MFp4: When doing lazy allocation, it turns out that we need to record the
actual resource values we received from the system rather than the range
we requested.  Since we request a range starting at 0, we would record
that number.  Later, since this == 0, we'd allocate again.  However,
we wouldn't write the new resource into the BAR.  This resulted in
a resource leak as well as a BAR that couldn't access the resource at
all since rman_get_start, et al, were wrong.

MFC After: 1 week (assuming RELENG_6 is open for business)
2005-10-29 05:52:17 +00:00
Warner Losh
87623e8dd6 Use symbolic name rather thanhard coding the cap pointer offset for
type two devices.
2005-10-29 05:49:06 +00:00
Warner Losh
46dfab17fb Minor style(9) nitage. 2005-10-28 05:56:50 +00:00
Bill Paul
85155d23de Add a 1 microsecond delay in pci_add_children(), right before the read
of the PCIR_HDRTYPE register. It's the value returned from this
read access that determines whether or not we decide a device is
present at the current slot index. For some reason that I can't
adequately explain, this read fails on my machine when probing the
USB controller on my machine (which happens a multifunction device
at slot index 3 hung off the PCI-PCI bridge on the AMD8111 (bus
index 1)). The read will return 0xFF even though it should return
0x80 to indicate the presence of a multifunction device.

As near as I can tell, there's some timing issue involved with reading
the 'dead' slot indexes 0 through 2 that causes the read of the actual
device at slot 3 to fail. I tried a couple of different tricks to
correct the problem (the patch to amd64/pci/pci_cfgreg.c fixes it
for the amd64 arch), but adding this delay is the only thing that
always allows the USB controllers to be correctly probed 100% of the
time. Whatever the problem is, it's likely confined to the AMD8111
chipset. However, a simple 1us delay is fairly harmless and should
have no side effects for other hardware. I consider this to be
voodoo, but it's fairly benign voodoo and it makes my USB keyboard
and mouse work again.

Note that this is the second time that I've had to resort to a
1us delay to fix a PCI-related problem with this AMD8111/Opteron
system (the first being a fix I made a while back to the NDISulator).
It's possible the delay really belongs in the cfgreg code itself,
or that pci_cfgreg needs some custom hackery for an errata in the
8111. (I checked but couldn't find any documented errata on AMD's
site that could account for these problems.)
2005-10-25 06:53:45 +00:00
John Baldwin
85266973b6 - Consolidate duplicated code for assigning interrupts to PCI devices via
routing, etc. in a static pci_assign_interrupt() function.
- Add a sledgehammer that allows the user to override the interrupt
  assignment of any PCI device via a tunable (e.g. "hw.pci0.7.INTB=5" would
  force any functions on the pci device in slot 7 of bus 0 that use B# to
  use IRQ 5).  This should be used with great caution!  Generally, if the
  interrupt routing in use provides specific tunables (such as hard-wiring
  the IRQ for a given $PIR or ACPI PCI link device), then those should be
  used instead.  One instance where this tunable might be useful is if a
  box has an MPTable with duplicate entries for the same PCI device with
  different IRQs.

MFC after:	1 week
2005-09-29 15:04:41 +00:00
Warner Losh
50757d2fce Split power state control into two variables. hw.pci.do_powerstate
has been removed.  It has been replaced by hw.pci.do_power_nodriver
and hw.pci.do_power_resume.  The former defaults to 0 while the latter
defaults to 1.

When do_powerstate was set to 0, it broke suspend/resume for a lot of
people as an unintended consequence.  This change will only affect the
areas that were intended to affect.  This change will have no effect on
servers, but will help laptops quite a bit.

MFC After: 3 days.
2005-09-21 19:47:00 +00:00
Warner Losh
6c996a0055 Change hw.pci.do_powerstate from a boolean to a range. 0 means the
same as today: do no power management.  1 means be conservative about
what you power down (any device class that has caused problems gets
added here).  2 means be agressive about what gets powered down (any
device class that's fundamental to the system is here).  3 means power
them all down, reguardless.  The default is 1.

The effect in the default system is to add mass storage devices to the
list that we don't power down.  From all the pciconf -l lists that
I've seen for the aac and amr issue, the bad device has been a mass
storage device class.

This is an attempt at a compromise between the very small number of
systems that have extreme issues with powerdown, and the very large
number of systems that gain real benefits from powerdown (I get about
20% more battery life when I attach a minimal set of drivers on my
Sony).  Hopefully it will strike the proper balance.

MFC After: 3 days (before next beta)
2005-09-11 04:09:44 +00:00
Warner Losh
6de560ab92 Allow one to access the cached values for CMDREG, CACHELNSZ, MINGNT,
MAXLAT and LATTIMER.

Improve error message when a bogus RID type is requested for a bar.
2005-09-11 03:22:03 +00:00
Warner Losh
a8cbc96cd8 More consistantly return the correct BAR size. Before, we'd only
return the correct bar size if we encountered a 64-bit BAR that had
its resources already assigned.  If the resources weren't yet
assigned, we'd bogusly assume it was a 32-bit bar and return 1.
2005-09-03 23:15:46 +00:00
John Baldwin
9a1bbc523c Typo in comment. 2005-09-01 16:41:42 +00:00
Warner Losh
b81b5c06b4 Treat resources that are 0xfffff.... as being 'unassigned'.
Reviewed by: jhb
Tested by: Mark Kirkwood
MFC After: 3 days
2005-09-01 02:42:34 +00:00
Warner Losh
f9937ed8f3 Mask off the bar's value after the probe test write before testing
against 0 in pci_alloc_map, just like we do in pci_add_map.  Also,
make sure that we restore the value to the BAR that was there before
if the bar is 0.  Chances are that it was 0 before the write too and
that the restoration is a nop, but better safe than sorry.

Notice by: dwhite
2005-06-03 19:41:06 +00:00
John Baldwin
f1e1aa9ba2 Typo.
Submitted by:	njl
2005-06-01 14:07:43 +00:00
John Baldwin
4081108643 Don't enable I/O or memory mode in a device's command register if the BAR
we are processing has a base address of zero.  Note that this will only
change behavior for devices where all the BARs of a given type have a base
address of 0 since we will enable the appropriate access when we encounter
the first BAR with a base that is not 0.  Specifically, this allows certain
Toshiba laptops to no longer require 'hw.pci.enable_io_modes=0' to avoid
hangs during boot.

PR:		kern/20040
PR:		i386/63776 (possibly)
PR:		i386/68900 (possibly)
PR:		i386/74532 (possibly)
MFC after:	1 week
2005-05-31 21:33:33 +00:00
Warner Losh
4e30440d7c Add a detach for pci bridge and pci bus drivers. This allows one to
theoretically unload pci bridges or pci drivers.  It will also allow
detach to work if one needed to detach a subtree.

This is inspired by looking at the p4 commits from bms to his 5.4
tree, but I didn't look at the final results.
2005-04-29 06:22:41 +00:00
John Baldwin
9e605855ab Call pci_print_verbose() before pci_add_resources() so that the order of
printf's during a verbose boot is more intuitive (the BAR listings and
interrupt routing info now comes after the config header dump rather than
just before it).
2005-04-14 17:52:55 +00:00
Warner Losh
ca44abece9 It isn't a whinable offence to want memory when the bar says ioport.
Put that behind bootverbose to make the ata driver less chatty on
advanced hardware.

Requested by: sos
2005-04-11 02:08:05 +00:00
Warner Losh
69c5c40b2d Go ahead and try to allocate PCI_BAR(5) for ata devices. 2005-04-10 23:49:04 +00:00
John-Mark Gurney
5da5a253a5 move the statement about switching power states to just before we do it, so
we don't print a false statement if the destination powerstate is
unsupported...
2005-04-01 16:22:50 +00:00
John-Mark Gurney
4ea3b0e7e2 add some additional pci classes and sub-classes..
Reviewed by:	imp (almost 6 months ago)
2005-03-26 20:31:09 +00:00
John-Mark Gurney
244f64d007 relocate the power state transition statements to the
pci_set_powerstate_method function...

Reviewed by:	imp
MFC after:	1 week
2005-03-23 21:24:29 +00:00
Warner Losh
36fed96550 Use STAILQ in preference to SLIST for the resources. Insert new resources
last in the list rather than first.

This makes the resouces print in the 4.x order rather than the 5.x order
(eg fdc0 at 0x3f0-0x3f5,0x3f7 is 4.x, but 0x3f7,0x3f0-0x3f5 is 5.x).  This
also means that the pci code will once again print the resources in BAR
ascending order.
2005-03-18 05:19:50 +00:00
Warner Losh
463ec0ac87 If bus_generic_susped returns an error, devlist is not freed. Free it.
Submitted by: Ted Unangst (using the Coverity Prevent analysis tool)
2005-03-15 22:53:31 +00:00
Warner Losh
c3c08f307c Expose pci_cfg_safe/restore for subclasses of pci to use. 2005-02-28 01:14:15 +00:00
Sam Leffler
aedaf6e272 kill unused variable
Noticed by:	Coverity Prevent analysis tool
2005-02-25 23:15:48 +00:00
Bernd Walter
b542a023e5 Enable interrupt routing as first choice on alpha.
The alpha default handler knows how to trigger a fallback.
2005-02-07 00:43:14 +00:00
Nate Lawson
73c58ad19d Fix typo. 2005-01-29 19:45:31 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Warner Losh
0290609953 Fix last second typos that crept in :-(. 2004-12-31 23:59:24 +00:00
Warner Losh
4ee5d2f181 Implement mimimum system software delays, per PCI PM 1.1 spec, as
suggested by Peter Edwards.  This seems to fix my fxp problems and
likely will fix his as well.  Use DELAY rather than *sleep because we
can be called from any context.
2004-12-31 20:43:46 +00:00
Warner Losh
e50dccaec1 Fix comments to match last commit, and minor reformatting... 2004-12-08 04:35:19 +00:00
Warner Losh
6f2156545c It turns out that a lot of newer systems have 'base peripherals' on
the PCI bus.  We presently have no drivers for these devices, so they
are powered down.  This is undesirable behavior since it breaks the
system when the base peripherals go away suddenly in the middle of
boot.

# if we ever get generic drivers for memory and/or base peripherals, then
# we can remove the tests here.
2004-12-08 04:16:18 +00:00
Nate Lawson
8526ed739d ACPI is not on pc98 either.
Informed by:	nyan
2004-12-03 08:44:56 +00:00
Nate Lawson
161ad64e63 Non-x86 platforms cannot use the ACPI includes. This should be fixed but
for now, only include the headers for i386, amd64, or ia64.

Pointed out by:	grehan
2004-12-03 08:13:08 +00:00
Nate Lawson
10ce62b975 Turn ACPI and PCI devices off or to a lower power state in suspend and
back on again in resume.  Override the default of D3 with the value the
BIOS specifies in _SxD, if present.  Skip serial devices (PNP05xx) since
they seem to hang when set to D3 and may require special driver support.
Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet
save/restore their config space and that seems to be necessary.

If this gives you trouble with suspend/resume, you can disable the new
ACPI and PCI power behavior separately with these tunables & sysctls:
    debug.acpi.do_powerstate
    hw.pci.do_powerstate

Approved by:	imp (pci)
Tested by:	acpi@ (numerous)
2004-12-02 08:07:12 +00:00
Warner Losh
4ae6f4a64e Make pci_do_powerstate default to 1 now that we've done the release to
get more testing.  This should help things a little.
2004-11-10 00:41:39 +00:00
John Baldwin
d39d4a6e64 - Change the ddb paging "support" to use a variable (db_lines_per_page) to
control the number of lines per page rather than a constant.  The variable
  can be examined and changed in ddb as '$lines'.  Setting the variable to
  0 will effectively turn off paging.
- Change db_putchar() to force out pending whitespace before outputting
  newlines and carriage returns so that one can rub out content on the
  current line via '\r     \r' type strings.
- Change the simple pager to rub out the --More-- prompt explicitly when
  the routine exits.
- Add some aliases to the simple pager to make it more compatible with
  more(1): 'e' and 'j' do a single line.  'd' does half a page, and
  'f' does a full page.

MFC after:	1 month
Inspired by:	kris
2004-11-01 22:15:15 +00:00
Brian Feldman
9b4fab9ef6 Fix a spelling error in a panic string. 2004-10-14 03:05:39 +00:00
Olivier Houchard
b19d97eb9c Re-route interrupts on arm as well. 2004-09-23 22:58:43 +00:00
Warner Losh
828a0b7110 Disable native ata support for now, too much breaks 2004-07-02 13:42:36 +00:00
Søren Schmidt
d485c7bcf3 Update the special handling code for ATA devices to allow usage of
PCI native addressing. That means that if the HW says that using "real"
addresses instead of the hardwired legacy compat ones is allowed, we will
use them.
2004-06-29 20:25:43 +00:00
Poul-Henning Kamp
89c9c53da0 Do the dreaded s/dev_t/struct cdev */
Bump __FreeBSD_version accordingly.
2004-06-16 09:47:26 +00:00
Warner Losh
ef77fe1a5b Use PCI_BAR() in preference to PCI_MAPS + x * 4.
Submitted by: jhb
2004-05-24 17:41:05 +00:00
Warner Losh
7138b71d5f Do not write to those config registers that are unambiguously defined
in the various pci specifications as readonly.  vendor, subvendor,
device and subdevice are required to be loaded in hardware by some
means that isn't the system BIOS or other system software (although
some devices do have ways of accomplishing this).  class and subclass
are defined to be read-only in section 6.2.1 (v2.2).  Apart from the
status register, which we weren't touching, these are the only
read-only registers I could find in the 2.2 spec.

progif is also defined as being read-only in section 6.2.1.  However,
the PCI IDE programming document specifically states that some of the
bits are read/write.  Since we may have to restore registers before we
have a driver attached, go ahead and restore this one byte when
transitioning between D3 and D0.

The PCI spec also says that writes to reserved and unimplemented
registers must be completed normally.  It makes no statements about
writes to read-only registers, so be as conservative as possible,
while covering the exception to the rule that is documented in a
subpart of the standard.

Requested by: socttl
2004-05-24 15:52:57 +00:00
Warner Losh
c5b82061f4 Fix cutNpasto in last commit. 2004-05-21 19:47:55 +00:00
Warner Losh
d776e1167f ifdef writing to registers that the base pci standard says are
read-only on D3->D0 power state transition.  Add a define to enable
them, but include a comment to contact me if there's a problem.
2004-05-21 14:41:02 +00:00
Warner Losh
17249aab6e Compeletely rewrite the description of hw.pci.do_powerstate to sound
better.
2004-05-21 07:06:54 +00:00
Warner Losh
4c04937d5b Improve the English somewhat.
Prodded by: ru@
2004-05-21 07:03:07 +00:00
Warner Losh
cd677980a1 Ooops, forgot to commit the updated definition for hw.pci.do_powerstate
when I committed code that changed its meaning.
2004-05-21 06:43:46 +00:00
Warner Losh
b17653cf41 MFp4:
Split the baby.  For idepci devices, now both legacy mode bits need
not be set.  We can run an idepci in a split mode.  However, it only
works better than before, not works.  It works better in that when one
device is legacy and the other isn't and disabled, we now operate
correctly.

sos submitted a version of this patch.
2004-05-21 06:41:15 +00:00
Warner Losh
ae8b157fbf Move pci_do_powerstate up a level. Now it just means 'do not turn devices
off into d3 state when there's no driver for the device'.  This should
help suspend/resume in the default case.
2004-05-21 06:39:09 +00:00
Warner Losh
e5af1ba884 MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass,
subclass, progif and revid.  While these are typically read
	only fields, they aren't always read-only.  progif is writable
	for ata devices, for example.  It does no harm when they are
	read only, and helps when they aren't.
2004-05-21 06:36:36 +00:00
Warner Losh
d53b25544c make the pci power state and resource code a lot less chatty. The
chattiness was left in for debugging, but now that nearly all of the
problems relating to the changes have been fixed, it is only annoying.  It
is still available via bootverbose.

Prodded by: jhb
2004-05-21 06:03:26 +00:00
Thomas Moestl
fe2c61013d Remove the EBus stopgap of r1.248; a proper fix is in place now. 2004-04-28 13:43:11 +00:00
Warner Losh
1c168bb710 Fix two typos from PR: 65694
1) In pci.c, we need to check the child device's state, not the parent
   device's state.
2) In acpi_pci.c, we have to run the power state change after the acpi
   method when the old_state is > new state, not the other way around.

Submitted by: Dmitry Remesov
PR: 65694
2004-04-26 02:11:38 +00:00
Marius Strobl
27c2013edf Add a stopgap for the EBus breakage on sparc64 since the PCI code does
resource pre-allocation. The problem is that the BARs of the EBus bridges
contain the ranges for the resources for the EBus devices beyond the bridge.
So when the EBus code tries to allocate the resource for an EBus device
it's already allocated by the PCI code.
To be removed again as soon as we have a proper solution in the EBus Code.

Reviewed by:	tmm
Approved by:	marcel (mentor)
2004-04-23 15:48:48 +00:00
Warner Losh
206995a116 ata devices in legacy are special, and we must treat them as such.
While I would have prefered to have a solution that didn't move
knowledge of this into the pci layer.  However, this is literally the
only exception that's listed in the PCI standard to the usual way of
decoding BARs.  atapci devices in legacy mode now ignore the first 4
bars and hard code the values to the legacy ide values (well, for each
of the controllers that are in legacy mode).  The 5th bar is handled
normally.

Remove the zero bar handling.  zero bars should be ignored at all
other times, and since we handle that specially, we don't need the
older workaround.
2004-04-21 20:19:56 +00:00
Søren Schmidt
470fcc93b9 Do not pre-allocate resources for BAR's on ATA MASTERDEV's thats on
the standard ATA primary and secondary addresses.

Reintroduce the size 1 ALTIO space so that we can have both ATA and
floppies back working.
2004-04-20 20:57:29 +00:00
Warner Losh
f77ad99d59 ooops. I disabled pci_enable_io_modes not pci_do_powerstate in the last
commit.  That was in error.

Noticed by: sos
2004-04-16 15:01:54 +00:00
Warner Losh
b24afb1761 make the bad bar warning less scary, and toss it behind a bootverbose.
It is harmless, but freaking people out.
2004-04-16 04:53:19 +00:00
Warner Losh
d966428737 Turn off the power stuff for a little while longer. There appears to be
something subtle wrong with it.
2004-04-16 04:50:54 +00:00
Warner Losh
b0855e456e Now that the dust has settled on the resource issues, turn on the
power parts of my patches and see what breaks.  Don't (yet) throw
the chatty messages behind a if (bootverbose).
2004-04-14 17:52:08 +00:00
Warner Losh
d9f6718ee3 Some devices have what appear to be invalid BARs. They are invalid in
the sense that any write to them reads back as a 0.  This presents a
problem to our resource allocation scheme.  If we encounter such vars,
the code now treats them as special, allowing any allocation against
them to succeed.  I've not seen anything in the standard to clearify
what host software should do when it encounters these sorts of BARs.

Also cleaned up some output while I'm here and add commmented out
bootverbose lines until I'm ready to reduce the verbosity of boot
messages.

This gets a number of south bridges and ata controllers made mostly by
VIA, AMD and nVidia working again.  Thanks to Soren Schmidt for his
help in coming up with this patch.
2004-04-13 19:31:57 +00:00
Warner Losh
e3d5128493 Add system tunable to turn off power state changes. Default to off until
we get the resource allocation stuff hammered out.

Fix and off by one error that caused unnecessary filtering of valid
BARs for only 4 bytes than ICH3 and other PCI IDE controllers have.
Andrew Gallatin submitted this, although it doesn't solve the problems
ICH3 controllers have with the new code, it does restore the former
resource list on the probe line.
2004-04-11 07:02:49 +00:00
Warner Losh
bbecd97c0b Only print state change message for real state changes. When we set a
device in D0 to D0, that's a no-op, however the messages seem to be
confusing some people.  Eventually, these messages will be parked
behind a if (bootverbose).

# I don't think this will fix any real bugs...
2004-04-09 20:41:18 +00:00
Warner Losh
cd8b53ed2d Omnibus PCI commit:
o Save and restore bars for suspend/resume as well as for D3->D0
	  transitions.
	o preallocate resources that the PCI devices use to avoid resource
	  conflicts
	o lazy allocation of resources not allocated by the BIOS.
	o set unattached drivers to state D3.  Set power state to D0
	  before probe/attach.  Right now there's two special cases
	  for this (display and memory devices) that need work in other
	  areas of the tree.

Please report any bugs to me.
2004-04-09 15:44:34 +00:00
Warner Losh
f54a290f54 Minor whitespace changes to conform better to stlye(9) and reduce diffs
with uncommitted changes I have in p4.
2003-12-24 02:01:22 +00:00
Peter Wemm
0d2a298904 Initial landing of SMP support for FreeBSD/amd64.
- This is heavily derived from John Baldwin's apic/pci cleanup on i386.
- I have completely rewritten or drastically cleaned up some other parts.
  (in particular, bootstrap)
- This is still a WIP.  It seems that there are some highly bogus bioses
  on nVidia nForce3-150 boards.  I can't stress how broken these boards
  are.  I have a workaround in mind, but right now the Asus SK8N is broken.
  The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed.
- Most of my testing has been with SCHED_ULE.  SCHED_4BSD works.
- the apic and acpi components are 'standard'.
- If you have an nVidia nForce3-150 board, you are stuck with 'device
  atpic' in addition, because they somehow managed to forget to connect the
  8254 timer to the apic, even though its in the same silicon!  ARGH!
  This directly violates the ACPI spec.
2003-11-17 08:58:16 +00:00
John Baldwin
4311d1d368 Enable PCI interrupt routing for i386 SMP kernels. 2003-11-03 22:06:35 +00:00
Doug Rabson
aec21b56e8 Make the cardbus driver a derived class of the pci driver. In theory, this
should allow many of the pci methods to be re-staticised.
2003-11-01 12:45:03 +00:00
Mitsuru IWASAKI
526b5e659d Add pci_resume() to reestablish interrupt routing after
suspend/resume.
Especially after hibernation, interrupt routing went back to initial
status on some machines.
2003-09-17 08:32:44 +00:00
Scott Long
ec40a9f9d0 Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
Scott Long
cadbc399ea Remove most of the magic constants from the extcap parsing code. 2003-09-14 06:23:19 +00:00
John Baldwin
ab551d918c Replace another instance of PCIR_MAPS with PCIR_BAR(x).
Reminded by:	dfr
2003-09-03 15:24:31 +00:00
John Baldwin
e27951b29c Use PCIR_BAR(x) instead of PCIR_MAPS.
Glanced over by:	imp, gibbs
Tested by:		i386 LINT
2003-09-02 17:30:40 +00:00
Doug Rabson
d37a68d05a Don't try to enable io or memory access for non-standard resource
addresses. This stops resource allocations for e.g. amdpm failing - this
has its own special ways of enabling access.
2003-09-01 15:01:49 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
Warner Losh
b0cb115fb7 Prefer the uintXX_t to the u_intXX_t names. 2003-08-22 03:11:53 +00:00
Warner Losh
8d50cc0e3e Define PCI_MAXHDRTYPE to be 2. We know about header types 0, 1 and 2.
Update the MI device scanning code to use PCI_MAXHDRTYPE rather than
the hard coded 2.
2003-08-01 21:45:56 +00:00
John Baldwin
3f2a1b0656 Update the 'ps', 'show pci', and 'show ktr' ddb commands to use the new
pager callout instead of homerolling their own paging facility.
2003-07-31 17:29:42 +00:00
Thomas Moestl
3920999db7 Add a new PCI interface method, assign_interrupt, to determine the
interrupt to be used for a device. This is intended solely for internal
use of PCI bus implementations, and exists so that PCI bus drivers
implementing special interrupt assignment methods which require
additional work at the bus level to work right can be easily derived
from the generic driver (or any other one) without resorting to hacks.

It will be used in the sparc64 ofw_pcibus driver, which will be
committed shortly.

Make use of this method in the generic implementation, and add it to
the method table of bus drivers derived from the PCI one.

Reviewed by:	imp, -hackers
2003-07-01 14:08:33 +00:00
Thomas Moestl
036c2cfbfa Allow to write the intpin ivar using the pci_set_intpin() accessor. There
are some Sun PCI devices around which bogusly set intpin to 0, although
they use the intline mechanism; this allows the device driver to correct
that.

Reviewed by:	imp
2003-07-01 13:54:10 +00:00
Yoshihiro Takahashi
403579314a Re-enabled PCI irq routing on pc98. 2003-06-22 06:09:14 +00:00
John-Mark Gurney
e3ee6a27a9 use a REG macro that was already defined.
Reorder how the pci probing in handled.  before adding devices, check to
see if the slot is a multi-function device to see if we should probe all
the functions.

Original idea by:	imp
2003-06-22 02:26:17 +00:00
John Baldwin
bd77aaf980 When we re-route a PCI interrupt, write the new IRQ value into the intline
register.

Reviewed by:	imp
2003-06-09 18:08:46 +00:00
Yoshihiro Takahashi
82cdd526b1 Don't route PCI irq on pc98. 2003-06-08 11:18:35 +00:00
John Baldwin
1beb381637 - Adjust the comment about re-routing PCI interrupts to be less
ia64-specific.
- When trying to re-route interrupts, don't change cfg->intline if the
  re-route fails by returning an invalid vector.  This fixes machines
  without any way of routing interrupts such as older PC's without a
  $PIR table.

We do not currently write the new intline value back to the hardware, but
we should.  That will likely be added in a later commit.
2003-06-07 15:00:19 +00:00