The on-board NIC is an 3x3 AR9380 with 5GHz only.
* enable pci code in AR9344_BASE
* enable ath_pci and the firmware loading bits in DB120
* add in the relevant hints in DB120.hints to inform the probe/attach
code where the PCIe fixup data is for the onboard chip.
This is only relevant for a default development board. I also have a
DB120 with the on-board PCIe wifi NIC disabled and it's exposed as
a real PCIe slot (to put normal PCIe NICs in); the fixup code will need
to be disabled to make this work correctly.
Tested:
* DB120
DB120 development board.
The AR934x SoCs are a MIPS74k based system with increased RAM addressing
space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3
on-board dual-band wifi.
This support isn't complete by any stretch; it's just enough to bring
the board up for others to tinker with. Notably, the MIPS74k support
is broken. However it boots enough to echo some basic probe/attach
messages, before dying somewhere in the TLB code.
Thankyou to Qualcomm Atheros for their continued support of me doing
open source work with their hardware.
Tested:
* AR9344, mips74k
