Commit Graph

163 Commits

Author SHA1 Message Date
John Baldwin
2ab55f4392 Change the nexus_pcib driver (eventually to be renamed to legacy_pcib) to
hang off of the legacy driver instead of the nexus.
2002-09-23 15:52:30 +00:00
John Baldwin
fe4663379e Axe unused include. 2002-09-20 19:16:41 +00:00
John Baldwin
fefe985dc6 Make sure a $PIR table header has a valid length before accepting the table
as valid.

Submitted by:	Michal Mertl <mime@traveller.cz>
2002-09-09 18:24:35 +00:00
Poul-Henning Kamp
a0c422db00 #include "opt_bla.h" goes first says Bruce. 2002-09-09 08:44:52 +00:00
Poul-Henning Kamp
9339569236 Fix style(9) bugs.
Brucified by:	bde
2002-09-08 15:16:49 +00:00
John Baldwin
7bbb0b56e4 Add a subclass of the PCI-PCI bridge driver that uses the PCIBIOS to
route interrupts if the child bus is described in the PCIBIOS interrupt
routing table.  For child busses that are in the routing table, they do
not necessarily use a 'swizzle' on their pins on the parent bus to route
interrupts for child devices.  If the child bus is an embedded device then
the pins on the child devices can be (and usually are) directly connected
either to a PIC or to a Interrupt Router.  This fixes PCIBIOS interrupt
routing across PCI-PCI bridges for embedded devices.
2002-09-06 22:19:39 +00:00
John Baldwin
c3ba1376f5 Add a function pci_probe_route_table() that returns true if our PCI BIOS
supports interrupt routing and if the specified PCI bus is present in the
routing table.
2002-09-06 22:15:44 +00:00
John Baldwin
facfd6e8ed Dump the $PIR table if booting verbose. 2002-09-06 19:25:25 +00:00
John Baldwin
8ab96fd8d0 - Add a pci_cfgintr_valid() function to see if a given IRQ is a valid
IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table.
- Change pci_cfgintr() to except the current IRQ of a device as a fourth
  argument and to use that IRQ for the device if it is valid.
- If an intpin entry in a $PIR entry has a link of 0, it means that that
  intpin isn't connected to anything that can trigger an interrupt.  Thus,
  test the link against 0 to find invalid entries in the table instead of
  implicitly relying on the irqs field to be zero.  In the machines I have
  looked at, intpin entries with a link of 0 often have the bits for all
  possible interrupts for PCI devices set.
2002-09-06 17:08:07 +00:00
John Baldwin
fbabd7bec2 Add support for printing out the contents of a PCI BIOS $PIR interrupt
routing table on the console.  Eventually it will be printed during
verbose boots.
2002-09-06 16:10:12 +00:00
John Baldwin
cea0a89545 Prefer the physical bus number of the PCI bus as the unit of the pciX
device created.
2002-09-06 16:09:07 +00:00
John Baldwin
5264a94f3f Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,
not the 'entry' member.  The entry point is formed from both a base and
a relative entry point.  'entry' is that relative offset.  It is perfectly
valid to have an entry point with a relative offset of 0.  PCIbios.ventry
is the virtual address of the entry point that takes both 'base' and
'entry' into account, thus it is the proper variable to test to see if we
have an entry point or not.
2002-09-05 17:07:07 +00:00
Poul-Henning Kamp
bd8add3d61 Change the support for AMDs ElanSC520 CPU from being a device driver to
be
	options	CPU_ELAN
(NB: Soekris.com users!)

It is cleaner this way.  We still recognize the cpu on the host-pci bridge.
2002-09-04 19:43:22 +00:00
Poul-Henning Kamp
14a3a6ea0b Move a prototype to the least wrong place.
Suggested by:	bde
2002-08-02 18:45:43 +00:00
Warner Losh
e300f53ca2 style(9)ize the whole file
Approved in concept a long time ago by: msmith
2002-07-21 05:35:42 +00:00
Andrew Gallatin
f76ec8facd Add support for probing secondary buses on the ServerWorks Grand Champion
chipset used for P4-Xeon machines

PR: kern/38894
Tested-by: "Marc G. Fournier" <scrappy@hub.org>
Submitted-by: Mark Tinguely (partially)
2002-07-19 18:35:08 +00:00
Poul-Henning Kamp
61658cf6a1 Add initialization code for the AMD Elan sc520 which maps the MMCR
into KVM and sets the i8254 frequency to the correct value.
2002-07-18 12:56:54 +00:00
Poul-Henning Kamp
3ae87b7ec6 Add an entry for the AMD Elan SC520 hostbridge. I do not belive we can
identify this gadget on the CPUID result alone, so I intend to activate
the necessary magic (i8254 frequency for instance) for it based on the
precense of the on-chip host to PCI bridge.
2002-07-18 10:57:20 +00:00
Warner Losh
8ce1ab3a24 Use a common function to map the bogus intlines.
Don't require pin be non-zero before we map bogus intlines, always do it.
This fixes a number of problems on HP Omnibook computers.

Tested/Reviewed by: Brooks Davis
2002-06-01 05:14:11 +00:00
Brooks Davis
26722a1909 Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just having
it in pci_cfgregread() wasn't sufficent on at least the HP Omnibook 500.

Reviewed by:	imp
2002-05-29 16:16:16 +00:00
Warner Losh
d5ccecfad7 o Work around bugs in the powerof2 macro: It thinks that 0 is a power of
2, but that's not the case.  This fixes the case where there were slots
  in the PIR table that had no bits set, but we assumed they did and used
  strange results as a result.
o Map invalid INTLINE registers to 255 in pci_cfgreg.c.  This should allow
  us to remove the bogus checks in MI code for non-255 values.

I put these changes out for review a while ago, but no one responded
to them, so into current they go.

This should help us work better on machines that don't route
interrupts in the traditional way.

MFC After: 4286 millifortnights
2002-04-24 15:30:11 +00:00
Warner Losh
e5d7e9c76c Fix a PNPID in a comment
Submitted by: David Xu
2002-04-24 15:22:53 +00:00
Nicolas Souchu
c17d43407f Major rework of the iicbus/smbus framework:
- VIA chipset SMBus controllers added
	- alpm driver updated
	- Support for dynamic modules added
	- bktr FreeBSD smbus updated but not tested
	- cleanup
2002-03-23 15:49:15 +00:00
Warner Losh
654d58ca24 Don't call the bios if the interrupt appaers to be already routed. Some
older PCI BIOSes hate this and this leads to panics when it is done.  Also,
assume that a uniquely routed interrupt is already routed.  This also
seems to help some older laptops with feable BIOSes cope.
2002-03-16 23:02:41 +00:00
Warner Losh
a8c18609ec The Libretto L series has no $PIR table, but does have a _PIR table.
This typo keeps us from properly routing an interrupt for CardBus
bridges on this machine.  So, now we look for $PIR and then _PIR to
cope.  With these changes, the Libretto L1 now works properly.
Evidentally, the idea comes from patch that the Japanese version of
RedHat (or against a Japanese version of Red Hat), but my Japanese
isn't good enough to to know for sure.

Reported by: Hiroyuki Aizu-san <eyes@navi.org>

# This may be an MFC candidate, but I'm not yet sure.
2002-01-20 03:28:29 +00:00
Murray Stokely
b0ae3ab3fe Add identification string for AMD-761 host to PCI bridge.
PR:	kern/32255
2001-12-10 09:27:00 +00:00
Warner Losh
1cf5f5552b MFS: I was confused. This code wasn't in -current after all.
Merge in the irq 0 detection.  Add comment about why.

If we have irq 0, ignore it like we do irq 255.  Some BIOS writers aren't
careful like they should be.
2001-11-26 21:25:03 +00:00
Warner Losh
d3b6477a19 It turns out that while Toshiba laptops don't want to route interrupts
multiple times, others do.  The last strategy, which was to assume
that already routed interrupts were good and just return them doesn't
work for some laptops.  So, instead, we have a new strategy: we notice
that we have an interrupt that's already routed.  We go ahead and try
to route it, none the less.  We will assume that it is correctly
routed, even if the route fails.  We still assume that other failures
in the bios32 call are because the interrupt is NOT routed.

Note: some laptops do not support the bios32 interface to PCI BIOS and
we need to call it via the INT 2A interface.  That is another windmill
to till at later.

Also correct a minor typo and minor whitespace nits.

Strong MFC candidate.
2001-08-28 16:35:01 +00:00
Warner Losh
d626906b0c MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.
Check return value from bios32.

[[ Yes, I was bad and committed this to stable first.  I should have done
   the commit in the other order. ]]
2001-08-27 20:44:38 +00:00
Warner Losh
0b9427de88 The general conesnsus on irc was that pci bios for config registers
and such was just a bad idea and one that users should be forced to
enable if they want it.  This patch introduces a hw.pci.enable_pcibios
tunable for those people.  This does not impact the pcibios interrupt
routing at all.

Approved by: peter, msmith
2001-08-21 07:53:37 +00:00
Peter Wemm
573be82757 Detect a certain type of PCIBIOS brain damage. For some reason,
some bios vendors took it apon themselves to "censor" the
host->pci bridges from PCIBIOS callers, even when the caller
explicitly asks for them.  This includes certain Compaq machines
(eg: DL360) and some laptops.

If we detect this, shut down pcibios and revert to using IO
port bashing.

Under -current, apcica does a better job anyway.
2001-08-21 03:10:55 +00:00
Mike Smith
85fab96387 Un-swap irq/link byte values so that printf works. 2001-05-11 04:52:29 +00:00
Mike Smith
6c9eb5f3a6 Free the memory we get from devclass_get_devices and device_get_children.
Submitted by:	wpaul
2001-02-08 20:44:49 +00:00
Peter Wemm
47c6b72621 Fix a warning due to missing prototype. 2001-01-19 09:10:14 +00:00
Bosko Milekic
6a47d852b9 Remove declaration of airq variable from outer block. There were two
declarations of a variable of the same name. The one in the outer block
was unused and probably just slipped in at one point or another. This
silences a compiler warning.
2001-01-12 07:49:29 +00:00
Mike Smith
bb0d0a8efc Next phase in the PCI subsystem cleanup.
- Move PCI core code to dev/pci.
 - Split bridge code out into separate modules.
 - Remove the descriptive strings from the bridge drivers.  If you
   want to know what a device is, use pciconf.  Add support for
   broadly identifying devices based on class/subclass, and for
   parsing a preloaded device identification database so that if
   you want to waste the memory, you can identify *anything* we know
   about.
 - Remove machine-dependant code from the core PCI code.  APIC interrupt
   mapping is performed by shadowing the intline register in machine-
   dependant code.
 - Bring interrupt routing support to the Alpha
   (although many platforms don't yet support routing or mapping
   interrupts entirely correctly).  This resulted in spamming
   <sys/bus.h> into more places than it really should have gone.
 - Put sys/dev on the kernel/modules include path.  This avoids
   having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
Mike Smith
e9ca98b28f Hack to work around a probe which will lock up at least some i450GX-based
systems.

From the PR:

 When 'probe.slot' is PCI_SLOTMAX (== 31) and 'probe.func' is 7,
 call to 'pci_cfgread()' here and machine suddenly hangs up.
 I don't know why...  (or 450GX chipset's bug?)

PR:		i386/20379
Submitted by:	Masayuki FUKUI <fukui@sonic.nm.fujitsu.co.jp>
2000-11-08 11:25:15 +00:00
Mike Smith
099d058b54 Improve the PCI interrupt routing code. Now the process is as follows:
- Look for a hardwired interrupt in the routing table for this
   bus/device/pin (we already did this).
 - Look for another device with the same link byte which has a hardwired
   interrupt.
 - Look for a PCI device matching an entry with the same link byte
   which has already been assigned an interrupt, and use that.
 - Look for a routable interrupt listed in the "PCI only" interrupts
   field and use that.
 - Pick the first interrupt that's marked as routable and use that.
2000-11-02 00:37:45 +00:00
Andrey A. Chernov
c07f6a2dd1 Return -10000 in pci_hostb_probe to allow agp driver (disabled otherwise) 2000-10-20 15:40:05 +00:00
Andrey A. Chernov
da0f52e1ea Add i815 Host to Hub 2000-10-20 15:14:51 +00:00
Mike Smith
9d55863400 Call the BIOS to route the selected interrupt. Correctly calculate the
interrupt from the PCI routing table (ffs returns 1 for the rightmost
bit, not 0).
2000-10-19 08:06:50 +00:00
Warner Losh
a37932521c Remove debug writes introduced in prior commit 2000-10-16 07:31:13 +00:00
Warner Losh
54c9005faf Add the ability to use the $PIR table in the BIOS to route interrupts
on demand.

Submitted by: msmith
2000-10-16 07:25:08 +00:00
Alan Cox
e0284d2eb1 Change the text for the ServerWorks north bridge chips. RCC is now
officially listed as ServerWorks by www.pcisig.com.
2000-10-14 23:45:09 +00:00
Mike Smith
3c3134d3a0 When testing for PCI bus overlap with another enumerator, make sure we
check for the right bus number.  This is still not quite right, but
fixes things for multi-bus machines again.

Submitted by:	tegge
2000-10-11 23:03:11 +00:00
Mike Smith
03de26e0d0 Only attach "legacy" PCI busses if none have been attached via any other
method.
2000-10-09 00:44:41 +00:00
Mike Smith
12a02d6efd Move the i386 PCI attachment code out of i386/isa back into i386/pci.
Split out the configuration space access primitives, as these are needed
elsewhere as well.
2000-10-02 07:11:13 +00:00
Peter Wemm
b6c8407840 Get out the roto-rooter and clean up the abuse of nexus ivars by the
i386/isa/pcibus.c.  This gets -current running again on multiple host->pci
machines after the most recent nexus commits.  I had discussed this with
Mike Smith, but ended up doing it slightly differently to what we
discussed as it turned out cleaner this way.  Mike was suggesting creating
a new resource (SYS_RES_PCIBUS) or something and using *_[gs]et_resource(),
but IMHO that wasn't ideal as SYS_RES_* is meant to be a global platform
property, not a quirk of a given implementation.  This does use the ivar
methods but does so properly.  It also now prints the physical pci bus that
a host->pci bridge (pcib) corresponds to.
2000-09-28 00:37:32 +00:00
Peter Wemm
4d8ea19f7c Catch a few more bogosities in certain chipsets before they mess us up.
Some have dual host->PCI bridges for the same logical pci bus (!), eg:
some of the RCC chipsets.  This is a 32/64 bit 33/66MHz and dual pci
voltage motherboard so persumably there are electical or signalling
differences but they are otherwise the same logical bus.
The new PCI probe code however was getting somewhat upset about it and
ended up creating two pci bridges to the same logical bus, which caused
devices on that logical bus to appear and be probed twice.

The ACPI data on this box correctly identifies this stuff, so bring on
ACPI! :-)
2000-09-05 00:53:34 +00:00
Peter Wemm
280b4748af Take a shot at fixing multiple pci busses on i386.
pcib_set_bus() cannot be used on the new child because it is
meant to be used on the *pci* device (it looks at the parent internally)
not the pcib being added.  Bite the bullet and use ivars for the bus
number to avoid any doubts about whether the softc is consistant between
probe and attach.  This should not break the Alpha code.
2000-08-31 23:11:35 +00:00
Doug Rabson
21c3015a24 * Completely rewrite the alpha busspace to hide the implementation from
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
  which call busspace.
* Rework pci config accesses to route through the pcib device instead of
  calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Mike Smith
2a50a6d730 Add PnP probe methods to some common AT hardware drivers. In each case,
the PnP probe is merely a stub as we make assumptions about some of this
hardware before we have probed it.

Since these devices (with the exception of the speaker) are 'standard',
suppress output in the !bootverbose case to clean up the probe messages
somewhat.
2000-06-23 07:44:33 +00:00
Jun Kuriyama
569e965893 Add OPTi 82C700 chipset.
Submitted by:	sanpei@sanpei.org
PR:		kern/18155 (part of)
2000-05-24 09:03:30 +00:00
Jun Kuriyama
3cc13eb5b1 Add 440MX chipset.
Submitted by:	YOSHIMURA Hideaki <hideakiy@cs-tokyo01.chuosystem.co.jp>
References:	[bsd-nomads:13764]
2000-05-24 02:24:38 +00:00
Mike Smith
ac9b3dacb2 Don't assume that the PCI BIOS is going to clear the unused bits in %ecx
when it returns.
2000-05-04 17:44:55 +00:00
Mike Smith
300451c472 Some more i386-only BIOS-friendliness:
- Add support for using the PCI BIOS functions for configuration space
   accesses, and make this the default.

 - Make PNPBIOS the default (obsoletes the PNPBIOS config option).

 - Add two new boot-time tunables to disable each of the above.
2000-04-16 20:48:33 +00:00
Doug Rabson
ac19291f35 Add a workaround to allow us to detect the second pci bus on an HP
Netserver LS/2.

Approved by: jkh
2000-02-23 20:25:06 +00:00
Doug Rabson
9a1498a435 Fix an uninitialised variable which affected probing on some machines.
Approved by: jkh
Reviewed by: gallatin
2000-02-13 09:49:05 +00:00
Andrew Gallatin
da4009202a Allow allows peer pci buses which are directly connected to the RCC host pci
chipset to be probed & attached on newer Dell PowerEdge servers, such as
the 2400 and 4400.

Reviewed by: 	dfr, msmith, jlemon
Tested by:	hnokubi@yyy.or.jp (in a previous incantation)
Approved by:	jkh
2000-02-09 20:05:30 +00:00
Nick Hibma
4f2e8d6383 Add PCI Id's for i810 chipsets.
PR:		16517
Submitted by:	SAKIYAMA Nobuo <sakichan@lares.dti.ne.jp>
Approved by:	jhk
2000-02-07 12:50:33 +00:00
Peter Wemm
4a1e4cb727 Clean up the cfgmech/pci_mechanism debris. The reason for the existance
of this is no longer an issue as we have a replacement driver for the
one that needed it.

Reviewed by:	dfr
2000-01-08 08:31:24 +00:00
Doug Rabson
c954d7368a Don't use a bogus bus number for Ross host-pci bridges.
PR:	kern/15278
Submitted by: Ahmed Benani <ahmed_benani@urbanet.ch>
1999-12-05 18:41:34 +00:00
Matthew N. Dodd
fe0d408987 Remove the 'ivars' arguement to device_add_child() and
device_add_child_ordered().  'ivars' may now be set using the
device_set_ivars() function.

This makes it easier for us to change how arbitrary data structures are
associated with a device_t.  Eventually we won't be modifying device_t
to add additional pointers for ivars, softc data etc.

Despite my best efforts I've probably forgotten something so let me know
if this breaks anything.  I've been running with this change for months
and its been quite involved actually isolating all the changes from
the rest of the local changes in my tree.

Reviewed by:	peter, dfr
1999-12-03 08:41:24 +00:00
Peter Wemm
cde35e1a3d If we have found pci devices via pci_cfgopen(), but don't find a
host->pci bridge specifically, then add a pcib0 device on the motherboard
for the pci bus to hang off.

Requested by:  Anders Andersson <anders@sanyusan.se>
Obtained from: dfr
1999-11-18 08:58:37 +00:00
Alan Cox
eab7cc95c4 Add text for the AMD-751 host-to-PCI and PCI-to-PCI (AGP) bridges. 1999-10-25 06:28:04 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Peter Wemm
f3b63bd388 Make the identify routine add itself with priority 100 to make sure it
goes after the npx/apm devices and any other motherboard devices that
may get added down the track.
1999-08-22 19:54:11 +00:00
Peter Wemm
accc665bbe Hopefully fix the previous commit, it caused *all* bridges to be detected
as PCI->HOST bridges on my (440BX) box.

My change is to remove the test at the beginning entirely, letting the
switch on the device ID happen first.  If the device ID is unknown, then
(in the default case) check for the generic PCIS_BRIDGE_HOST tag.  This
should allow wierd cases (eg: wpaul's IMS VL bridge) to work by using the
id override.  This strategy is more in line with the other PCI match
methods we use elsewhere,

I only have a limited testbed, but having my USB etc devices detected as
PCI->HOST bridges doesn't look good.
1999-08-10 09:22:21 +00:00
Bill Paul
d9d628b000 Fix nexus_pcib_is_host_bridge() so that it detects my 486's PCI bus
correctly. It has the following code:

        if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_HOST)
                return NULL;

My 486 has an Integrated Micro Solutions PCI bridge which identifies
itself as subclass PCIS_BRIDGE_OTHER, not PCIS_BRIDGE_HOST. Consequently,
it gets ignored. In my opinion, the correct test should be:

        if ((class != PCIC_BRIDGE) && (subclass != PCIS_BRIDGE_HOST))
                return NULL;

That way the test still succeeds because the chip's class is PCIC_BRIDGE.
Clearly it's not reasonable to expect all host to PCI bridges to always
have a subclass of PCIS_BRIDGE_HOST since I've got one that doesn't.
This way the sanity test should remain relatively sane while still allowing
some oddball yet correct hardware to work. If somebody has a better way
to do it, go ahead and tweak the test, but be aware that
class == PCIC_BRIDGE and subclass == PCIS_BRIDGE_OTHER is a valid case.

While I was here, I also added an explicit ID string for the IMS chipset.
I also dealt with a minor style nit: it's bad karma not to have a default
case for your switch statements, but the one in this routine doesn't have
one. The default string of "Host to PCI bridge" is now assigned in a
default case of the switch statement instead of initializing "s" with the
string before the switch and then not having any default case.
1999-08-09 21:12:18 +00:00
Peter Wemm
cac6a04400 Don't probe if pci_cfgopen() fails to find pci hardware, like we used to
to.  This might have caused interesting things on non-PCI hardware if
PCI was compiled in.
1999-08-04 13:38:24 +00:00
Mike Smith
850013034a Add support for multiple PCI busses directly connected to the nexus.
This is only partially complete, but allows 450NX-based systems with
more than one PCI bus to be used again.

Submitted by:	dfr
1999-07-16 01:00:30 +00:00
Peter Wemm
8dc26439da Move pcibus (host -> pci bus) probe/attach routines from nexus
to pcibus.c.  pci_cfgopen() becomes static and there are no more
bus #ifdef's in nexus.c.
1999-05-18 20:48:43 +00:00
Stefan Eßer
8277ac255e Make the class code checks in function pci_cfgcheck less strict.
It failed to recognize the PCI bus in a system that had only an
old chip-set (class code 000000) and a Cyclom multiport serial
card on PCI bus 0, but no VGA card or disk or network controller.

PR:		i386/5300
Submitted by:	Nickolay N. Dudorov <nnd@itfs.nsk.su>
1997-12-20 09:04:25 +00:00
Bruce Evans
f71d35e402 Removed unused #includes. 1997-07-20 14:10:18 +00:00
Stefan Eßer
b3daa02e72 Yet another fix for configuration mechanism 1 register accesses:
Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).
1997-05-26 21:52:41 +00:00
Stefan Eßer
64039d403f Fix previous fix: The enable bit is bit 31 (0x8000000) and not bit 15. 1997-05-26 21:25:24 +00:00
Stefan Eßer
e0c57a9615 Set enable bit when writing the configuration address in configuration
mode 1. Omission of this bit makes all config register accesses fail in
on recent chip sets ...

(The problem was reported and debug output provided by: Steve Passe)
1997-05-26 21:11:05 +00:00
Stefan Eßer
5bec615793 Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
Stefan Eßer
5c03639065 Mask out revision register in consistency test of class register. 1997-04-09 11:34:50 +00:00
Stefan Eßer
6df09d1e0b Fix spelling of align and interrupt in comments. 1997-04-09 09:16:27 +00:00
Stefan Eßer
b4b8847934 Fix consistency test to not fail on pre PCI 2.0 motherboards 1997-04-09 09:15:03 +00:00
Stefan Eßer
81cf5d7aae improve pcibus_check: Only assume PCI if at least one PCI to anything bridge
on bus 0.
This fixes problems with EISA-only systems mistakenly being assumed to support PCI.
1997-03-05 20:52:00 +00:00
Peter Wemm
6875d25465 Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.
1997-02-22 09:48:43 +00:00
Bruce Evans
4123678332 Sync with <pci/pcibus.h>. pcibus.c unfortunately still compiled (with
only 3 or 4 warnings) when pb_maxirq went away.
1997-01-25 18:51:01 +00:00
Jordan K. Hubbard
1130b656e5 Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore.  This update would have been
insane otherwise.
1997-01-14 07:20:47 +00:00
Nate Williams
62ce633d36 Make the code more consistant by using the INTR*MASK macros througout the
code.

Reviewed by:	bde

[
Bruce suggest removing the macros completely, but I'm not up to that
task quite yet.
]
1997-01-08 16:12:56 +00:00
Satoshi Asami
e30f001135 More merge and update.
(1) deleted #if 0

    pc98/pc98/mse.c

(2) hold per-unit I/O ports in ed_softc

    pc98/pc98/if_ed.c
    pc98/pc98/if_ed98.h

(3) merge more files by segregating changes into headers.

  new file (moved from pc98/pc98):

    i386/isa/aic_98.h

  deleted:

    well, it's already in the commit message so I won't repeat the
    long list here ;)

Submitted by:	The FreeBSD(98) Development Team
1996-10-30 22:41:46 +00:00
Bruce Evans
9b2b0822b7 Removed unused #includes of <i386/isa/icu.h> and <i386/isa/icu.h>. icu.h
is only used by the icu support modules and by a few drivers that know
too much about the icu (most only use it to convert `n' to `IRQn').  isa.h
is only used by ioconf.c and by a few drivers that know too much about
isa addresses (a few have to, because config is deficient).
1996-06-18 01:22:40 +00:00
Stefan Eßer
21219d2116 Change CONF1_ENABLE_MSK to 0x7ff00000 in another attempt to decide
whether a system could possibly support PCI configuration mechanism 1
(or whether it rather is an EISA only system ...).
1996-06-13 21:50:41 +00:00
Stefan Eßer
e20df7fc31 Make pcibus_check() ignore Device/Vendor IDs of all 0. 1996-04-30 21:37:21 +00:00
Bruce Evans
3157adc8af Removed now-unused #includes of <machine/cpu.h>. They were for bootverbose
being declared in the wrong place.
1996-04-07 17:32:42 +00:00
Bruce Evans
a680ab7537 Count PCI irqs in up to 4 ISAish counters named `pci irqnn' instead of
in the clk0 counter.

Reviewed by:	s
1996-03-29 15:01:51 +00:00
Bruce Evans
6ea3e9d839 Completed function declarations and/or added prototypes and/or added
#includes to get prototypes.

pci now uses a different interrupt handler type for interrupts that it
dispatches and the isa interrupt handler type for the interrupts that
it handles.
1995-12-16 00:27:59 +00:00
Poul-Henning Kamp
6f4e0beb7e Staticize and cleanup. 1995-12-10 13:40:44 +00:00
Stefan Eßer
2e80ea0536 Make CONF1_ENABLE_MSK1 even less restriktive: Ignore slot ID ... 1995-10-17 23:30:11 +00:00
Stefan Eßer
0e2f699b9e At least the ASUS Triton motherboards don't disable the PCI bus configuration
accesses after the BIOS bus scan. The previous revision made the assumption,
that every PCI motherboard did ...

Change the test on the initial value of the CONF1_ADDR_PORT register in a way
that makes the probe succeed on triton based motherboards, without breaking
the EISA motherboard that has some non-PCI register at the same address.
1995-10-17 15:23:14 +00:00
Stefan Eßer
287911bd50 Go back to separate tests for configuration mechanism 1 and mechanism 2.
Require the state of the configuration enable bits to be OFF assuming
that the BIOS left them that way, as it should anyway to avoid bad things
to happen.

The tests themselves are copied from the previous release, with the
exception of CONF1_ENABLE_MSK1 having the LSB set. This bit should be
read back as '0', since only DWORD addresses are legal.
1995-10-15 23:43:08 +00:00
Stefan Eßer
c7483249e7 Fix bad typo: CONF1_ENABLE_RES1 was written CONF1_ENABLE_CHK1 ... 1995-10-09 21:56:24 +00:00
Stefan Eßer
77b573149a New approach to the PCI bus configuration mechanism probe problem:
- try to make sure there is any kind of PCI device
- if there is anything at port 0x0cf8, then check for mech. 1 or 2
1995-09-22 19:10:54 +00:00
Stefan Eßer
a3adc4f8c5 Revert most changes of previous commit.
Changes relative to 1.12:
- Put extra instruction between outl()/inl() sequence to prevent the
  old value being read back because of the bus capacitance.
- Additional check for existence of register at CONF2_ENABLE_PORT.
1995-09-18 21:48:39 +00:00