282d1ef778
This was omitted in r334112 and r334996 which cause the PLL to not correctly reparent, leaving the armclk to be derived from the APLL instead of the NPLL. The arm core clock is now correctly set to 600Mhz via the assigned-clock present in the DTB. |
||
---|---|---|
.. | ||
acpica | ||
arm64 | ||
cavium | ||
cloudabi32 | ||
cloudabi64 | ||
conf | ||
coresight | ||
include | ||
linux | ||
qualcomm | ||
rockchip |