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allwinner
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allwinner: Add A64 ccung support
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2017-07-03 19:30:03 +00:00 |
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altera/socfpga
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Add FPGA manager driver for Intel Arria 10.
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2017-03-03 14:19:37 +00:00 |
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amlogic/aml8726
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Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
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2017-03-07 22:42:44 +00:00 |
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annapurna/alpine
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Add PLATFORM and PLATFORM_SMP support to the ALPINE kernel configuration.
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2017-07-04 12:26:47 +00:00 |
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arm
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Require the ARM Generic Timer driver is built for MULTIDELAY on 32bit arm.
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2017-07-05 09:27:18 +00:00 |
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at91
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Load the transmit dma buffer at attach time as well. We don't need to
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2017-06-18 21:03:35 +00:00 |
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broadcom/bcm2835
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Fix spelling mistake, BCM2835_PASWORD -> BCM2835_PASSWORD
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2017-04-03 22:36:45 +00:00 |
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cavium/cns11xx
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Allow setting access-width for UART registers.
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2017-02-27 20:08:42 +00:00 |
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cloudabi32
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Move struct syscall_args syscall arguments parameters container into
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2017-06-12 21:03:23 +00:00 |
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conf
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Require the ARM Generic Timer driver is built for MULTIDELAY on 32bit arm.
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2017-07-05 09:27:18 +00:00 |
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freescale
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Add a driver for the imx6 on-chip realtime clock.
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2017-07-04 18:38:34 +00:00 |
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include
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Clean up MD pollution of bus_dma.h:
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2017-07-01 05:35:29 +00:00 |
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lpc
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Add and use a MMC_DECLARE_BRIDGE macro for declaring mmc(4) bridges
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2017-03-07 22:42:44 +00:00 |
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mv
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Create root DMA tag and fix MBUS windows on DMA coherent platforms
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2017-06-21 18:27:05 +00:00 |
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nvidia
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Restore original (pre r315760) naming for Tegra SDHCI device.
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2017-03-23 08:16:53 +00:00 |
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qemu
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Make the default FDT implementation of platform_mp_setmaxid use the cpu
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2017-03-17 12:45:53 +00:00 |
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ralink
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[arm] [rt1310] add initial RT1310 SoC code.
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2017-05-06 06:14:46 +00:00 |
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rockchip
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Remake support for SMP kernel on UP cpu:
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2017-02-02 06:14:44 +00:00 |
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samsung/exynos
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Add a delay count to the last few places. This will help make MULTIDELAY
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2017-07-04 17:15:23 +00:00 |
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ti
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Move the simple armv6 only timer drivers to require MULTIDELAY to help
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2017-07-04 18:07:09 +00:00 |
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versatile
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Move the simple armv6 only timer drivers to require MULTIDELAY to help
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2017-07-04 18:07:09 +00:00 |
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xilinx
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Add a delay count to the last few places. This will help make MULTIDELAY
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2017-07-04 17:15:23 +00:00 |
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xscale
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Allow setting access-width for UART registers.
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2017-02-27 20:08:42 +00:00 |
88fd0c95a3