freebsd-dev/sys/x86/x86
Konstantin Belousov dc43978aa5 amd64: allow parallel shootdown IPIs
Stop using smp_ipi_mtx to protect global shootdown state, and
move/multiply the global state into pcpu.  Now each CPU can initiate
shootdown IPI independently from other CPUs.  Initiator enters
critical section, then fills its local PCPU shootdown info
(pc_smp_tlb_XXX), then clears scoreboard generation at location (cpu,
my_cpuid) for each target cpu.  After that IPI is sent to all targets
which scan for zeroed scoreboard generation words.  Upon finding such
word the shootdown data is read from corresponding cpu' pcpu, and
generation is set.  Meantime initiator loops waiting for all zeroed
generations in scoreboard to update.

Initiator does not disable interrupts, which should allow
non-invalidation IPIs from deadlocking, it only needs to disable
preemption to pin itself to the instance of the pcpu smp_tlb data.

The generation is set before the actual invalidation is performed in
handler. It is safe because target CPU cannot return to userspace
before handler finishes. In principle only NMI can preempt the
handler, but NMI would see the kernel handler frame and not touch
not-invalidated user page table.

Handlers loop until they do not see zeroed scoreboard generations.
This, together with hardware keeping one pending IPI in LAPIC IRR
should prevent lost shootdowns.

Notes.
1. The code does protect writes to LAPIC ICR with exclusion. I believe
   this is fine because we in fact do not send IPIs from interrupt
   handlers. More for !x2APIC mode where ICR access for write requires
   two registers write, we disable interrupts around it. If considered
   incorrect, I can add per-cpu spinlock around ipi_send().
2. Scoreboard lines owned by given target CPU can be padded to the
   cache line, to reduce ping-pong.

Reviewed by:	markj (previous version)
Discussed with:	alc
Tested by:	pho
Sponsored by:	The FreeBSD Foundation
MFC after:	3 weeks
Differential revision:	https://reviews.freebsd.org/D25510
2020-07-14 20:37:50 +00:00
..
autoconf.c
bus_machdep.c Port the NetBSD KCSAN runtime to FreeBSD. 2019-11-21 11:22:08 +00:00
busdma_bounce.c Remove unnecessary WITNESS check in x86 bus_dma 2020-06-03 00:16:36 +00:00
busdma_machdep.c Remove unnecessary WITNESS check in x86 bus_dma 2020-06-03 00:16:36 +00:00
cpu_machdep.c Control for Special Register Buffer Data Sampling mitigation. 2020-06-12 22:14:45 +00:00
delay.c
dump_machdep.c
fdt_machdep.c
identcpu.c x86: add bits definitions for SRBDS mitigation control. 2020-06-12 22:12:57 +00:00
intr_machdep.c Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many) 2020-02-26 14:26:36 +00:00
io_apic.c Do not spuriously re-enable disabled io_apic pin on EOI for some configurations. 2020-03-18 21:34:52 +00:00
legacy.c Stop listing "on motherboard" as the parent of nexus devices on x86. 2019-08-14 22:13:11 +00:00
local_apic.c Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many) 2020-02-26 14:26:36 +00:00
mca.c Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many) 2020-02-26 14:26:36 +00:00
mp_watchdog.c Mark more nodes as CTLFLAG_MPSAFE or CTLFLAG_NEEDGIANT (17 of many) 2020-02-26 14:26:36 +00:00
mp_x86.c amd64: allow parallel shootdown IPIs 2020-07-14 20:37:50 +00:00
mptable_pci.c Drop "All rights reserved" from my copyright statements. 2019-03-06 22:11:45 +00:00
mptable.c Drop "All rights reserved" from my copyright statements. 2019-03-06 22:11:45 +00:00
msi.c x86: Bump default msi/msix vector limit to 2048 2020-06-12 18:41:12 +00:00
nexus.c Move phys_avail definition into MI code. It is consumed in the MI layer and 2019-08-16 00:45:14 +00:00
pvclock.c
stack_machdep.c Reimplement stack capture of running threads on i386 and amd64. 2020-01-31 15:43:33 +00:00
tsc.c Assume all TSCs are synchronized for AMD Family 17h processors and later 2020-06-22 20:42:58 +00:00
ucode.c Free microcode memory later. 2019-05-17 17:11:01 +00:00
x86_mem.c