freebsd-nq/sys/mips/atheros/files.ar71xx

# $FreeBSD$

mips/atheros/apb.c		standard
mips/atheros/ar71xx_gpio.c	optional gpio
mips/atheros/ar71xx_machdep.c	standard
mips/atheros/ar71xx_ehci.c	optional ehci
mips/atheros/ar71xx_ohci.c	optional ohci
mips/atheros/ar71xx_pci.c	optional ar71xx_pci pci
mips/atheros/ar724x_pci.c	optional ar724x_pci pci
mips/atheros/ar71xx_pci_bus_space.c	optional pci
mips/atheros/ar71xx_spi.c	optional ar71xx_spi
mips/atheros/pcf2123_rtc.c	optional pcf2123_rtc ar71xx_spi
mips/atheros/ar71xx_wdog.c	optional ar71xx_wdog
mips/atheros/if_arge.c		optional arge
mips/atheros/uart_bus_ar71xx.c	optional uart_ar71xx
mips/atheros/uart_cpu_ar71xx.c	optional uart_ar71xx
mips/atheros/ar71xx_bus_space_reversed.c	standard
mips/mips/intr_machdep.c        standard
mips/mips/tick.c		standard
mips/atheros/ar71xx_setup.c	standard
mips/atheros/ar71xx_chip.c	standard
mips/atheros/ar724x_chip.c	standard
mips/atheros/ar91xx_chip.c	standard
mips/atheros/ar71xx_fixup.c	optional ar71xx_ath_eeprom

dev/hwpmc/hwpmc_mips24k.c	optional hwpmc
- Revert changes accidentally killed by merge operation 2009-04-14 22:53:22 +00:00			`# $FreeBSD$`

			`mips/atheros/apb.c standard`
Add AR71XX GPIO bus driver. 2010-09-28 03:31:34 +00:00			`mips/atheros/ar71xx_gpio.c optional gpio`
- Revert changes accidentally killed by merge operation 2009-04-14 22:53:22 +00:00			`mips/atheros/ar71xx_machdep.c standard`
- Add EHCI controller driver for AR71XX-based boards. 2009-04-19 22:58:36 +00:00			`mips/atheros/ar71xx_ehci.c optional ehci`
- Revert changes accidentally killed by merge operation 2009-04-14 22:53:22 +00:00			`mips/atheros/ar71xx_ohci.c optional ohci`
In preparation for the AR724x PCIe bus code, make the AR71xx PCI bus glue require 'device ar71xx_pci' . Users of the AR71xx board configs will now require this for functioning PCI: device pci device ar71xx_pci 2011-04-30 11:28:21 +00:00			`mips/atheros/ar71xx_pci.c optional ar71xx_pci pci`
Add some initial PCIe bridge support for the AR724x chipsets. This is reported to work on the AR7240 based Ubiquiti Rocket M5 but I haven't tested it on that hardware. I also don't yet have it fully working on the AR7242 based development board here; probe/attach functions but the register space resource looks like the endian-ness is wrong (0x10000000 instead of 0x00001000).o Further digging will be required. Submitted by: Luiz Otavio O Souza 2011-04-30 11:36:16 +00:00			`mips/atheros/ar724x_pci.c optional ar724x_pci pci`
- Add pci bus space that translates byte order to little endian, may be it will be merged with bus_space_reversed later - Handle memory resources close to bus in order to control bus_space_tag 2009-05-15 21:36:50 +00:00			`mips/atheros/ar71xx_pci_bus_space.c optional pci`
- Add SPI bus driver for ar71xx SoC 2009-05-18 23:32:04 +00:00			`mips/atheros/ar71xx_spi.c optional ar71xx_spi`
- Add driver for PCF2123, SPI real time clock/calendar 2010-01-22 22:14:12 +00:00			`mips/atheros/pcf2123_rtc.c optional pcf2123_rtc ar71xx_spi`
- Add AR71XX watchdog timer driver 2009-07-09 20:16:01 +00:00			`mips/atheros/ar71xx_wdog.c optional ar71xx_wdog`
- Revert changes accidentally killed by merge operation 2009-04-14 22:53:22 +00:00			`mips/atheros/if_arge.c optional arge`
Migrate the AR71xx UART (an 8250 derivative) to hide behind uart_ar71xx. The AR9330/AR9331 UART is a totally different thing, so having it included with 'uart' is not going to work out. 2012-11-17 04:05:46 +00:00			`mips/atheros/uart_bus_ar71xx.c optional uart_ar71xx`
			`mips/atheros/uart_cpu_ar71xx.c optional uart_ar71xx`
- Handle byte-order issue for non-word accesses to memory mapped registers with ar71xx_bus_space_reversed. Note, that byte order of values is handled by drivers. bus_spaces fixes only position of register in word. - Replace .hints hack for AR71XX UART with ar71xx_bus_space_reversed. 2009-04-19 22:56:35 +00:00			`mips/atheros/ar71xx_bus_space_reversed.c standard`
Does 4 things: 1) Adds future RMI directories 2) Places intr_machdep.c in specfic files.arch pointing to the generic intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c (which we will need for RMI) in the machine specific directory 3) removes intr_machdep.c from files.mips 4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We may need to look at finding a better place to put this. But first I want to get this thing compiling. 2009-10-15 21:03:32 +00:00			`mips/mips/intr_machdep.c standard`
With this commit our friend RMI will now compile. I have not tested it and the chances of it running yet are about ZERO.. but it will now compile. The hard part now begins, making it run ;-) 2009-10-30 08:53:11 +00:00			`mips/mips/tick.c standard`
Preparation work for supporting the AR91xx and AR724x. * Implement a SoC probe function, from Linux, which determines the SoC family, type and revision. This only probes the AR71xx series SoC and (currently) panics on others. * Migrate some of the AR71XX specific hardware init (USB device, determining system frequencies) into using the cpuops introduced in an earlier commit. Other SoC specific hardware stuff (per-device flush/WB, GPIO pin wiring, Ethernet PLL setup, other things I've likely missed) will be introduced in subsequent commits. Reviewed by: imp@ Obtained from: (partially) Linux 2010-08-19 02:03:12 +00:00			`mips/atheros/ar71xx_setup.c standard`
			`mips/atheros/ar71xx_chip.c standard`
Add some initial AR724X chipset support. This is untested but should at least allow an AR724X to boot. The current code is lacking the detail needed to expose the PCIe bus. It is also lacking any NIC, PLL or flush/WB code. 2010-08-19 11:53:55 +00:00			`mips/atheros/ar724x_chip.c standard`
Add initial Atheros AR91XX support. This works well enough to bring a system up to single-user mode using an MDROOT. Known Issues: * The EHCI USB doesn't currently work and will panic the kernel during attach. * The onboard ethernet won't work until the PLL routines have been fleshed out and shoe-horned into if_arge. * The WMAC device glue (and quite likely the if_ath support) hasn't yet been implemented. 2010-08-19 11:40:10 +00:00			`mips/atheros/ar91xx_chip.c standard`
Introduce the matching PCI ath(4) fixup code from ar71xx_pci into ar724x_pci.c. * Move out the code which populates the firmware into ar71xx_fixup.c * Shuffle around the ar724x fixup code to match what the ar71xx fixup code does. I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't yet load, as the AR9285 EEPROM code needs to be made "flash aware." TODO: * Validate that I haven't broken AR71xx * Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes * Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from Linux OpenWRT. The current WAR has only been tested on the AR7240 and I'm not sure the way the BAR register is treated is "right". The "fixup" method here is right when setting the BAR for local access - ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242), but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the initial "fixup" BAR. It then restores the original BAR. I'll have to read the ar724x PCI bus glue to see what other special cases await. 2012-04-20 08:26:05 +00:00			`mips/atheros/ar71xx_fixup.c optional ar71xx_ath_eeprom`
Rework MIPS PMC code: - Replace MIPS24K-specific code with more generic framework that will make adding new CPU support easier - Add MIPS24K support for new framework - Limit backtrace depth to 1 for stability reasons and add option HWPMC_MIPS_BACKTRACE to override this limitation 2012-03-22 18:01:23 +00:00
			`dev/hwpmc/hwpmc_mips24k.c optional hwpmc`