Commit Graph

120 Commits

Author SHA1 Message Date
Jung-uk Kim
7609e73ca0 Remove duplicate code. Reduce diff between amd64 and i386. 2012-12-01 00:56:19 +00:00
Jung-uk Kim
8c2b353ead Use volatile keywords properly. 2012-11-30 20:15:01 +00:00
Jung-uk Kim
231ac244f8 Tidy up inline assembly. No functional change. 2012-11-30 00:59:37 +00:00
Andriy Gapon
851dbc07af pciereg_cfg*: use assembly to access the mem-mapped cfg space
AMD BKDG for CPU families 10h and later requires that the memory
mapped config is always read into or written from al/ax/eax register.

Discussed with:	kib, alc
Reviewed by:	kib (earlier version)
MFC after:	25 days
2012-10-14 10:13:50 +00:00
Andriy Gapon
1e908511f8 number of cleanups in i386 and amd64 pci md code
o introduce PCIE_REGMAX and use it instead of ad-hoc constant
o where 'reg' parameter/variable is not already unsigned, cast it to
  unsigned before comparison with maximum value to cut off negative
  values
o use PCI_SLOTMAX in several places where 31 or 32 were explicitly used
o drop redundant check of 'bytes' in i386 pciereg_cfgread() - valid
  values are already checked in the subsequent switch

Reviewed by:	jhb
MFC after:	1 week
2009-09-24 07:11:23 +00:00
John Baldwin
d3da228f37 Add a read-only sysctl hw.pci.mcfg to mirror the tunable by the same name.
MFC after:	1 week
2009-05-18 21:47:32 +00:00
John Baldwin
6cad8eb41d Fall back to using configuration type 1 accesses for PCI config requests if
the requested PCI bus falls outside of the bus range given in the ACPI
MCFG table.  Several BIOSes seem to not include all of the PCI busses in
systems in their MCFG tables.  It maybe that the BIOS is simply buggy and
does support all the busses, but it is more conservative to just fall back
to the old method unless it is certain that memory accesses will work.
2009-03-24 18:10:22 +00:00
John Baldwin
3591fea8b0 Add a 'hw.pci.mcfg' tunable. It can be set to 0 to disable memory-mapped
PCI config access.
2008-09-11 21:42:11 +00:00
John Baldwin
2d10570afe Some K8 chipsets don't expose all of the PCI devices on bus 0 via PCIe
memory-mapped config access.  Add a workaround for these systems by
checking the first function of each slot on bus 0 using both the
memory-mapped config access and the older type 1 I/O port config access.
If we find a slot that is only visible via the type 1 I/O port config
access, we flag that slot.  Future PCI config transactions to flagged
slots on bus 0 use type 1 I/O port config access rather than memory mapped
config access.
2008-09-10 18:06:08 +00:00
John Baldwin
d320e05ca5 Extend the support for PCI-e memory mapped configuration space access:
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the
  rest of the kernel.  It now also accepts parameters via function
  arguments rather than global variables.
- Add a notion of minimum and maximum bus numbers and reject requests for
  an out of range bus.
- Add more range checks on slot/func/reg/bytes parameters to the cfg reg
  read/write routines.  Don't panic on any invalid parameters, just fail
  the request (writes do nothing, reads return -1).  This matches the
  behavior of the other cfg mechanisms.
- Port the memory mapped configuration space access to amd64.  On amd64
  we simply use the direct map (via pmap_mapdev()) for the memory mapped
  window.
- During acpi_attach() just after loading the ACPI tables, check for a
  MCFG table.  If it exists, call pciereg_cfgopen() on each subtable
  (memory mapped window).  For now we only support windows for domain 0
  that start with bus 0.  This removes the need for more chipset-specific
  quirks in the MD code.
- Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets
  since these machines should all have MCFG tables via ACPI.
- Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen()
  earlier.

MFC after:	2 weeks
2008-08-22 02:14:23 +00:00
John Baldwin
98bbce55fa Adjust the code to probe for the PCI config mechanism to use.
- On amd64, just assume type #1 is always used.  PCI 2.0 mandated
  deprecated type #2 and required type #1 for all future bridges which
  was well before amd64 existed.
- For i386, ignore whatever value was in 0xcf8 before testing for type #1
  and instead rely on the other tests to determine if type #1 works.  Some
  newer machines leave garbage in 0xcf8 during boot and as a result the
  kernel doesn't find PCI at all (which greatly confuses ACPI which expects
  PCI to exist when PCI busses are in the namespace).

MFC after:	3 days
Discussed with:	scottl
2007-11-28 22:20:08 +00:00
Bill Paul
ba3af76df7 Modify the pci_cfgdisable() routine to bring it more in line with
other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0
to the config address register when using config mechanism 1 to turn
off config access. In fact, it can be downright troublesome, since it
seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause
it to sporadically botch reads from some devices. This is the cause
of the missing USP ports problem I was experiencing with my Sun Opteron
system.

Also correct the case for mechanism 2: it's only necessary to write
a 0 to the ENABLE port.
2005-10-25 04:53:29 +00:00
Peter Wemm
ba2426ff44 MFi386: whitespace, copyright header, etc updates 2005-01-21 05:56:41 +00:00
Warner Losh
46280ae719 Begin all license/copyright comments with /*- 2005-01-05 20:17:21 +00:00
Peter Wemm
10884719f8 MFi386: nuke pci_cfgintr 2004-03-13 19:19:13 +00:00
Peter Wemm
d0f2d056fa MFi386: change an outb to a DELAY() 2004-01-28 20:46:31 +00:00
Peter Wemm
21616ec307 Various whitespace and cosmetic sync-up's with i386.
Approved by:  re (scottl)
2003-12-06 23:19:47 +00:00
David E. O'Brien
56ae44c5df Use __FBSDID().
Brought to you by:	a boring talk at Ottawa Linux Symposium
2003-07-25 21:19:19 +00:00
Peter Wemm
afa8862328 Commit MD parts of a loosely functional AMD64 port. This is based on
a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to
attempt to get a stable base to start from.  There is a lot missing still.
Worth noting:
- The kernel runs at 1GB in order to cheat with the pmap code.  pmap uses
  a variation of the PAE code in order to avoid having to worry about 4
  levels of page tables yet.
- It boots in 64 bit "long mode" with a tiny trampoline embedded in the
  i386 loader.  This simplifies locore.s greatly.
- There are still quite a few fragments of i386-specific code that have
  not been translated yet, and some that I cheated and wrote dumb C
  versions of (bcopy etc).
- It has both int 0x80 for syscalls (but using registers for argument
  passing, as is native on the amd64 ABI), and the 'syscall' instruction
  for syscalls.  int 0x80 preserves all registers, 'syscall' does not.
- I have tried to minimize looking at the NetBSD code, except in a couple
  of places (eg: to find which register they use to replace the trashed
  %rcx register in the syscall instruction).  As a result, there is not a
  lot of similarity.  I did look at NetBSD a few times while debugging to
  get some ideas about what I might have done wrong in my first attempt.
2003-05-01 01:05:25 +00:00
Peter Wemm
af3d516f55 Initiate de-orbit burn for USE_PCI_BIOS_FOR_READ_WRITE. This has been
#if'ed out for a while.  Complete the deed and tidy up some other bits.

We need to be able to call this stuff from outer edges of interrupt
handlers for devices that have the ISR bits in pci config space.  Making
the bios code mpsafe was just too hairy.  We had also stubbed it out some
time ago due to there simply being too much brokenness in too many systems.
This adds a leaf lock so that it is safe to use pci_read_config() and
pci_write_config() from interrupt handlers.  We still will use pcibios
to do interrupt routing if there is no acpi.. [yes, I tested this]

Briefly glanced at by:  imp
2003-02-18 03:36:49 +00:00
Warner Losh
a4bbd12ff1 MFp4:
o Fix small style nit.  This was supposed to be part of the last batch of
  style fixes, but somehow didn't get merged.
2002-11-14 05:22:37 +00:00
Warner Losh
ce494452fe MFp4:
o It turns out that we always need to try to route the interrupts for
  the case where the $PIR tells us there can be only one.  Some machines
  require this, while others fail when we try to do this (bogusly, imho).
  Since we have no apriori way of knowing which is which, we always try to
  do the routing and hope for the best if things fail.
o Add some additional comments that state the obvious, but amplify it in
  non-obvious ways (judging from the questions I've gotten).

This should un-break older laptops that still have to use PCIBIOS to route
interrupts.

Tested by: sam
2002-11-02 22:35:24 +00:00
Warner Losh
984de797ff Use 0xffffffff instead of -1 for id to compare against.
Use exact width types, since this is a MD file and won't be used elsewhere.
Fix a couple of resulting printf breakages

Bug found by: phk using Flexlint
2002-11-02 22:32:04 +00:00
Warner Losh
ea5420299c o go ahead and route the interupt, even if it is supposedly unique.
there are some strange machines that seem to need this.
o delete bogus comment.
o don't use the the bios for read/writing config space.  They interact badly
  with SMP and being called from ISR.  This brings -current in line with
  -stable.

# make the latter #ifdef on USE_PCI_BIOS_FOR_READ_WRITE in case we
# need to go back in a hurry.
2002-10-07 05:15:05 +00:00
Poul-Henning Kamp
cb8e433232 Don't call function in return() for a void function. 2002-09-28 17:36:29 +00:00
John Baldwin
8ff25e9763 Put verbose printf's in the PCI BIOS interrupt routing code under
if (bootverbose).
2002-09-23 18:13:42 +00:00
John Baldwin
fe4663379e Axe unused include. 2002-09-20 19:16:41 +00:00
John Baldwin
fefe985dc6 Make sure a $PIR table header has a valid length before accepting the table
as valid.

Submitted by:	Michal Mertl <mime@traveller.cz>
2002-09-09 18:24:35 +00:00
John Baldwin
c3ba1376f5 Add a function pci_probe_route_table() that returns true if our PCI BIOS
supports interrupt routing and if the specified PCI bus is present in the
routing table.
2002-09-06 22:15:44 +00:00
John Baldwin
facfd6e8ed Dump the $PIR table if booting verbose. 2002-09-06 19:25:25 +00:00
John Baldwin
8ab96fd8d0 - Add a pci_cfgintr_valid() function to see if a given IRQ is a valid
IRQ for an entry in a PCIBIOS interrupt routing ($PIR) table.
- Change pci_cfgintr() to except the current IRQ of a device as a fourth
  argument and to use that IRQ for the device if it is valid.
- If an intpin entry in a $PIR entry has a link of 0, it means that that
  intpin isn't connected to anything that can trigger an interrupt.  Thus,
  test the link against 0 to find invalid entries in the table instead of
  implicitly relying on the irqs field to be zero.  In the machines I have
  looked at, intpin entries with a link of 0 often have the bits for all
  possible interrupts for PCI devices set.
2002-09-06 17:08:07 +00:00
John Baldwin
fbabd7bec2 Add support for printing out the contents of a PCI BIOS $PIR interrupt
routing table on the console.  Eventually it will be printed during
verbose boots.
2002-09-06 16:10:12 +00:00
John Baldwin
5264a94f3f Test PCIbios.ventry against 0 to see if we found a PCIbios entry point,
not the 'entry' member.  The entry point is formed from both a base and
a relative entry point.  'entry' is that relative offset.  It is perfectly
valid to have an entry point with a relative offset of 0.  PCIbios.ventry
is the virtual address of the entry point that takes both 'base' and
'entry' into account, thus it is the proper variable to test to see if we
have an entry point or not.
2002-09-05 17:07:07 +00:00
Warner Losh
e300f53ca2 style(9)ize the whole file
Approved in concept a long time ago by: msmith
2002-07-21 05:35:42 +00:00
Warner Losh
8ce1ab3a24 Use a common function to map the bogus intlines.
Don't require pin be non-zero before we map bogus intlines, always do it.
This fixes a number of problems on HP Omnibook computers.

Tested/Reviewed by: Brooks Davis
2002-06-01 05:14:11 +00:00
Brooks Davis
26722a1909 Restore the irq=0 => irq=255 hack to pci_cfgintr_search(). Just having
it in pci_cfgregread() wasn't sufficent on at least the HP Omnibook 500.

Reviewed by:	imp
2002-05-29 16:16:16 +00:00
Warner Losh
d5ccecfad7 o Work around bugs in the powerof2 macro: It thinks that 0 is a power of
2, but that's not the case.  This fixes the case where there were slots
  in the PIR table that had no bits set, but we assumed they did and used
  strange results as a result.
o Map invalid INTLINE registers to 255 in pci_cfgreg.c.  This should allow
  us to remove the bogus checks in MI code for non-255 values.

I put these changes out for review a while ago, but no one responded
to them, so into current they go.

This should help us work better on machines that don't route
interrupts in the traditional way.

MFC After: 4286 millifortnights
2002-04-24 15:30:11 +00:00
Warner Losh
654d58ca24 Don't call the bios if the interrupt appaers to be already routed. Some
older PCI BIOSes hate this and this leads to panics when it is done.  Also,
assume that a uniquely routed interrupt is already routed.  This also
seems to help some older laptops with feable BIOSes cope.
2002-03-16 23:02:41 +00:00
Warner Losh
a8c18609ec The Libretto L series has no $PIR table, but does have a _PIR table.
This typo keeps us from properly routing an interrupt for CardBus
bridges on this machine.  So, now we look for $PIR and then _PIR to
cope.  With these changes, the Libretto L1 now works properly.
Evidentally, the idea comes from patch that the Japanese version of
RedHat (or against a Japanese version of Red Hat), but my Japanese
isn't good enough to to know for sure.

Reported by: Hiroyuki Aizu-san <eyes@navi.org>

# This may be an MFC candidate, but I'm not yet sure.
2002-01-20 03:28:29 +00:00
Warner Losh
1cf5f5552b MFS: I was confused. This code wasn't in -current after all.
Merge in the irq 0 detection.  Add comment about why.

If we have irq 0, ignore it like we do irq 255.  Some BIOS writers aren't
careful like they should be.
2001-11-26 21:25:03 +00:00
Warner Losh
d3b6477a19 It turns out that while Toshiba laptops don't want to route interrupts
multiple times, others do.  The last strategy, which was to assume
that already routed interrupts were good and just return them doesn't
work for some laptops.  So, instead, we have a new strategy: we notice
that we have an interrupt that's already routed.  We go ahead and try
to route it, none the less.  We will assume that it is correctly
routed, even if the route fails.  We still assume that other failures
in the bios32 call are because the interrupt is NOT routed.

Note: some laptops do not support the bios32 interface to PCI BIOS and
we need to call it via the INT 2A interface.  That is another windmill
to till at later.

Also correct a minor typo and minor whitespace nits.

Strong MFC candidate.
2001-08-28 16:35:01 +00:00
Warner Losh
d626906b0c MFS: IRQ ordering, PRVERB and more whining in pcibios_get_version on failure.
Check return value from bios32.

[[ Yes, I was bad and committed this to stable first.  I should have done
   the commit in the other order. ]]
2001-08-27 20:44:38 +00:00
Warner Losh
0b9427de88 The general conesnsus on irc was that pci bios for config registers
and such was just a bad idea and one that users should be forced to
enable if they want it.  This patch introduces a hw.pci.enable_pcibios
tunable for those people.  This does not impact the pcibios interrupt
routing at all.

Approved by: peter, msmith
2001-08-21 07:53:37 +00:00
Peter Wemm
573be82757 Detect a certain type of PCIBIOS brain damage. For some reason,
some bios vendors took it apon themselves to "censor" the
host->pci bridges from PCIBIOS callers, even when the caller
explicitly asks for them.  This includes certain Compaq machines
(eg: DL360) and some laptops.

If we detect this, shut down pcibios and revert to using IO
port bashing.

Under -current, apcica does a better job anyway.
2001-08-21 03:10:55 +00:00
Mike Smith
85fab96387 Un-swap irq/link byte values so that printf works. 2001-05-11 04:52:29 +00:00
Mike Smith
6c9eb5f3a6 Free the memory we get from devclass_get_devices and device_get_children.
Submitted by:	wpaul
2001-02-08 20:44:49 +00:00
Peter Wemm
47c6b72621 Fix a warning due to missing prototype. 2001-01-19 09:10:14 +00:00
Bosko Milekic
6a47d852b9 Remove declaration of airq variable from outer block. There were two
declarations of a variable of the same name. The one in the outer block
was unused and probably just slipped in at one point or another. This
silences a compiler warning.
2001-01-12 07:49:29 +00:00
Mike Smith
bb0d0a8efc Next phase in the PCI subsystem cleanup.
- Move PCI core code to dev/pci.
 - Split bridge code out into separate modules.
 - Remove the descriptive strings from the bridge drivers.  If you
   want to know what a device is, use pciconf.  Add support for
   broadly identifying devices based on class/subclass, and for
   parsing a preloaded device identification database so that if
   you want to waste the memory, you can identify *anything* we know
   about.
 - Remove machine-dependant code from the core PCI code.  APIC interrupt
   mapping is performed by shadowing the intline register in machine-
   dependant code.
 - Bring interrupt routing support to the Alpha
   (although many platforms don't yet support routing or mapping
   interrupts entirely correctly).  This resulted in spamming
   <sys/bus.h> into more places than it really should have gone.
 - Put sys/dev on the kernel/modules include path.  This avoids
   having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
Mike Smith
099d058b54 Improve the PCI interrupt routing code. Now the process is as follows:
- Look for a hardwired interrupt in the routing table for this
   bus/device/pin (we already did this).
 - Look for another device with the same link byte which has a hardwired
   interrupt.
 - Look for a PCI device matching an entry with the same link byte
   which has already been assigned an interrupt, and use that.
 - Look for a routable interrupt listed in the "PCI only" interrupts
   field and use that.
 - Pick the first interrupt that's marked as routable and use that.
2000-11-02 00:37:45 +00:00