Commit Graph

372 Commits

Author SHA1 Message Date
Andrew Turner
59c3cb81c1 Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2016-04-15 16:05:41 +00:00
Stanislav Galabov
915c6043b0 Make NIRQ configurable for MIPS
Submitted by:	kan
Reviewed by:	kan
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5964
2016-04-15 15:44:02 +00:00
Stanislav Galabov
a82ccc6f1e Define PCI_RES_BUS for MIPS.
This is done as part of the work on D5908, but as a separate commit.

Approved by:	adrian (mentor)
Sponsored by:	Smartcom - Bulgaria AD
2016-04-12 07:18:48 +00:00
Konstantin Belousov
90edf67ecf POSIX states that #include <signal.h> shall make both mcontext_t and
ucontext_t available.  Our code even has XXX comment about this.

Add a bit of compliance by moving struct __ucontext definition into
sys/_ucontext.h and including it into signal.h and sys/ucontext.h.

Several machine/ucontext.h headers were changed to use namespace-safe
types (like uint64_t->__uint64_t) to not depend on sys/types.h.
struct __stack_t from sys/signal.h is made always visible in private
namespace to satisfy sys/_ucontext.h requirements.

Apparently mips _types.h pollutes global namespace with f_register_t
type definition.  This commit does not try to fix the issue.

PR:	207079
Reported and tested by:	Ting-Wei Lan <lantw44@gmail.com>
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
2016-02-12 07:38:19 +00:00
Adrian Chadd
67a2f29041 Missing commit - remove MIPS fdt bus space.
Differential Revision:	https://reviews.freebsd.org/D5184
2016-02-11 06:19:58 +00:00
Adrian Chadd
7519c628d3 Remove bus space fdt for MIPS.
This was originall done by kan@.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan
Differential Revision:	https://reviews.freebsd.org/D5184
2016-02-11 06:19:32 +00:00
Adrian Chadd
9a8d0c1f0c Begin the MIPS_INTRNG support.
This is a prelude to intr-ng support for MIPS boards that need it -
notably the CI20 port from kan@ that's upcoming, but also work that
Stanislav is doing for the Mediatek platforms.

This is the initial platform dependent bits in include/intr.h, some
#defines for the nexus code for the intrng initialisation/runtime
bits, some changed naming (which I'll fix later to be the same, much
like what I did for ARM intr-ng) in exception.S, and the first cut
at a PIC.

Stanislav and I refactored out the common code for intrng support,
so the mips intrng definitions are quite small (sys/mips/include/intr.h.)

This is all work done by kan@, which stanislav has been cherry picking
into common code for his mediatek chipset work.

Tested:

* Carambola2 - no regressions (not intr-ng though!)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan (original author)
Differential Revision:	https://reviews.freebsd.org/D5182
2016-02-11 06:09:27 +00:00
Adrian Chadd
56f9ec0685 Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for
clearing hazards.

This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use
the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K
 (somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to
this list.

Also, for the cases of MIPS coherent processing systems (currently 1004K,
1074K, interAptiv and proAptiv) - define proper CCA attributes.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5078
2016-02-02 16:00:42 +00:00
Adrian Chadd
04b5e02371 Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options
This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K

It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV

CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.

I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5077
2016-02-02 07:47:38 +00:00
Brooks Davis
bd3f34d4ba Shift saved floating point registers up in jmp_buf.
sigmask_t is 128-bits so requires two slots.

Approved by:	CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
MFC after:	1 week
Sponsored by:	DARPA, AFRL
2016-01-20 22:23:08 +00:00
Adrian Chadd
d06ccd84b3 Begin the initial support for the mips1004kc core.
* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.

Tested:

* MT7621A SoC (not yet in-tree)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 15:52:21 +00:00
Adrian Chadd
7b61491a8d [mips] Add TLB pagemask probing code, and print out the allowable page sizes.
This is from Stacey's work on larger kernel stack sizes for MIPS.  Thanks!

Submitted by:	sson
2015-12-22 15:59:41 +00:00
Ian Lepore
f3be407b23 Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.h
is what includes machine/ofw_machdep.h.  Don't declare OF_decode_addr();
it isn't implemented yet on mips and the declaration for it is about to
be commonized into openfirm.h.
2015-12-20 19:09:12 +00:00
Alan Cox
c869e67208 Introduce a new mechanism for relocating virtual pages to a new physical
address and use this mechanism when:

1. kmem_alloc_{attr,contig}() can't find suitable free pages in the physical
   memory allocator's free page lists.  This replaces the long-standing
   approach of scanning the inactive and inactive queues, converting clean
   pages into PG_CACHED pages and laundering dirty pages.  In contrast, the
   new mechanism does not use PG_CACHED pages nor does it trigger a large
   number of I/O operations.

2. on 32-bit MIPS processors, uma_small_alloc() and the pmap can't find
   free pages in the physical memory allocator's free page lists that are
   covered by the direct map.  Tested by: adrian

3. ttm_bo_global_init() and ttm_vm_page_alloc_dma32() can't find suitable
   free pages in the physical memory allocator's free page lists.

In the coming months, I expect that this new mechanism will be applied in
other places.  For example, balloon drivers should use relocation to
minimize fragmentation of the guest physical address space.

Make vm_phys_alloc_contig() a little smarter (and more efficient in some
cases).  Specifically, use vm_phys_segs[] earlier to avoid scanning free
page lists that can't possibly contain suitable pages.

Reviewed by:	kib, markj
Glanced at:	jhb
Discussed with:	jeff
Sponsored by:	EMC / Isilon Storage Division
Differential Revision:	https://reviews.freebsd.org/D4444
2015-12-19 18:42:50 +00:00
Warner Losh
14f4e15704 Correct the CONFIG0_VI value. According to
http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the
config0 word, not bit 2.  This should fix virtually indexed caches
(relatively new in the MIPS world, so no current platforms used this
and current code just uses it as an optimization). It was causing
false positives on newer platforms that default to large values for
the kseg0 cache coherency attribute.

Submitted by: Stanislav Galabov
PR:	205249
2015-12-11 16:51:04 +00:00
Adrian Chadd
941f53b9a9 mips74k: use cache-writeback for memory, not writethrough.
When I ported this code from netbsd I was .. slightly mips74k greener.
I used writethrough because (a) it's what netbsd did, and (b) if I used
writethrough then things "didn't work."

Fast-forward a couple years, more MIPS hacking and a whole lot more
understanding of the bus APIs (the last few commits notwithstanding;
it's been a long week, ok?) and I have this working for arge,
argemdio, spi and ath.  Hans has it working for USB.  The ath barrier
code will come in a later commit.

This gets the routing throughput up from 220mbit -> 337mbit.
I'm sure the bridging throughput will be similarly improved.

Tested:

* QCA955x SoC, routing workload.
2015-10-31 00:04:44 +00:00
Ian Lepore
f4110e9110 Switch from a stub to a real implementation of pmap_page_set_attr() for mips,
and implement support for VM_MEMATTR_UNCACHEABLE.  This will be used in
upcoming changes to support BUS_DMA_COHERENT in bus_dmamem_alloc().

Reviewed by:	adrian, imp
2015-10-21 14:57:59 +00:00
Ed Maste
fc8c856029 Rationalize BSD license on sys/*/include/in_cksum.h
Remove the advertising clause from the Regents of the University of
California's license, per the letter dated July 22, 1999.

Update clause numbering.
2015-08-05 19:05:12 +00:00
Ed Maste
96226a9aa7 Rationalize BSD license on sys/*/include/float.h
Remove the advertising clause from the Regents of the University of
California's license, per the letter dated July 22, 1999.

Update clause numbering.
2015-08-05 17:05:35 +00:00
Konstantin Belousov
8954a9a4e6 Add the atomic_thread_fence() family of functions with intent to
provide a semantic defined by the C11 fences with corresponding
memory_order.

atomic_thread_fence_acq() gives r | r, w, where r and w are read and
write accesses, and | denotes the fence itself.

atomic_thread_fence_rel() is r, w | w.

atomic_thread_fence_acq_rel() is the combination of the acquire and
release in single operation.  Note that reads after the acq+rel fence
could be made visible before writes preceeding the fence.

atomic_thread_fence_seq_cst() orders all accesses before/after the
fence, and the fence itself is globally ordered against other
sequentially consistent atomic operations.

Reviewed by:	alc
Discussed with:	bde
Sponsored by:	The FreeBSD Foundation
MFC after:	3 weeks
2015-07-08 18:12:24 +00:00
Alan Cox
966272ca33 Retire VM_FREEPOOL_CACHE as the next step in eliminating PG_CACHE pages.
Differential Revision:	https://reviews.freebsd.org/D2712
Reviewed by:	kib
Sponsored by:	EMC / Isilon Storage Division
2015-06-08 04:59:32 +00:00
Bjoern A. Zeeb
b748af7305 Similarly to other architecture, add the include for cpufunc.h which is
needed for pte.h by vmstat to resolve MIPS_CCA_UNCACHED.
2015-05-28 12:33:21 +00:00
Adrian Chadd
623d2d40af Increment the vm stats "v_intr" counter so the global system interrupt
statistics work again.

I'm not sure why/when this broke, only that it used to work fine.

This commit is brought to you by Maker Faire Bay Area 2015.
2015-05-16 23:51:24 +00:00
John Baldwin
dbee5c671a Move the 32-bit compatible procfs types from freebsd32.h to <sys/procfs.h>
and export them to userland.
- Define __HAVE_REG32 on platforms that define a reg32 structure and check
  for this in <sys/procfs.h> to control when to export prstatus32, etc.
- Add prstatus32_t and prpsinfo32_t typedefs for the 32-bit structures.
  libbfd looks for these types, and having them fixes 'gcore' in gdb of a
  32-bit process on a 64-bit platform.
- Use the structure definitions from <sys/procfs.h> in gcore's elf32 core
  dump code instead of duplicating the definitions.

Differential Revision:	https://reviews.freebsd.org/D2142
Reviewed by:	kib, nathanw (powerpc bits)
MFC after:	1 week
2015-04-08 16:30:45 +00:00
Ruslan Bukin
0276459325 Add 64 byte linesize cache flushing routines for L1 instruction, L1 data
and L2 data caches.

Sponsored by:	HEIF5
2015-03-26 14:51:24 +00:00
Ruslan Bukin
fd3276de58 Add 128-byte cache flushing routines.
Leave CNMIPS untouched as these functions depends on config2
register.
2015-01-20 11:10:25 +00:00
Mark Johnston
bdb9ab0dd9 Factor out duplicated code from dumpsys() on each architecture into generic
code in sys/kern/kern_dump.c. Most dumpsys() implementations are nearly
identical and simply redefine a number of constants and helper subroutines;
a generic implementation will make it easier to implement features around
kernel core dumps. This change does not alter any minidump code and should
have no functional impact.

PR:		193873
Differential Revision:	https://reviews.freebsd.org/D904
Submitted by:	Conrad Meyer <conrad.meyer@isilon.com>
Reviewed by:	jhibbits (earlier version)
Sponsored by:	EMC / Isilon Storage Division
2015-01-07 01:01:39 +00:00
Ed Maste
942c32333e Update ELF headers to include additional defines
The elftoolchain project includes these additional defines for various
userland programs. Given that arch-specific defines are still interesting
in the context of userland programs reading or writing ELF metadata, they
should be included in top-level ELF headers.

Remove duplicate defines from ARM and MIPS elf headers.

Submitted by:	will (initial version)
Reviewed by:	imp, will
Sponsored by:	The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D844
2015-01-02 15:36:29 +00:00
Alan Cox
d866a563d4 The physical memory allocator supports the use of distinct free lists for
managing pages from different address ranges.  Generally speaking, this
feature is used to increase the likelihood that physical pages are
available that can meet special DMA requirements or can be accessed through
a limited-coverage direct mapping (e.g., MIPS).  However, prior to this
change, the configuration of the free lists was static, i.e., it was
determined at compile time.  Consequentally, free lists could be created
for address ranges that held no actual pages, for example, on 32-bit MIPS-
based systems with 512 MB or less of physical memory.  This change makes
the creation of the free lists dynamic, i.e., it is based on the available
physical memory at boot time.

On 64-bit x86-based systems with 64 GB or more of physical memory, create
free lists for managing pages with physical addresses below 4 GB.  This
change is to address reported problems with initializing devices that
require the allocation of physical pages below 4 GB on some systems with
128 GB or more of physical memory.

PR:		185727
Differential Revision:	https://reviews.freebsd.org/D1274
Reviewed by:	jhb, kib
MFC after:	3 weeks
Sponsored by:	EMC / Isilon Storage Division
2014-12-31 00:54:38 +00:00
Ruslan Bukin
4cf0a674c0 Correct the functions declaration. 2014-11-23 22:09:05 +00:00
Brooks Davis
1e7bf26b33 Add FPU support for MIPS setjmp(3)/longjmp(3).
This change saves/restores the callee-saved MIPS floating point
registers as documented by the o32/n32/n64 spec ("MIPSpro N32
ABI Handbook", Table 2-1) for the _setjmp(3), _longjmp(3),
setjmp(3) and longjmp(3) C library functions.  This is only
included when the C library is built with hardware floating point
support (or when "SOFTFLOAT" is not defined).

Submitted by:	sson
MFC after:	1 month
Sponsored by:	DARPA, AFRL
2014-11-21 20:02:06 +00:00
Ruslan Bukin
209fe5ef9a Add L2-cache writeback/flush operations. Supported 32,128-byte line-size,
else ignored. Cavium Networks also ignored as it has non-standard config
registers.

Obtained from:	NetBSD
Sponsored by:	DARPA, AFRL
2014-11-20 17:06:41 +00:00
Konstantin Belousov
4f3dc90023 Add fueword(9) and casueword(9) functions. They are like fuword(9)
and casuword(9), but do not mix value read and indication of fault.

I know (or remember) enough assembly to handle x86 and powerpc.  For
arm, mips and sparc64, implement fueword() and casueword() as wrappers
around fuword() and casuword(), which means that the functions cannot
distinguish between -1 and fault.

On architectures where fueword() and casueword() are native, implement
fuword() and casuword() using fueword() and casuword(), to reduce
assembly code duplication.

Sponsored by:	The FreeBSD Foundation
Tested by:	pho
MFC after:	2 weeks (ia64 needs treating)
2014-10-28 15:22:13 +00:00
Mark Johnston
5eaae1411f Pass up the error status of minidumpsys() to its callers.
PR:		193761
Submitted by:	Conrad Meyer <conrad.meyer@isilon.com>
Sponsored by:	EMC / Isilon Storage Division
2014-10-08 20:25:21 +00:00
Gleb Smirnoff
0abfc519b4 style(9) 2014-09-07 05:47:48 +00:00
Adrian Chadd
89a4f450d7 Implement local sfbuf_map and sfbuf_unmap for MIPS32.
The pre-rework behaviour was not to keep the cached mappings around after
the sfbuf was used but instead to recycle said mappings.

PR:		kern/193400
2014-09-06 22:38:32 +00:00
Gleb Smirnoff
c8d2ffd6a7 Merge all MD sf_buf allocators into one MI, residing in kern/subr_sfbuf.c
The MD allocators were very common, however there were some minor
differencies. These differencies were all consolidated in the MI allocator,
under ifdefs. The defines from machine/vmparam.h turn on features required
for a particular machine. For details look in the comment in sys/sf_buf.h.

As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have
machine/sf_buf.h, which is usually quite small.

Tested by:	glebius (i386), tuexen (arm32), kevlo (arm32)
Reviewed by:	kib
Sponsored by:	Netflix
Sponsored by:	Nginx, Inc.
2014-08-05 09:44:10 +00:00
Marcel Moolenaar
8bf2af7fc9 Add missing definition of ELF_MACHINE_OK, now used by gcore(1). 2014-07-26 18:52:23 +00:00
Tijl Coosemans
0a4c54d606 Rename __wchar_t so it no longer conflicts with __wchar_t from clang 3.4
-fms-extensions.

MFC after:	2 weeks
2014-04-01 14:46:11 +00:00
Ed Maste
0fcefb433d Update NetBSD Foundation copyrights to 2-clause BSD
The NetBSD Foundation states "Third parties are encouraged to change the
license on any files which have a 4-clause license contributed to the
NetBSD Foundation to a 2-clause license."

This change removes clauses 3 and 4 from copyright / license blocks that
list The NetBSD Foundation as the only copyright holder.

Sponsored by:	The FreeBSD Foundation
2014-03-18 01:40:25 +00:00
Robert Watson
a02a14d1a6 Update MIPS bootinfo.h to reflect the actual MIPS boot2/loader boot-time
interface.

MFC after:	3 weeks
Sponsored by:	DARPA, AFRL
2014-02-19 09:19:09 +00:00
Nathan Whitehorn
dcd08302e5 Retire machine/fdt.h as a header used by MI code, as its function is now
obsolete. This involves the following pieces:
- Remove it entirely on PowerPC, where it is not used by MD code either
- Remove all references to machine/fdt.h in non-architecture-specific code
  (aside from uart_cpu_fdt.c, shared by ARM and MIPS, and so is somewhat
  non-arch-specific).
- Fix code relying on header pollution from machine/fdt.h includes
- Legacy fdtbus.c (still used on x86 FDT systems) now passes resource
  requests to its parent (nexus). This allows x86 FDT devices to allocate
  both memory and IO requests and removes the last notionally MI use of
  fdtbus_bs_tag.
- On those architectures that retain a machine/fdt.h, unused bits like
  FDT_MAP_IRQ and FDT_INTR_MAX have been removed.
2014-01-05 18:46:58 +00:00
Alan Cox
c70af4875e As of r257209, all architectures have defined VM_KMEM_SIZE_SCALE. In other
words, every architecture is now auto-sizing the kmem arena.  This revision
changes kmeminit() so that the definition of VM_KMEM_SIZE_SCALE becomes
mandatory and the definition of VM_KMEM_SIZE becomes optional.

Replace or eliminate all existing definitions of VM_KMEM_SIZE.  With
auto-sizing enabled, VM_KMEM_SIZE effectively became an alternate spelling
for VM_KMEM_SIZE_MIN on most architectures.  Use VM_KMEM_SIZE_MIN for
clarity.

Change kmeminit() so that the effect of defining VM_KMEM_SIZE is similar to
that of setting the tunable vm.kmem_size.  Whereas the macros
VM_KMEM_SIZE_{MAX,MIN,SCALE} have had the same effect as the tunables
vm.kmem_size_{max,min,scale}, the effects of VM_KMEM_SIZE and vm.kmem_size
have been distinct.  In particular, whereas VM_KMEM_SIZE was overridden by
VM_KMEM_SIZE_{MAX,MIN,SCALE} and vm.kmem_size_{max,min,scale}, vm.kmem_size
was not.  Remedy this inconsistency.  Now, VM_KMEM_SIZE can be used to set
the size of the kmem arena at compile-time without that value being
overridden by auto-sizing.

Update the nearby comments to reflect the kmem submap being replaced by the
kmem arena.  Stop duplicating the auto-sizing formula in every machine-
dependent vmparam.h and place it in kmeminit() where auto-sizing takes
place.

Reviewed by:	kib (an earlier version)
Sponsored by:	EMC / Isilon Storage Division
2013-11-08 16:25:00 +00:00
Brooks Davis
dd2f74a820 MFP4:
Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30

        FreeBSD/mips stores page-table entries in a near-identical format
        to MIPS TLB entries -- only it overrides certain "reserved" bits
        in the MIPS-defined EntryLo register to hold software-defined bits
        (swbits) to avoid significantly increasing the page table memory
        footprint.  On n32 and n64, these bits were (a) colliding with
        MIPS64r2 physical memory extensions and (b) being improperly
        cleared.

        Attempt to fix both of these problems by pushing swbits further
        along 64-bit EntryLo registers into the reserved space, and
        improving consistency between C-based and assembly-based clearing
        of swbits -- in particular, to use the same definition.  This
        should stop swbits from leaking into TLB entries -- while ignored
        by most current MIPS hardware, this would cause a problem with
        (much) larger physical memory sizes, and also leads to confusing
        hardware-level tracing as physical addresses contain unexpected
        (and inconsistent) higher bits.

        Discussed with: imp, jmallett

Change 1187301 by brooks@brooks_zenith on 2013/10/23 14:40:10
        Loop back the initial commit of 221534 to HEAD.  Correct its
        implementation for mips32.

MFC after:	3 days
Sponsored by:	DARPA/AFRL
2013-10-23 21:35:39 +00:00
Brooks Davis
0e902f8a24 Revert r256934, it needs work to build on mips32. 2013-10-23 13:32:52 +00:00
Brooks Davis
f66834b69a MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM

MFC after:	3 days
Sponsored by:	DAPRA/AFRL
2013-10-22 21:08:25 +00:00
Brooks Davis
cf193ef13e MFP4:
Change 221534 by rwatson@rwatson_zenith_cl_cam_ac_uk on 2013/01/27 16:05:30

        FreeBSD/mips stores page-table entries in a near-identical format
        to MIPS TLB entries -- only it overrides certain "reserved" bits
        in the MIPS-defined EntryLo register to hold software-defined bits
        (swbits) to avoid significantly increasing the page table memory
        footprint.  On n32 and n64, these bits were (a) colliding with
        MIPS64r2 physical memory extensions and (b) being improperly
        cleared.

        Attempt to fix both of these problems by pushing swbits further
        along 64-bit EntryLo registers into the reserved space, and
        improving consistency between C-based and assembly-based clearing
        of swbits -- in particular, to use the same definition.  This
        should stop swbits from leaking into TLB entries -- while ignored
        by most current MIPS hardware, this would cause a problem with
        (much) larger physical memory sizes, and also leads to confusing
        hardware-level tracing as physical addresses contain unexpected
        (and inconsistent) higher bits.

        Discussed with: imp, jmallett

MFC after:	3 days
Sponsored by:	DARPA/AFRL
2013-10-22 21:06:27 +00:00
Warner Losh
0013199a74 Elminate NON_LEAF and use NESTED instead to unify our assembler
conventions.

Reviewed by:	jmallet@
2013-10-15 04:45:09 +00:00
Warner Losh
10eb94556e Replace NLEAF with LEAF_NOPROFILE to unify the conventions we use in
our assembler files.

Reviewed by:	jmallet@
2013-10-15 04:44:21 +00:00
Warner Losh
f7cad617a1 Replace uses of the ALEAF macro with XLEAF and remove ALEAF macro to
try to unify the conventions used in our assembler.

Reviewed by:	jmallet@
2013-10-15 04:43:31 +00:00