Commit Graph

18 Commits

Author SHA1 Message Date
Justin T. Gibbs
41c47eee15 Simplify my copyright license terms.
aic7xxx.c:
	Add a function for sucking firmware out of the controller
	prior to reset.

	Remove some inline bloat from functions that should not have
	been inlined.

	During initialization, wait 1ms after the chip reset before
	touching any registers.  You can get machine checks on certain
	architectures (Atari I think?) without the delay.

	Return CAM_REQ_CMP for external BDR requests instead
	of CAM_BDR_SENT.

	Bump some messages to bootverbose levels above 1.

	Don't clear any negotiated sync rate if the target rejects
	a WDTR message.  The sync rate is only cleared if the target
	accepts a WDTR message.

	Fix a small bug in the mesgin handling code that could cause
	us to believe that we had recieved a message that was actually
	received by another target.  This could only confuse us in
	some very rare transmission negotiation scenarios.

	Remove some unecessary cleanup of residual information after
	a residual is reported.  The sequencer does this when the
	command is queued now.
1999-12-06 18:23:31 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Justin T. Gibbs
42aed36923 Kill an unused INTSTAT type. 1999-08-16 22:43:08 +00:00
Justin T. Gibbs
06d2b844cc Better workaround for aic7890 chip bug. Use the HS_MAILBOX register to
tell the sequencer to pause itself for a target msg variable update.  This
avoids the pause race entirely as HS_MAILBOX can be accessed without
pausing the chip.

3.2 Merge candidate.
1999-05-14 05:07:25 +00:00
Justin T. Gibbs
1ab33b7b83 Clean up and order register definitions. 1999-03-08 22:43:23 +00:00
Justin T. Gibbs
c562189829 Keep track of negotiated transfer parameters for each initiator<->target
connection.

Clean up support for devices featuring the multiple target SCSI ID feature.
On aic7890/91/96/97 chips, we can now assume the target role on multiple
target ids simultaneously.  Although these chips also have sufficient
instruction space to hold to support the initiator and target role at the
same time, the initiator role is currently disabled as it will conflict
(chip design restriction) with the multi-tid feature.  I'll probably add
a nob to enable the initiator (there-by disabling multi-tid) some time
in the future.

Return queue full or busy, depending on the tagged nature of the incoming
request, if our command input queue fills up in host memeory.

Deal with accept target I/O resource shortages.

If we get an underrun on a transaction that wasn't supposed to transmit
any data, don't attempt to print out the S/G list.  The code would
run until hitting a non-present page. (oops)
1999-03-05 23:35:48 +00:00
Justin T. Gibbs
863c602654 Add support for routing initiator transactions to disabled luns to the
black hole device.  The controller will now only accept selections if
the black hole device is present and some other target/lun is enabled
for target mode.

Handle the IGNORE WIDE RESIDUE message.  This support has not been tested.

Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS,
and CLEAR QUEUE messages as a target.

Fix a few problems with tagged command handling in target mode.

Wait until the sync offset counter falls to 0 before changing phase
after a data-in transfer completes as the DMA logic seems to indicate
transfer complete as soon as our last REQ is issued.

Simplify some of the target mode message handling code in the sequencer.
1999-01-14 06:14:15 +00:00
Justin T. Gibbs
0378c40c5c Fix a few problems with handling rejected transfer negotiation messages.
Use the host message loop for any unknown message types instead of performing
a reject message in the sequencer.  Pass reject messages to the host
message loop too which frees up a sequencer interrupt type slot.

Default to issuing a bus reset if initiator mode is enabled.  It seems
that the reset scsi bus bit is not defined in the same location for
all aic78xx BIOSes, so attempting to honor this setting will have to
wait until I get more information on how to detect it.

Nuke some unused variables.
1998-12-17 00:06:52 +00:00
Justin T. Gibbs
0ca48af774 Perform a save data pointers operation if a data transfer was performed
in target mode, but we are not completing the command.

Use a template of allowed bus arbitration phases to selectively and
dynamically enable/disable initiator or target (re)selection.

Properly handle timeouts for target role transactions - just go to the
bus free state and report the error to the peripheral driver.

Checkpoint support for the XPT_ABORT_CCB function code.  This currently
handles the accept tio and immediate notify ccb types, but does not
handle the continue target I/O or SCSI I/O ccb types.  This is enough
to handle dynamic target enable/disable events.

Clean up the SCSI reset code so that we perform at most 1 SCSI bus
reset at initialization, the reset requested by the XPT layer.
1998-12-15 08:22:42 +00:00
Justin T. Gibbs
4dd5dcaecd Revamp the way that exceptional message handling is performed so that it
is more robust and common code can be used for both the target and iniator
roles.  The mechanism for tracking negotiation state has also been simplified.

Add support for sync/wide negotiation in target mode and fix many of
the target mode bugs running at higher speeds uncovered.  Make a first
stab at getting all of the bus skew delays correct.  Sync+Wide dataout
transfers still cause problems, but this may be an initiator problem.

Ensure that we exit BITBUCKET mode if the controller is restarted.

Add support for target mode only firmware downloads.  This has been
tested on the aic7880, but should mean that we can perform target mode
on any aic7xxx controller.  Mixed mode (initiator and target roles in
the same firmware load) is currently only supported on the aic7890, but
with optimization, may fit on chips with less instruction space.
1998-12-10 04:14:50 +00:00
Justin T. Gibbs
08c6fbfa40 Change the delivery mechanism for incoming target commands. We now
use a 256 entry ring buffer of descriptersfor this purpose.  This allows
the use of a simple 8bit counter in the sequencer code for tracking start
location.

Entries in the ring buffer now contain a "cmd_valid" byte at their tail.
As an entry is serviced, this byte is cleared by the kernel and set by
the sequencer during its dma of a new entry.  Since this byte is the last
portion of the command touched during a dma, the kernel can use this
byte to ensure the command it processes is completely valid.

The new command format requires a fixed sized DMA from the controller
to deliver which allowed for additional simplification of the sequencer
code.  The hack that required 1 SCB slot to be stolen for incoming
command delivery notification is also gone.
1998-11-23 01:33:47 +00:00
Justin T. Gibbs
3bafc9d432 Massive overhaul of the aic7xxx driver:
- Convert to CAM
 - Use a new DMA based queuing and paging scheme
 - Add preliminary target mode support
 - Add support for the aic789X chips
 - Take advantage of external SRAM on more controllers.
 - Numerous bug fixes and performance improvements.
1998-09-15 07:24:17 +00:00
Justin T. Gibbs
37507c1bd2 Add support to aicasm for "downloaded constants". These are immediate
operands that are set during seqeuncer program download instead of at
assembly time.

Convert the sequencer code to use" downloaded constants" for four run time
constants that vary depending on the board type.  This frees up 4 bytes
of sequencer scratch ram space where these constants used to be stored and
also removes the additional instructions required to load their values
into the accumulator prior to using them.

Remove the REJBYTE sram variable.  The host driver can just as easly
read the accumulator to get this value.

The scratch ram savings is important as the old code used to clober the
SCSICONF register on 274X cards which sits near the top of scratch ram
space.  The SCSICONF register controls bus termination, and clobbering
it is not a good thing.  Now we have 4 bytes to spare.

This should fix the reported problems with cards that don't have devices
attached to them failing with a stream of "Somone reset bus X" messages.

Doug Ledford determined the cause of the problem, fixes by me.
1997-09-27 19:37:31 +00:00
Justin T. Gibbs
083bc8b2cc Add a spin lock that prevents the sequencer from attempting to add an
entry to the QOUTFIFO when it is full.  This should eliminate the
"Timed out while idle" problems that many have reported.

In truth, this is somewhat of a hack.  Although are interrupt latency is
low enough that we should be able to always service the queue in time,
since each entry must be passed up to the higher SCSI layer for what can
be a large amount of processing (perhaps even resulting in a new command
being queued) with interrupts disabled, we need this mechanism to avoid
overflow.  In the future, these additional tasks will be offloaded to a
software interrupt handler which should make this hack unnecessary.
1997-08-13 17:02:47 +00:00
Justin T. Gibbs
f68f348b20 Modify my copyright notice to allow the sequencer to be used with GPLed
software (aka Linux).

Fix a few bugs in the sequencer assembler.

Make it easy to compiler the assembler with debugging turned on.
1997-06-27 19:38:56 +00:00
Justin T. Gibbs
cd6867d0d3 The following scenario would result in a bogus residual being reported
if SCB Paging was enabled:

    disconnect with more data to transfer
    disconnected SCB gets paged out
    target reconnects so we page SCB back in
    target completes transfer so residual is 0
    target disconnects
    SCB gets reused but not paged out since the residual is 0 (optimization)
    target reconnects so we page the SCB back in
    we report a residual because of stale residual information.

The fix for this is to set a flag that forces the SCB to be paged back
up to the host if we page in an SCB with a residual

Pointed out by: Doug Ledford <dledford@dialnet.net>
1997-04-24 16:52:18 +00:00
Justin T. Gibbs
45b7cf8750 Re-arange the selection and reselection code to hopefully kill the
spurious selection timeouts that have been reported.
1997-04-14 02:26:59 +00:00
Justin T. Gibbs
c5cb388883 Makefile gram.y scan.l sequencer.h symbol.c symbol.h aic7xxx_asm.c:
New sequencer assembler for the aic7xxx adapters.  This assembler
	performs some amount of register type checking, allows bit
	manipulation of symbolic constants, and generates "patch tables"
	for conditionalized downloading of portions of the program.
	This makes it easier to take full advantage of the different
	features of the aic7xxx cards without imposing run time penalies
	or being bound to the small memory footprints of the low end
	cards for features like target mode.

aic7xxx.reg:
	New, assembler parsed, register definitions fo the aic7xxx cards.
	This was done primarily in anticipation of 7810 support which
	will have a different register layout, but should be able to use
	the same assembler.  The kernel aic7xxx driver consumes a generated
	file in the compile directory to get the definitions of the register
	locations.

aic7xxx.seq:
	Convert to the slighly different syntax of the new assembler.

	Conditionalize SCB_PAGING, ultra, and twin features which shaves
	quite a bit of space once the program is downloaded.

	Add code to leave the selection hardware enabled during reconnects
	that win bus arbitration.  This ensures that we will rearbitrate
	as soon as the bus goes free instead of delaying for a bit.

	When we expect the bus to go free, perform all of the cleanup
	associated with that event "up front" and enter a loop awaiting
	bus free.  If we see a REQ first, complain, but attempt to
	continue.  This will hopefully address, or at least help diagnose,
	the "target didn't send identify" messages that have been reported.

Spelling corrections obtained from NetBSD.
1997-03-16 07:08:19 +00:00