29 Commits

Author SHA1 Message Date
Alexander Motin
dd60e051f7 - Use mutex to serialize index/data register pair usage, when
accessing SATA registers. Unserialized access under heavy load caused
wrong speed reporting and potentially could cause device loss.
 - To free memory and other resources (including above), allocated
during chipinit() method call on attach, add new chipdeinit() method,
called during driver detach.

Submitted by:   Andrew Boyer <aboyer@averesystems.com> (initial version)
Approved by:	re (kib)
MFC after:	1 week
2011-07-22 16:37:04 +00:00
Alexander Motin
e292b310e9 Skip BAR(5) usage for SATA registers access on ICH8M Apples, because for
some reason it causes system lock up. Linux does the same.

MFC after:	1 week
2011-06-14 20:30:15 +00:00
Jack F Vogel
73e3bb6563 Chipset support for the new Intel Panther Point PCH, thanks
to Seth Heasley for preparing the changes.
2011-05-11 20:31:27 +00:00
Alexander Motin
c7dd7de64d According to ATA specifications, when ATAPI master is the only device, it
should respond with all zeroes to any access to slave registers. Test with
PATA devices confirmed such behavior. Unluckily, Intel SATA controllers in
legacy emulation mode behave differently, not making any difference between
ATA and ATAPI devices. It causes false positive slave device detection and,
as result, command timeouts.

To workaround this problem, mask result of legacy-emulated soft-reset with
the device presence information received from the SATA-specific registers.
2011-04-21 20:56:34 +00:00
Alexander Motin
53479021ba - Fix mapping of the last two SATA ports on 6-port Intel controllers.
This improves hard-reset and hot-plug on these ports.
 - Device with ID 0x29218086 is a 2-port variant of ICH9 in legacy mode.
Skip probing for nonexistent slave devices there.
2011-04-21 11:44:16 +00:00
Jack F Vogel
bf0477b215 Support for the new Patsburg PCH chipset:
- SMBus Controller
     - SATA Controller
     - HD Audio Controller
     - Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days
2011-02-01 01:05:11 +00:00
Jack F Vogel
d5267ede37 Support for the new DH89xxCC PCH chipset including:
- SATA controller
      - Watchdog timer
      - SMBus controller
2011-01-31 18:41:52 +00:00
Alexander Motin
f1bfc8aba8 ICH7 SATA controller in legacy mode can provide access to SATA registers
via AHCI-like memory resource at BAR(5). Use it if BIOS was so kind to
allocate memory for that BAR. This allows hot-plug support and connection
speed reporting.

MFC after:	2 weeks
2011-01-24 09:24:20 +00:00
Alexander Motin
82d2b37bc0 Remove stale line, accidentally slipped into r214016.
MFC after:	3 days
2010-11-02 09:31:24 +00:00
Alexander Motin
bda55b6adb Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.
2010-10-18 11:30:13 +00:00
Alexander Motin
bfc8500c34 Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.

Submitted by:	jfv@
MFC after:	1 week
2010-08-28 07:10:51 +00:00
Alexander Motin
aecfe194a9 If ata_sata_phy_reset() failed and ata_generic_reset() is not called, mark
channel as having no devices connected. This improves hot-unplug operation
on legacy-emulating SATA controllers.
2010-07-10 15:36:27 +00:00
Alexander Motin
9a9bce34f1 Make hw.ata.ata_dma_check_80pin tunable affect not only device side, but
also controller side cable checks. Make respective sysctl writable.

PR:		kern/143462
2010-07-10 13:46:14 +00:00
Alexander Motin
6ee9deb145 Fix PCH chipset IDs. They are 0x3bxx, not 0x3axx.
Pointy hat to:	me
2010-06-04 07:35:59 +00:00
Alexander Motin
41a11d8753 Oops! Wrong word order. :( 2010-02-22 17:34:35 +00:00
Alexander Motin
6f2c1316f0 Add Intel PCH SATA controller IDs. 2010-02-22 16:27:47 +00:00
Alexander Motin
7aab51b33e Add support for Intel SCH PATA controller.
PR:		kern/140251
2009-12-22 19:48:06 +00:00
Alexander Motin
066f913a94 MFp4:
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this options deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.

As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.atapi_dma tunable work again.

Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.

Submitted by:	nwitehorn (powerpc part)
2009-12-06 00:10:13 +00:00
Alexander Motin
301f81f0fb Release over-agressive WDMA0 mode timings as close to spec as chip can. 2009-11-22 12:19:50 +00:00
Alexander Motin
48a21eb99c Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
2009-11-22 11:17:31 +00:00
Alexander Motin
fb549e86e7 Add more ICH10 chip IDs.
Submitted by:	Dmitry S. Luhtionov <mitya@cabletv.dp.ua>
2009-11-09 09:27:09 +00:00
Alexander Motin
ebbb35ba70 MFp4:
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.
2009-10-31 13:24:14 +00:00
Alexander Motin
f95dcaae42 MFp4:
Reduce default PCI ATA drivers priorities from absolute to default,
to allow them been overriden. It was so before modularization.
2009-06-24 19:49:18 +00:00
Xin LI
db7da92301 According to Intel documentation (307013), 3Gbps mode is supported on
Desktop chipsets only for ICH7 series, so mark all ICH7M as ATA_SA150
instead of ATA_SA300.
2009-06-01 07:05:52 +00:00
Alexander Motin
9cf4fe2ebe Integrate user/mav/ata branch:
Add ch_suspend/ch_resume methods for PCI controllers and implement them
for AHCI. Refactor AHCI channel initialization according to it.

Fix Port Multipliers operation. It is far from perfect yet, but works now.
Tested with JMicron JMB363 AHCI + SiI 3726 PMP pair.
Previous version was also tested with SiI 4726 PMP.

Hardware sponsored by: Vitsch Electronics / VEHosting.nl
2009-03-30 22:18:38 +00:00
Robert Noland
9373e7bb61 Remove the local management of INTx as this is now taken care of by pci.
Reviewed by:	jhb
MFC after:	3 days
2009-03-04 18:25:39 +00:00
Alexander Motin
78d154163c Quite mechanical ch_detach implementations for all atapci subdrivers.
Some dmainit call fixes for previous commit.
2009-02-19 00:32:55 +00:00
Alexander Motin
04ff88ceac As soon as they called in only same one place (ata_pcichannel_attach()),
join allocate() and dmainit() atapci subdriver's channel initialization
methods into single ch_attach() method.

As opposite to ch_attach() add new ch_detach() method to deallocate/disable
channel.
2009-02-18 22:17:48 +00:00
Søren Schmidt
13014ca04a This is the roumored ATA modulerisation works, and it needs a little explanation.
If you just config KERNEL as usual there should be no apparent changes, you'll get all chipset support code compiled in.

However there is now a way to only compile in code for chipsets needed on a pr vendor basis. ATA now has the following "device" entries:

atacore:	ATA core functionality, always needed for any ATA setup

atacard:	CARDBUS support
atacbus:	PC98 cbus support
ataisa:		ISA bus support
atapci:		PCI bus support only generic chipset support.

ataahci:	AHCI support, also pulled in by some vendor modules.

ataacard, ataacerlabs, ataadaptec, ataamd, ataati, atacenatek, atacypress, atacyrix, atahighpoint, ataintel, ataite, atajmicron, atamarvell, atamicron, atanational, atanetcell, atanvidia, atapromise, ataserverworks, atasiliconimage, atasis, atavia;	Vendor support, ie atavia for VIA chipsets

atadisk:	ATA disk driver
ataraid:	ATA softraid driver

atapicd:	ATAPI cd/dvd driver
atapifd:	ATAPI floppy/flashdisk driver
atapist:	ATAPI tape driver

atausb:		ATA<>USB bridge
atapicam:	ATA<>CAM bridge

This makes it possible to config a kernel with just VIA chipset support by having the following ATA lines in the kernel config file:

device          atacore
device          atapci
device          atavia

And then you need the atadisk, atapicd etc lines in there just as usual.

If you use ATA as modules loaded at boot there is few changes except the rename of the "ata" module to "atacore", things looks just as usual.
However under atapci you now have a whole bunch of vendor specific drivers, that you can kldload individually depending on you needs. Drivers have the same names as used in the kernel config explained above.
2008-10-09 12:56:57 +00:00