aic7xxx.c:
In target mode, reset the TQINPOS on every restart of the sequencer.
In the past we did this only during a bus reset, but there are other
reasons the sequencer might be reset.
In ahc_clear_critical_section(), disable pausing chip interrupts while
we step the sequencer out of a critical section. This avoids the
possibility of getting a pausing interrupt (unexpected bus free,
bus reset, etc.) that would prevent the sequencer from stepping.
Send the correct async notifications in the case of a BDR or bus reset.
In ahc_loadseq(), correct the calculation of our critical sections.
In some cases, the sections would be larger than needed.
aic7xxx.h:
Remove an unused SCB flag.
aic7xxx.seq:
MK_MESSAGE is cleared by the kernel, there is no need to waste
a sequencer instruction clearing it.
aic7xxx_freebsd.c:
Go through the host message loop instead of issuing a single
byte message directly in the ahc_timeout() case where we
are currently on the bus to the device. The effect is the same,
but this way we get a nice printf saying that an expected BDR
was delivered instead of an unexpected bus free.
If we are requeuing an SCB for an error recovery action, be sure
to set the DISCONNECTED flag in the in-core version of the SCB.
This ensures that, in the SCB-paging case, the sequencer will
still recognize the reselection as valid even if the version
of the SCB with this flag set was never previously paged out
to system memory. In the non-paging case, set the MK_MESSAGE
flag in SCB_CONTROL directly.
aic7xxx_pci.c:
Enable the Memeory Write and Invalidate bug workaround for
all aic7880 chips with revs < 1. This bug is rarely triggered
in FreeBSD as most transfers end on cache-aligned boundaries,
but a recheck of my references indicates that these chips
are affected.
of two (one to access the circular input fifo, the other to get the SCB).
This costs us a command slot so the driver can now only queue 254
simultaneous commands.
Have the kernel driver honor critical sections in sequencer code.
When prefetching S/G segments only pull a cacheline's worth but
never less than two elements. This reduces the impact of the
prefetch on the main data transfer when compared to the 128
byte fetches the driver used to do.
Add "bootverbose" logging for transfer negotiations.
Correct a bug in ahc_set_syncrate() that would prevent an update
of the sync parameters if only the ppr_options had changed.
Correct locking for calls to ahc_free_scb(). ahc_free_scb() is no
longer protected internally to simplify ports to other platforms.
Make sure we unfreeze our SIMQ if a resource shortage has occurred
and an SCB is been freed.
ahc_pci.c:
Turn on cacheline streaming for all controllers that support it.
Clarify diagnostic messages about PCI interrupts.
sequencer files. Different platforms place the included files in different
locations and it is easier to modify the include path passed as arguments
to the assembler than adding #ifdef support to the assembler.
Remove a spurious 'nop' instruction.
Separate our platform independent hooks from core driver functionality
shared between platforms (FreeBSD and Linux at this time).
Add sequencer workarounds for several chip->chipset interactions.
Correct external SCB corruption problem on aic7895 based cards (3940AUW).
Lots of cleanups resulting from the port to another OS.
Disable "cache line streaming" for aic7890/91 Rev A chips. I
have never seen these chips fail using this feature, but
some of Adaptec's regression tests have.
Explicitly set "cache line streaming" to on for aic7896/97
chips. This was happening before, but this documents the
fact that these chips will not function correctly without
CACHETHEEN set.
aic7xxx.h:
Add new bug types.
Fix a typo in a comment.
aic7xxx.reg:
Add a definition for the SHVALID bit in SSTAT3 for Ultra2/3
chips. This bit inicates whether the bottom most (current)
element in the S/G fifo has exhausted its data count.
aic7xxx.seq:
Be more careful in how we turn off the secondary DMA channel.
Being less careful may hang the PCI bus arbitor that negotiates
between the two DMA engines.
Remove an unecessary and incorrect flag set operation in
the overrun case.
On Ultra2/3 controllers, clear the dma FIFO before starting
to handle an overrun. We don't want any residual bytes from
the beginning of the overrun to cause the code that shuts
down the DMA engine from hanging because the FIFO is not
(and never will be) empty.
If the data fifo is empty by the time we notice that a
read transaction has completed, there is no need to
hit the flush bit on aic7890/91 hardware that will not
perform an auto-flush. Skip some cycles by short circuiting
the manual flush code in this case.
When transitioning out of data phase, make sure that we
have the next S/G element loaded for the following
reconnect if there is more work to do. The code
would do this in most cases before, but there was
a small window where the current S/G element could
be exhausted before our fetch of the next S/G element
completed. Since the S/G fetch is already initiated
at this point, it makes sense to just wait for the
segment to arrive instead of incuring even more latency
by canceling the fetch and initiating it later.
Fast path the end of data phase handling for the last
S/G segment. In the general case, we might have
worked ahead a bit by stuffing the S/G FIFO with
additional segments. If we stop before using them
all, we need to fixup our location in the S/G stream.
Since we can't work past the last S/G segment, no
fixups are ever required if we stop somewhere in
that final segment.
Fix a little buglet in the target mode dma bug handler.
We were employing the workaround in all cases instead
of only for the chips that require it.
Fix the cause of SCB timeouts and possible "lost data"
during read operations on the aic7890. When sending
a data on any Ultra2/3 controller, the final segment
must be marked as such so the FIFO will be flushed and
cleaned up correctly when the transfer is ended. We
failed to do this for the CDB transfer and so, if
the target immediately transfered from command to data
phase without an intervening disconnection, the first
segment transferred would be any residual bytes from
the cdb transfer. The Ultra160 controllers for some
reason were not affected by this problem.
Many Thanks to Tor Egge for bringing the aic7890 problem
to my attention, providing analysis, as well as a mechanism
to reproduce the problem.
Correct the BUILD_TCL macro. It was placing the target id
in the wrong bits. This was only an issue for adapters that
do not perform SCB paging (aha-3940AUW for instance).
Don't bother inlining ahc_index_busy_tcl. It is never
used in a performance critical path and is a bit chunky.
Correct ahc_index_busy_tcl to deal with "busy target tables"
embedded in the latter half of 64byte SCBs.
Don't initialize the busy target table to its empty state
until after we have finished extracting configuration
information from chip SRAM. In the common case of using
16 bytes of chip SRAM to do untagged target lookups,
we were trashing the last 8 targets configuration data.
(actually only target 8 because of the bug in the
BUILD_TCL macro).
Cram the "bus reset delivered" message back under bootverbose.
Fix the cleanup of the SCB busy target table when aborting
commands. If the lun is wildcarded, we must loop through
all possible luns.
aic7xxx.h:
Only bother supporting 64 luns right now. It doesn't seem
like either this driver or any peripherals will be doing
information unit transfers (where the lun number is a
32 bit integer) any time soon.
aic7xxx.seq:
Fix support for the aic7895. We must flush the data
FIFO if performing a manual transfer that is not
a multiple of 8 bytes. We were doing this quite
regularly for embedded cdbs.
Manaually flush the fifo on earlier adapters when
dealing with embedded cdbs too. We were stuffing
the FIFO with 16 bytes instead, but triggering
the flush is more efficient and allows us to
remove two instructions from the "copy_to_fifo"
routine.
other systems.
o Normalize copyright text.
o Clean up probe code function interfaces by passing around a single
structure of common arguments instead of passing "too many" args
in each function call.
o Add support for the AAA-131 as a SCSI adapter.
o Add support for the AHA-4944 courtesy of "Matthew N. Dodd" <winter@jurai.net
o Correct manual termination support for PCI cards. The bit definitions
for manual termination control in the SEEPROM were incorrect.
o Add support for extracting NVRAM information from SCB 2 for BIOSen
that use this mechanism to pass this data to OS drivers.
o Properly set the STPWLEVEL bit in PCI config space based on the
setting in an SEEPROM.
o Go back to useing 32byte SCBs for all controllers. The current
firmware allows us to embed 12byte cdbs on all controllers in
a 32byte SCB, and larger cdbs are rarely used, so it is a
better use of this space to offer more SCBs (32).
o Add support for U160 transfers.
o Add an idle loop executed during data transfers that prefetches
S/G segments on controllers that have a secondary DMA engine
(aic789X).
o Improve the performance of reselections by avoiding an extra
one byte DMA in the case of an SCB lookup miss for the reselecting
target. We now keep a 16byte "untagged target" array on the card
for dealing with untagged reselections. If the controller has
external SCB ram and can support 64byte SCBs, then we use an
"untagged target/lun" array to maximize concurrency. Without
external SCB ram, the controller is limited to one untagged
transaction per target, auto-request sense operations excluded.
o Correct the setup of the STPWEN bit in SXFRCTL1. This control
line is tri-stated until set to one, so set it to one and then
set it to the desired value.
o Add tagged queuing support to our target role implementation.
o Handle the common cases of the ignore wide residue message
in firmware.
o Add preliminary support for 39bit addressing.
o Add support for assembling on big-endian machines. Big-endian
support is not complete in the driver.
o Correctly remove SCBs in the waiting for selection queue when
freezing a device queue.
o Now that we understand more about the autoflush bug on the
aic7890, only use the workaround on devices that need it.
o Add a workaround for the "aic7890 hangs the system when you
attempt to pause it" problem. We can now pause the aic7890
safely regardless of what instruction it is executing.
negotiation features (DT, ULTRA2, ULTRA, FAST). The offsets
where not properly updated when the DT entry was added and so
the driver could attempt to negotiate a speed faster than that
supported by the target device or even requested by the user
via SCSI-Select settings. *
o Update the target mode incoming command queue kernel index value
ever 128 commands instead of 32. This means that the kernel will
always try to keep its index (as seen on the card - the kernel may
actually have cleared more space) 128 commands ahead of where the
sequencer is adding entries.
o Use the HS_MAILBOX register instead of the KERNEL_TQINPOS location
in SRAM to indicate the kernel's target queue possition on Ultra2
cards. This avoids the "pause bug" on these cards and also turns
out to be much more efficient.
o When enabling or disabling a particular target id for target mode,
make sure that the taret id in the SCSIID register does not
reference an ID that is not to receive target selections. This
is only an issue on chips that support the multiple target id
feature where the value in SCSIID will still affect selection
behavior regardless of the values in the target id bit field
registers.
o Remove some target mode debugging printfs.
o Make sure that the sense length reported in ATIO commands is
always zero. This driver does not, yet, report HBA generated
sense information for accepted commands.
o Honor the CAM_TIME_INFINITY and CAM_TIME_DEFAULT values for
the CCB timeout field.
o Make the driver compile with AHC_DEBUG again.
* Noticed by: Andrew Gallatin<gallatin@cs.duke.edu>
for optimizing the unpause operation no-longer exist, and this is much
safer.
When restarting the sequencer, reconstitute the free SCB list on the card.
This deals with a single instruction gap between marking the SCB as free
and actually getting it onto the free list.
Reduce the number of transfer negotiations that occur. In the past, we
renegotiated after every reported check condition status. This ensures
that we catch devices that have unexpectidly reset. In this situation,
the target will always report the check condition before performing a
data-phase. The new behavior is to renegotiate for any check-condition where
the residual matches the orginal data-length of the command (including
0 length transffers). This avoids renegotiations during things like
variable tape block reads, where the check condition is reported only
to indicate the residual of the read.
Revamp the parity error detection logic. We now properly report and
handle injected parity errors in all phases. The old code used to hang
on message-in parity errors.
Correct the reporting of selection timeout errors to the XPT. When
a selection timeout occurs, only the currently selecting command
is flagged with SELTO status instead of aborting all currently active
commands to that target.
Fix flipped arguments in ahc_match_scb and in some of the callers of this
routine. I wish that gcc allowed you to request warnings for enums passed
as ints.
Make ahc_find_msg generically handle all message types.
Work around the target mode data-in wideodd bug in all non-U2 chips.
We can now do sync-wide target mode transfers in target mode across the
hole product line.
Use lastphase exclusively for handling timeouts. The current phase
doesn't take the bus free state into account.
Fix a bug in the timeout handler that could cause corruption of the
disconnected list.
When sending an embedded cdb to a target, ensure that we start on a
quad word boundary in the data-fifo. It seems that unaligned stores
do not work correctly.
93cx6.c:
Make the SRAM dump output a little prettier.
aic7xxx.c:
Store all SG entries into our SG array in kernel space.
This makes data-overrun and other error reporting more
useful as we can dump all SG entries. In the past,
we only stored the SG entries that the sequencer might
need to access, which meant we skipped the first element
that is embedded into the SCB.
Add a table of chip strings and replace ugly switch
statements with table lookups.
Add a table with bus phase strings and message reponses
to parity errors in those phases. Use the table to
pretty print bus phase messages as well as collapse
another switch statement.
Fix a bug in target mode that could cause us to unpause
the sequencer early in bus reset processing.
Add the 80MHz/DT mode into our syncrate table. This
rate is not yet used or enabled.
Correct some comments, clean up some code...
aic7xxx.h:
Add U160 controller feature information.
Add some more bit fields for various SEEPROM formats.
aic7xxx.reg:
Add U160 register and register bit definitions.
aic7xxx.seq:
Make phasemis state tracking more straight forward. This
avoids the consumption of SINDEX which is a very useful register.
For the U160 chips, you must use the 'mov' instruction to
update DFCNTRL. Using 'or' to set the PRELOADED bit is
completely ineffective.
At the end of the command phase, wair for our ACK signal
to de-assert before disabling the SCSI dma engine. For
slow devices, this avoids clearing the ACK before the
other end has had a chance to see it and lower REQ.
aic7xxx.c:
Add a function for sucking firmware out of the controller
prior to reset.
Remove some inline bloat from functions that should not have
been inlined.
During initialization, wait 1ms after the chip reset before
touching any registers. You can get machine checks on certain
architectures (Atari I think?) without the delay.
Return CAM_REQ_CMP for external BDR requests instead
of CAM_BDR_SENT.
Bump some messages to bootverbose levels above 1.
Don't clear any negotiated sync rate if the target rejects
a WDTR message. The sync rate is only cleared if the target
accepts a WDTR message.
Fix a small bug in the mesgin handling code that could cause
us to believe that we had recieved a message that was actually
received by another target. This could only confuse us in
some very rare transmission negotiation scenarios.
Remove some unecessary cleanup of residual information after
a residual is reported. The sequencer does this when the
command is queued now.
aic7xxx parts. This problem could result in data corruption
during periods of my PCI bus load by busmasters other than the
aic7xxx.
Many thanks to Andrew Gallatin <gallatin@cs.duke.edu> for characterizing
the symptoms of this problem and testing this fix.
Honor the 'bus reset at startup' option now that the XPT properly
handles transfer negotiation in this scenario.
Honor the sync rate settings on Ultra2 controllers. We would
always negotiate at the fastest speed. Oops.
aic7xxx.h:
Whitespace.
aic7xxx.seq:
Fix a minor nit that would cause the controller to miss the update
of the negotiation required bitmask causing the negotiation to
be delayed by a command.
tell the sequencer to pause itself for a target msg variable update. This
avoids the pause race entirely as HS_MAILBOX can be accessed without
pausing the chip.
3.2 Merge candidate.
Don't mess with the IRQMS bit in the host control register unless
we are an aic7770 chip.
Use calling context to determine if the card is already paused when
we update the target message request bit field in controller scratch
ram. Looking at the paused bit in the HCNTRL register opened up a
race condition.
Insert delays in the target message request update routine as a temporary
work around for what looks like a chip bug. I'm still investigating this
one.
Fix the Abort/Abort Tag/BDR handler to pull its message from the message
buffer in our softc instead of attempting to get it from a register on
the controller. The message is never recorded by the controller in the
new message scheme.
Don't rely on having an SCB when a BDR occurs. We can issue these during
invalid reconnects to.
Fix a few cases where we were restarting the sequencer but then still
falling out of a switch statement to unpause the sequencer again.
This could cause us to mess up sequencer state if it generated another
pausing interrupt between the time of the restart and unpause.
Kill the 'transceiver settle' loop during card initialization. I
failed to realize that a controller that is not connected to any
cables will never settle or enable the SCSI transceivers at all.
The correct solution is to monitor the IOERR interrupt which indicates
that the transceiver state has changed (UW<->LVD).
Modify the aic7xxx assembler to properly echo input when stdin is not
a tty.
connection.
Clean up support for devices featuring the multiple target SCSI ID feature.
On aic7890/91/96/97 chips, we can now assume the target role on multiple
target ids simultaneously. Although these chips also have sufficient
instruction space to hold to support the initiator and target role at the
same time, the initiator role is currently disabled as it will conflict
(chip design restriction) with the multi-tid feature. I'll probably add
a nob to enable the initiator (there-by disabling multi-tid) some time
in the future.
Return queue full or busy, depending on the tagged nature of the incoming
request, if our command input queue fills up in host memeory.
Deal with accept target I/O resource shortages.
If we get an underrun on a transaction that wasn't supposed to transmit
any data, don't attempt to print out the S/G list. The code would
run until hitting a non-present page. (oops)
black hole device. The controller will now only accept selections if
the black hole device is present and some other target/lun is enabled
for target mode.
Handle the IGNORE WIDE RESIDUE message. This support has not been tested.
Checkpoint work on handling ABORT, BUS DEVICE RESET, TERMINATE I/O PROCESS,
and CLEAR QUEUE messages as a target.
Fix a few problems with tagged command handling in target mode.
Wait until the sync offset counter falls to 0 before changing phase
after a data-in transfer completes as the DMA logic seems to indicate
transfer complete as soon as our last REQ is issued.
Simplify some of the target mode message handling code in the sequencer.
Use the host message loop for any unknown message types instead of performing
a reject message in the sequencer. Pass reject messages to the host
message loop too which frees up a sequencer interrupt type slot.
Default to issuing a bus reset if initiator mode is enabled. It seems
that the reset scsi bus bit is not defined in the same location for
all aic78xx BIOSes, so attempting to honor this setting will have to
wait until I get more information on how to detect it.
Nuke some unused variables.
in target mode, but we are not completing the command.
Use a template of allowed bus arbitration phases to selectively and
dynamically enable/disable initiator or target (re)selection.
Properly handle timeouts for target role transactions - just go to the
bus free state and report the error to the peripheral driver.
Checkpoint support for the XPT_ABORT_CCB function code. This currently
handles the accept tio and immediate notify ccb types, but does not
handle the continue target I/O or SCSI I/O ccb types. This is enough
to handle dynamic target enable/disable events.
Clean up the SCSI reset code so that we perform at most 1 SCSI bus
reset at initialization, the reset requested by the XPT layer.
is more robust and common code can be used for both the target and iniator
roles. The mechanism for tracking negotiation state has also been simplified.
Add support for sync/wide negotiation in target mode and fix many of
the target mode bugs running at higher speeds uncovered. Make a first
stab at getting all of the bus skew delays correct. Sync+Wide dataout
transfers still cause problems, but this may be an initiator problem.
Ensure that we exit BITBUCKET mode if the controller is restarted.
Add support for target mode only firmware downloads. This has been
tested on the aic7880, but should mean that we can perform target mode
on any aic7xxx controller. Mixed mode (initiator and target roles in
the same firmware load) is currently only supported on the aic7890, but
with optimization, may fit on chips with less instruction space.
use a 256 entry ring buffer of descriptersfor this purpose. This allows
the use of a simple 8bit counter in the sequencer code for tracking start
location.
Entries in the ring buffer now contain a "cmd_valid" byte at their tail.
As an entry is serviced, this byte is cleared by the kernel and set by
the sequencer during its dma of a new entry. Since this byte is the last
portion of the command touched during a dma, the kernel can use this
byte to ensure the command it processes is completely valid.
The new command format requires a fixed sized DMA from the controller
to deliver which allowed for additional simplification of the sequencer
code. The hack that required 1 SCB slot to be stolen for incoming
command delivery notification is also gone.
- Convert to CAM
- Use a new DMA based queuing and paging scheme
- Add preliminary target mode support
- Add support for the aic789X chips
- Take advantage of external SRAM on more controllers.
- Numerous bug fixes and performance improvements.
data fifo is full, but the PCI input latch is not empty,
HDMAEN cannot be cleared. The fix used here is to attempt
to drain the data fifo until there is space for the input
latch to drain and HDMAEN de-asserts.
This is a 1 instruction fix, so it should have no performance
impact.
operands that are set during seqeuncer program download instead of at
assembly time.
Convert the sequencer code to use" downloaded constants" for four run time
constants that vary depending on the board type. This frees up 4 bytes
of sequencer scratch ram space where these constants used to be stored and
also removes the additional instructions required to load their values
into the accumulator prior to using them.
Remove the REJBYTE sram variable. The host driver can just as easly
read the accumulator to get this value.
The scratch ram savings is important as the old code used to clober the
SCSICONF register on 274X cards which sits near the top of scratch ram
space. The SCSICONF register controls bus termination, and clobbering
it is not a good thing. Now we have 4 bytes to spare.
This should fix the reported problems with cards that don't have devices
attached to them failing with a stream of "Somone reset bus X" messages.
Doug Ledford determined the cause of the problem, fixes by me.
entry to the QOUTFIFO when it is full. This should eliminate the
"Timed out while idle" problems that many have reported.
In truth, this is somewhat of a hack. Although are interrupt latency is
low enough that we should be able to always service the queue in time,
since each entry must be passed up to the higher SCSI layer for what can
be a large amount of processing (perhaps even resulting in a new command
being queued) with interrupts disabled, we need this mechanism to avoid
overflow. In the future, these additional tasks will be offloaded to a
software interrupt handler which should make this hack unnecessary.
if SCB Paging was enabled:
disconnect with more data to transfer
disconnected SCB gets paged out
target reconnects so we page SCB back in
target completes transfer so residual is 0
target disconnects
SCB gets reused but not paged out since the residual is 0 (optimization)
target reconnects so we page the SCB back in
we report a residual because of stale residual information.
The fix for this is to set a flag that forces the SCB to be paged back
up to the host if we page in an SCB with a residual
Pointed out by: Doug Ledford <dledford@dialnet.net>
to fix a selection timeout problem.
If we can't find an SCB for the reconnecting target, issue a bus device
reset as the SCSI2 spec suggests.
Add a missing call to "add_scb_to_free_list" in the non paging case. In
the non-paging case, the SCBs don't really need to be on the free list,
but putting them there clears the tag field which is something the recovery
code depends on.
Be consistant about testing for parity errors after waiting for a
REQ on the bus.
Don't ack the last byte in a transaction until after we've cleared
all target state.
aic7xxx_asm.c:
Test the return value of getopt against -1 not EOF. (Yet another
shameless victum of the style guide being wrong).
loop, test for them separately. The bug report from David Malone showed that
even though we had been reselected (SELDI was true), we sat in the poll for
work loop until the selection timeout timer expired. It may be that the
SSTAT0 register doesn't like to have more than one bit tested at a time.
I've seen stranger things than this on these parts.
either by looking it up in the array of pending, per target, untagged
transactions, or by using the tag value passed in during the identify. The
old code only direct indexed for tagged transactions. This makes the
"findSCB" routine only necessary when SCB paging is enabled, so appropriately
conditionalize it. This greatly simplifies the non SCB paging code flow.
Stick 4 more, twin channel only, instructions behind
.if ( TWIN_CHANNEL)
aic7xxx_asm.c:
Add the -O options which allows the specification of which options
to include in a program listing. This makes it possible to easily
determine the address of any instruction in the program across
different hardware/option configurations. Updated usage() as well.
New sequencer assembler for the aic7xxx adapters. This assembler
performs some amount of register type checking, allows bit
manipulation of symbolic constants, and generates "patch tables"
for conditionalized downloading of portions of the program.
This makes it easier to take full advantage of the different
features of the aic7xxx cards without imposing run time penalies
or being bound to the small memory footprints of the low end
cards for features like target mode.
aic7xxx.reg:
New, assembler parsed, register definitions fo the aic7xxx cards.
This was done primarily in anticipation of 7810 support which
will have a different register layout, but should be able to use
the same assembler. The kernel aic7xxx driver consumes a generated
file in the compile directory to get the definitions of the register
locations.
aic7xxx.seq:
Convert to the slighly different syntax of the new assembler.
Conditionalize SCB_PAGING, ultra, and twin features which shaves
quite a bit of space once the program is downloaded.
Add code to leave the selection hardware enabled during reconnects
that win bus arbitration. This ensures that we will rearbitrate
as soon as the bus goes free instead of delaying for a bit.
When we expect the bus to go free, perform all of the cleanup
associated with that event "up front" and enter a loop awaiting
bus free. If we see a REQ first, complain, but attempt to
continue. This will hopefully address, or at least help diagnose,
the "target didn't send identify" messages that have been reported.
Spelling corrections obtained from NetBSD.
time that we really want to do this is when a bus reset causes the sequencer
to be reset and the kernel driver now handles this case.
Remove some reordering in the select2 routine that wasn't necessary.
It was an experimental fix for a race condition I fixed elsewhere, and
confused the code flow.
Don't bother looping on a parity error in the mesgout loop since we can't
see parity errors on out phases.
Clean up the mesgin_identify code. In the old days, we "snooped" for tag
messages and used this as an indicator of whether or not the target was
using tagged transactions. This forced the sequencer to ack the identify
before determining if a valid SCB matched the target meaning that an abort
message to handle this case might not be seen before the target entered a
data phase. Since we can determin the "tagged-ness" of a target by looking
it up in the array of busy targets (recently introduced), we can determine
this up front simplifying the search code as well as ensuring we can follow
the SCSI specs method for rejecting a reselection.
When an SCB is placed on the free list, set its SCB_TAG to SCB_LIST_NULL.
This makes it much easier for the kernel driver to find active SCBs on the
card during error recovery.
negotiation messages may be tagged, we were overrunning the old buffer.
The variable that was getting squashed is updated before the message goes
out, causing corrupted SDTR or WDTR messages. Depending on the phases
traversed before message out, this could cause the wrong offset to be
negotiated allowing data overruns to occur. The problem is easier to
detect with wide targets on the chain since the allowed offset is smaller.
Also removed the unnecessary clearing of SPIORDY during the message out
phase. We don't rely on SPIORDY any more.
When setting the HCNT registers, do so in ascending order.
When performing tagged queueing in non-paging mode, also check the
disconnected bit in the SCB as extra sanity during a reconection.
Make the labels in the DMA routine more sane.
When doing a DMA, if we see the DMADONE condition come true, we can
simply turn of the DMA enable bits in DFCNTRL without testing the FIFO
state as HDONE is true when DMADONE is true and this emplies the FIFO is
empty.
These changes clear up the data overrun error messages and seem to prevent
the "timed out in data-in phase" problems.
free.
When we clear SCSIRATE, also clear the FAST20 bit in SXFRCTL0. This also
allowed me to clean up some of the ULTRA code.
ULTRAENB->FAST20 to follow the convention in the Adaptec data books.
Fix the data-overrun code to set both stcnt and hcnt otherwise, the transfer
will just hang until we get a timeout.
Add implicit support for the NOOP message. I've never heard of the driver
issueing a reject for one, but its silly to reject NOOP and who knows how a
device might react.
In the dma routine, check SDONE before cleaing SDMAEN. The data books mention
SDONE possibly being cleared when SDMAEN is reset. Clients of dma now need
to check if SINDEX is cleared to know if a phasemis occured.
Fix some comments to be correct.
host DMAs. The additional test to ensure that the DMA has stopped is also
unnecessary since we've already waited for the DMA to complete.
Update my copyright for the new year.
Expand the boundaries of a pause disabled region to close of possible race
condition.
Revert a portion of the DMA code to fix false overruns.
Add a missing "add_scb_to_free_list" so we don't leak SCBs.
SDONE, not HDONE.
In the data phase dma handler, mask off just the enable bits instead of
clearing the whole register. Clearing the direction bit could be bad.
Also don't stop a DMA until MREQPEND goes false. Doing this may cause
an ABORT on the PCI bus although I have yet to see this happen.
Add definitions for MREQPEND and the BRDCTL register. The BRDCTL register
is used to handle high byte termination and automatic termination testing.
Only enable reselections once the channel and SCSIRATE have been cleared.
Add a pause block around the test busy code in the non-tagged case to simplify
error recovery in the corner case of aborting an SCB that just got started.
Simplify reselection processing by removing the call to initialize_scsiid.
Clear the scsiseq re/select control bits and setup for catching bogus
busfrees earlier in the re/select process.
Improve the automatic PIO code. It turns out that SPIORDY is not a reliable
hardware condition bit, so use REQINIT intstead. Don't rely on PHASEMIS
either since it can take too long to come true. Use a brute force comparison
instead.
Remove some unnecessary overhead in the command complete processing. It
should be nearly impossible to overflow the QOUTFIFO (worst case 9 command
have to complete with at least 6 of them requiring paging on an aic7850),
so don't take the additional PIO hit to guard against this condition. If we
don't see our interrupt in time, the system has bigger problems elsewhere.
If this ever does happen, the timeout handler will notice and retry the
command.
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.
Boy, I'm glad we're not using sup anymore. This update would have been
insane otherwise.
