There is a hardware problem between Cortex-A9 CPUs and on-chip devices
in Armada 38X SoCs that may cause hang on heavy load. This can be
however worked around by mapping all registers and PCI IO
as strongly ordered instead of device memory.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Reviewed by: mmel
Tested by: mw_semihalf.com
Obtained from: Semihalf
Differential revision: https://reviews.freebsd.org/D10218
This commit enables usage of HWPMC interrupts for the
Marvell SoCs, which use MPIC (Armada38x and ArmadaXP).
Those interrupts require extra unmasking, comparing to
others. Also, in order to process counters per-CPU,
they are masked/unmasked using separate registers' sets
for each core.
Submitted by: Michal Mazur <mkm@semihalf.com>
Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Differential revision: https://reviews.freebsd.org/D10913
This patch contains a new driver for the network unit of Marvell
Armada 38x/XP SoCs, called NETA. This support was thoroughly tested
and optimised in terms of stability and performance. Additional
hardware features, like Buffer Management (BM) or Parser and Classifier
(PnC) will be progressively supported as needed.
Submitted by: Fabien Thomas <fabien.thomas@stormshield.eu>
Arnaud Ysmal <arnaud.ysmal@stormshield.eu>
Zbigniew Bodek <zbb@semihalf.com>
Michal Mazur <mkm@semihalf.com>
Bartosz Szczepanek <bsz@semihalf.com>
Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield (main development)
Netgate (cleanup and upstreaming)
Differential revision: https://reviews.freebsd.org/D10706
This commit is another part of preparation for PCIe multi-port
support for Marvell SoCs. Some device trees include pcie-controller
node as a bus-parent of pcie nodes. This patch adds support for
new bus, collects and configures device informations and finally
adds PCIB devices as a childs of pcie-controller in Newbus hierarchy.
Submitted by: Marcin Mazurek <mma@semihalf.com>
Obtained form: Semihalf
Sponsored by: Stormshield
Reviewed by: https://reviews.freebsd.org/D10906
Original PCIe nodes for Marvell SoCs consists of ports' nodes
under main controller node. In order to properly parse
this kind of representation in DT a mechanism for traversing
through the tree required an update. Moreover, processing FDT
data consisting of more than 2 cells had to be fixed,
because the 'reg' property of mrvl,pcie node have additional
parameter in front of 64-bit address. It should be skipped
by default. This commit works properly with old mrvl,pcie
representation for Kirkwood and ArmadaXP SoCs.
Submitted by: Wojciech Macek <wma@semihalf.com>
Michal Mazur <mkm@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Differential revision: https://reviews.freebsd.org/D10905
This patch fixes sporadic problems with updating time
with mv_rtc driver by configuring access to it via MBUS.
For this purpose already existing second set of resources
in rtc@3800 node of Armada 38x DT is used.
Submitted by: Dominik Ermel <der@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10901
This commit enables optional reset of the RTC, in case
its registers' contents did not sustain the reboot or power-off/on
sequence. Without it, further usage of RTC is impossible
(e.g. writing values to RTC_TIME register will not succeed).
The reset is performed only if Clock Correction register
does not comprise RTC_NOMINAL_TIMING, what helps to distinguish,
whether the software configured RTC before or it comprises
the default value.
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10900
This patch fixes a bug introduced with commit:
r294510 "Remove an extra '!' found by clang 3.8."
'!' was removed without inverting the logic, which
broke PCIe legacy interrupts operation for Marvell
controllers.
Submitted by: Michal Mazur <mkm@semihalf.com>
Obtained from: Semihalf
Sponsored by: Netgate
Armada 38x SoC's equipped with 4GB DRAM suffer freeze
during CESA operation, if MBUS window opened at given
DRAM CS reaches end of the address space. Apply a workaround
by setting the window size to the closest possible
value, i.e. divide it by 2 (it has to be power-of-2).
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10724
PM status is only supported on Kirkwood and Disvovery.
Cleanup the code to properly report its state on
other platforms.
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10718
DELAY is a problematic routine called all over the kernel.
Armada38x using CA-9 CPUs are using mpcore timer to count events
and measure time but DELAY in the mpcore timer code is a weak
function reference and therefore will be replaced by the platform
implementation if the one is introduced. Since Armada38x uses
on-chip watchdog to which the driver is merged with the on-chip timer
driver there will be a platform DELAY implementation.
The latter however will not use any HW timers as it will not attempt
to configure any. Phony busy loop will be used instead.
To fix that we introduce a separate watchdog driver for Armada platforms,
(currently only A38X) and stop using Marvell timer driver. That
switches DELAY to the desired implementation.
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10710
Resolving CPU windows from localbus entry caused buffer overflow
and memory corruption. Fix wrong indexing and ensure the index
does not exceed table size.
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10720
Marvell Armada 380 is a uni-processor variant of the 38x SoC
family. A function platform_mp_setmaxid() was setting a hardcoded
value, which caused boot fail on A380. Fix this by relying on
the CPU count obtained from device tree nodes.
Submitted by: Marcin Wojtas <mw@semihalf.com
Obtained from: Semihalf
Sponsored by: Netgate
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10783
Before the fix for single interrupt, both percpu and non-percpu routes
were enabled/disable at the same time.
Submitted by: Marcin Wojtas <mw@semihalf.com
Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10716
For all Marvell devices, MBUS windows configuration is done
in a common place. Only CESA was an exception, so move its
related code from driver to mv_common.c. This way it uses
same proper DRAM information, same as all other interfaces
instead of parsing DT /memory node directly.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10723
consistent and easier to read.
While here, remove two unused static functions and fix a unused function
warning when building !INTRNG.
No functional changes.
Sponsored by: Rubicon Communications, LLC (Netgate)
If MPIC happens to be a slave interrupt controller (as on Armada38x),
it should be attached after primary interrupt controller.
Thus BUS_PASS_ORDER_LATE was added to default BUS_PASS_INTERRUPT.
This change doesn't affect the cases when MPIC is standalone IC.
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10715
OF_finddevice doesn't find the "simple-bus" node, which is problematic
for Marvell platforms, using nested buses in Device Tree, like
Armada 38x SoC.
Submitted by: Arnaud Ysmal <arnaud.ysmal@stormshield.eu>
Obtained from: Stormshield
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10719
sdhci_fdt.
Enable the SDHCI controller, bus and devices on ARMADA38X kernel.
Tested on: ClearFog Pro
Reviewed by: Marcin Wojtas <mw at semihalf.com>
Sponsored by: Rubicon Communications, LLC (Netgate)
Differential Revision: https://reviews.freebsd.org/D10606
Tested on: ClearFog Pro
Reviewed by: Marcin Wojtas <mw at semihalf.com>
Sponsored by: Rubicon Communications, LLC (Netgate)
Differential Revision: https://reviews.freebsd.org/D10601
Add early init handler, which comprises various internal
bus optimisations for Armada 38x SoC's. Magic values used
due to undocumented registers.
Submitted by: Marcin Wojtas <mw@semihalf.com>,
Arnaud Ysmal <arnaud.ysmal@stormshield.eu>
Obtained from: Semihalf, Stormshield
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10219
Introduce machine-dependent part of the arm/pl310 driver for
Armada 38x SoCs. Add prefetch and power savings configuration.
Submitted by: <arnaud.ysmal@stormshield.eu>
Obtained from: Stormshield
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D10220
It seems to be old code from the armv6 project branch that never had a
kernel config.
Reviewed by: mmel
Sponsored by: ABT Systems Lrd
Differential Revision: https://reviews.freebsd.org/D7166
Convert PCIe hot plug support over to asking the firmware, if any, for
permission to use the HotPlug hardware. Implement pci_request_feature
for ACPI. All other host pci connections to allowing all valid feature
requests.
Sponsored by: Netflix
- Use new option SMP_ON_UP instead of (mis)using specific CPU type.
By this, any SMP kernel can be compiled with SMP_ON_UP support.
- Enable runtime detection of CPU multiprocessor extensions only
if SMP_ON_UP option is used. In other cases (pure SMP or UP),
statically compile only required variant.
- Don't leak multiprocessor instructions to UP kernel.
- Correctly handle data cache write back to point of unification.
DCCMVAU is supported on all armv7 cpus.
- For SMP_ON_UP kernels, detect proper TTB flags on runtime.
Differential Revision: https://reviews.freebsd.org/D9133
Commit r312747 ("Setup decoding windows for ARMADA38X") resulted
in build failing for Marvell platforms, which don't have AHCI controller.
This patch provides a fix by adding dummy functions for such cases.
On the occasion rename register dump routine to decode_win_ahci_dump,
in order to avoid confusion.
Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
This file provides support for AHCI mode on Armada38x
and adds new optional AHCI device to arm/mv/files.mv.
Submitted by: Konrad Adamczyk <ka@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D9222
It is necesarry to open memory windows on internal bus for
AHCI driver to work correctly.
Submitted by: Konrad Adamczyk <ka@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D9220
Configure decoding windows only for devices with
enabled nodes in FDT.
Submitted by: Konrad Adamczyk <ka@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: zbb
Differential revision: https://reviews.freebsd.org/D9219
* Currently supports only Armada38X family but other Marvell SoC's
can be added if needed.
* Provides temperature is C deg.
* To print the temperature one can use:
sysctl dev.armada_thermal.0.temperature
Submitted by: Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D9217
Replace archaic "busses" with modern form "buses."
Intentionally excluded:
* Old/random drivers I didn't recognize
* Old hardware in general
* Use of "busses" in code as identifiers
No functional change.
http://grammarist.com/spelling/buses-busses/
PR: 216099
Reported by: bltsrc at mail.ru
Sponsored by: Dell EMC Isilon
for later Cortex-A CPUs that support the Multiprocessor Extensions. This
will be needed to support both in a single GENERIC kernel while still
being able to only build for a single SoC.
Reviewed by: mmel
Relnotes: yes
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D8138
Check if there is a second CESA SRAM node in FDT and add a CPU window
for it. Define A38X specific macro for setting device attribute for
each node.
Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6216
On other platforms with CESA accelerator the SRAM memory is mapped in
early init before driver is attached. This method only works correctly
with mappings no smaller than L1 section size (1MB). There may be more
SRAM blocks and they may have smaller sizes than 1MB as is the case
for Armada38x. Instead, map SRAM memory with bus_space_map() in CESA
driver attach. Note that we can no longer assume that VA == PA for the
SRAM.
Submitted by: Michal Stanek <mst@semihalf.com
Obtained from: Semihalf
Sponsored by: Stormshield
Differential revision: https://reviews.freebsd.org/D6215
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.
ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.
Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.
Loves it: imp
