Commit Graph

270 Commits

Author SHA1 Message Date
Nate Lawson
8526ed739d ACPI is not on pc98 either.
Informed by:	nyan
2004-12-03 08:44:56 +00:00
Nate Lawson
161ad64e63 Non-x86 platforms cannot use the ACPI includes. This should be fixed but
for now, only include the headers for i386, amd64, or ia64.

Pointed out by:	grehan
2004-12-03 08:13:08 +00:00
Nate Lawson
10ce62b975 Turn ACPI and PCI devices off or to a lower power state in suspend and
back on again in resume.  Override the default of D3 with the value the
BIOS specifies in _SxD, if present.  Skip serial devices (PNP05xx) since
they seem to hang when set to D3 and may require special driver support.
Also, skip non-type 0 PCI devices (i.e., bridges) since our we don't yet
save/restore their config space and that seems to be necessary.

If this gives you trouble with suspend/resume, you can disable the new
ACPI and PCI power behavior separately with these tunables & sysctls:
    debug.acpi.do_powerstate
    hw.pci.do_powerstate

Approved by:	imp (pci)
Tested by:	acpi@ (numerous)
2004-12-02 08:07:12 +00:00
Warner Losh
4ae6f4a64e Make pci_do_powerstate default to 1 now that we've done the release to
get more testing.  This should help things a little.
2004-11-10 00:41:39 +00:00
John Baldwin
d39d4a6e64 - Change the ddb paging "support" to use a variable (db_lines_per_page) to
control the number of lines per page rather than a constant.  The variable
  can be examined and changed in ddb as '$lines'.  Setting the variable to
  0 will effectively turn off paging.
- Change db_putchar() to force out pending whitespace before outputting
  newlines and carriage returns so that one can rub out content on the
  current line via '\r     \r' type strings.
- Change the simple pager to rub out the --More-- prompt explicitly when
  the routine exits.
- Add some aliases to the simple pager to make it more compatible with
  more(1): 'e' and 'j' do a single line.  'd' does half a page, and
  'f' does a full page.

MFC after:	1 month
Inspired by:	kris
2004-11-01 22:15:15 +00:00
Brian Feldman
9b4fab9ef6 Fix a spelling error in a panic string. 2004-10-14 03:05:39 +00:00
Olivier Houchard
b19d97eb9c Re-route interrupts on arm as well. 2004-09-23 22:58:43 +00:00
Warner Losh
828a0b7110 Disable native ata support for now, too much breaks 2004-07-02 13:42:36 +00:00
Søren Schmidt
d485c7bcf3 Update the special handling code for ATA devices to allow usage of
PCI native addressing. That means that if the HW says that using "real"
addresses instead of the hardwired legacy compat ones is allowed, we will
use them.
2004-06-29 20:25:43 +00:00
Poul-Henning Kamp
89c9c53da0 Do the dreaded s/dev_t/struct cdev */
Bump __FreeBSD_version accordingly.
2004-06-16 09:47:26 +00:00
Warner Losh
ef77fe1a5b Use PCI_BAR() in preference to PCI_MAPS + x * 4.
Submitted by: jhb
2004-05-24 17:41:05 +00:00
Warner Losh
7138b71d5f Do not write to those config registers that are unambiguously defined
in the various pci specifications as readonly.  vendor, subvendor,
device and subdevice are required to be loaded in hardware by some
means that isn't the system BIOS or other system software (although
some devices do have ways of accomplishing this).  class and subclass
are defined to be read-only in section 6.2.1 (v2.2).  Apart from the
status register, which we weren't touching, these are the only
read-only registers I could find in the 2.2 spec.

progif is also defined as being read-only in section 6.2.1.  However,
the PCI IDE programming document specifically states that some of the
bits are read/write.  Since we may have to restore registers before we
have a driver attached, go ahead and restore this one byte when
transitioning between D3 and D0.

The PCI spec also says that writes to reserved and unimplemented
registers must be completed normally.  It makes no statements about
writes to read-only registers, so be as conservative as possible,
while covering the exception to the rule that is documented in a
subpart of the standard.

Requested by: socttl
2004-05-24 15:52:57 +00:00
Warner Losh
c5b82061f4 Fix cutNpasto in last commit. 2004-05-21 19:47:55 +00:00
Warner Losh
d776e1167f ifdef writing to registers that the base pci standard says are
read-only on D3->D0 power state transition.  Add a define to enable
them, but include a comment to contact me if there's a problem.
2004-05-21 14:41:02 +00:00
Warner Losh
17249aab6e Compeletely rewrite the description of hw.pci.do_powerstate to sound
better.
2004-05-21 07:06:54 +00:00
Warner Losh
4c04937d5b Improve the English somewhat.
Prodded by: ru@
2004-05-21 07:03:07 +00:00
Warner Losh
cd677980a1 Ooops, forgot to commit the updated definition for hw.pci.do_powerstate
when I committed code that changed its meaning.
2004-05-21 06:43:46 +00:00
Warner Losh
b17653cf41 MFp4:
Split the baby.  For idepci devices, now both legacy mode bits need
not be set.  We can run an idepci in a split mode.  However, it only
works better than before, not works.  It works better in that when one
device is legacy and the other isn't and disabled, we now operate
correctly.

sos submitted a version of this patch.
2004-05-21 06:41:15 +00:00
Warner Losh
ae8b157fbf Move pci_do_powerstate up a level. Now it just means 'do not turn devices
off into d3 state when there's no driver for the device'.  This should
help suspend/resume in the default case.
2004-05-21 06:39:09 +00:00
Warner Losh
e5af1ba884 MFp4: o save/restore subvendor, subdevice, vendor, device, baseclass,
subclass, progif and revid.  While these are typically read
	only fields, they aren't always read-only.  progif is writable
	for ata devices, for example.  It does no harm when they are
	read only, and helps when they aren't.
2004-05-21 06:36:36 +00:00
Warner Losh
d53b25544c make the pci power state and resource code a lot less chatty. The
chattiness was left in for debugging, but now that nearly all of the
problems relating to the changes have been fixed, it is only annoying.  It
is still available via bootverbose.

Prodded by: jhb
2004-05-21 06:03:26 +00:00
Thomas Moestl
fe2c61013d Remove the EBus stopgap of r1.248; a proper fix is in place now. 2004-04-28 13:43:11 +00:00
Warner Losh
1c168bb710 Fix two typos from PR: 65694
1) In pci.c, we need to check the child device's state, not the parent
   device's state.
2) In acpi_pci.c, we have to run the power state change after the acpi
   method when the old_state is > new state, not the other way around.

Submitted by: Dmitry Remesov
PR: 65694
2004-04-26 02:11:38 +00:00
Marius Strobl
27c2013edf Add a stopgap for the EBus breakage on sparc64 since the PCI code does
resource pre-allocation. The problem is that the BARs of the EBus bridges
contain the ranges for the resources for the EBus devices beyond the bridge.
So when the EBus code tries to allocate the resource for an EBus device
it's already allocated by the PCI code.
To be removed again as soon as we have a proper solution in the EBus Code.

Reviewed by:	tmm
Approved by:	marcel (mentor)
2004-04-23 15:48:48 +00:00
Warner Losh
206995a116 ata devices in legacy are special, and we must treat them as such.
While I would have prefered to have a solution that didn't move
knowledge of this into the pci layer.  However, this is literally the
only exception that's listed in the PCI standard to the usual way of
decoding BARs.  atapci devices in legacy mode now ignore the first 4
bars and hard code the values to the legacy ide values (well, for each
of the controllers that are in legacy mode).  The 5th bar is handled
normally.

Remove the zero bar handling.  zero bars should be ignored at all
other times, and since we handle that specially, we don't need the
older workaround.
2004-04-21 20:19:56 +00:00
Søren Schmidt
470fcc93b9 Do not pre-allocate resources for BAR's on ATA MASTERDEV's thats on
the standard ATA primary and secondary addresses.

Reintroduce the size 1 ALTIO space so that we can have both ATA and
floppies back working.
2004-04-20 20:57:29 +00:00
Warner Losh
f77ad99d59 ooops. I disabled pci_enable_io_modes not pci_do_powerstate in the last
commit.  That was in error.

Noticed by: sos
2004-04-16 15:01:54 +00:00
Warner Losh
b24afb1761 make the bad bar warning less scary, and toss it behind a bootverbose.
It is harmless, but freaking people out.
2004-04-16 04:53:19 +00:00
Warner Losh
d966428737 Turn off the power stuff for a little while longer. There appears to be
something subtle wrong with it.
2004-04-16 04:50:54 +00:00
Warner Losh
b0855e456e Now that the dust has settled on the resource issues, turn on the
power parts of my patches and see what breaks.  Don't (yet) throw
the chatty messages behind a if (bootverbose).
2004-04-14 17:52:08 +00:00
Warner Losh
d9f6718ee3 Some devices have what appear to be invalid BARs. They are invalid in
the sense that any write to them reads back as a 0.  This presents a
problem to our resource allocation scheme.  If we encounter such vars,
the code now treats them as special, allowing any allocation against
them to succeed.  I've not seen anything in the standard to clearify
what host software should do when it encounters these sorts of BARs.

Also cleaned up some output while I'm here and add commmented out
bootverbose lines until I'm ready to reduce the verbosity of boot
messages.

This gets a number of south bridges and ata controllers made mostly by
VIA, AMD and nVidia working again.  Thanks to Soren Schmidt for his
help in coming up with this patch.
2004-04-13 19:31:57 +00:00
Warner Losh
e3d5128493 Add system tunable to turn off power state changes. Default to off until
we get the resource allocation stuff hammered out.

Fix and off by one error that caused unnecessary filtering of valid
BARs for only 4 bytes than ICH3 and other PCI IDE controllers have.
Andrew Gallatin submitted this, although it doesn't solve the problems
ICH3 controllers have with the new code, it does restore the former
resource list on the probe line.
2004-04-11 07:02:49 +00:00
Warner Losh
bbecd97c0b Only print state change message for real state changes. When we set a
device in D0 to D0, that's a no-op, however the messages seem to be
confusing some people.  Eventually, these messages will be parked
behind a if (bootverbose).

# I don't think this will fix any real bugs...
2004-04-09 20:41:18 +00:00
Warner Losh
cd8b53ed2d Omnibus PCI commit:
o Save and restore bars for suspend/resume as well as for D3->D0
	  transitions.
	o preallocate resources that the PCI devices use to avoid resource
	  conflicts
	o lazy allocation of resources not allocated by the BIOS.
	o set unattached drivers to state D3.  Set power state to D0
	  before probe/attach.  Right now there's two special cases
	  for this (display and memory devices) that need work in other
	  areas of the tree.

Please report any bugs to me.
2004-04-09 15:44:34 +00:00
Warner Losh
f54a290f54 Minor whitespace changes to conform better to stlye(9) and reduce diffs
with uncommitted changes I have in p4.
2003-12-24 02:01:22 +00:00
Peter Wemm
0d2a298904 Initial landing of SMP support for FreeBSD/amd64.
- This is heavily derived from John Baldwin's apic/pci cleanup on i386.
- I have completely rewritten or drastically cleaned up some other parts.
  (in particular, bootstrap)
- This is still a WIP.  It seems that there are some highly bogus bioses
  on nVidia nForce3-150 boards.  I can't stress how broken these boards
  are.  I have a workaround in mind, but right now the Asus SK8N is broken.
  The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed.
- Most of my testing has been with SCHED_ULE.  SCHED_4BSD works.
- the apic and acpi components are 'standard'.
- If you have an nVidia nForce3-150 board, you are stuck with 'device
  atpic' in addition, because they somehow managed to forget to connect the
  8254 timer to the apic, even though its in the same silicon!  ARGH!
  This directly violates the ACPI spec.
2003-11-17 08:58:16 +00:00
John Baldwin
4311d1d368 Enable PCI interrupt routing for i386 SMP kernels. 2003-11-03 22:06:35 +00:00
Doug Rabson
aec21b56e8 Make the cardbus driver a derived class of the pci driver. In theory, this
should allow many of the pci methods to be re-staticised.
2003-11-01 12:45:03 +00:00
Mitsuru IWASAKI
526b5e659d Add pci_resume() to reestablish interrupt routing after
suspend/resume.
Especially after hibernation, interrupt routing went back to initial
status on some machines.
2003-09-17 08:32:44 +00:00
Scott Long
ec40a9f9d0 Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
Scott Long
cadbc399ea Remove most of the magic constants from the extcap parsing code. 2003-09-14 06:23:19 +00:00
John Baldwin
ab551d918c Replace another instance of PCIR_MAPS with PCIR_BAR(x).
Reminded by:	dfr
2003-09-03 15:24:31 +00:00
John Baldwin
e27951b29c Use PCIR_BAR(x) instead of PCIR_MAPS.
Glanced over by:	imp, gibbs
Tested by:		i386 LINT
2003-09-02 17:30:40 +00:00
Doug Rabson
d37a68d05a Don't try to enable io or memory access for non-standard resource
addresses. This stops resource allocations for e.g. amdpm failing - this
has its own special ways of enabling access.
2003-09-01 15:01:49 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
Warner Losh
b0cb115fb7 Prefer the uintXX_t to the u_intXX_t names. 2003-08-22 03:11:53 +00:00
Warner Losh
8d50cc0e3e Define PCI_MAXHDRTYPE to be 2. We know about header types 0, 1 and 2.
Update the MI device scanning code to use PCI_MAXHDRTYPE rather than
the hard coded 2.
2003-08-01 21:45:56 +00:00
John Baldwin
3f2a1b0656 Update the 'ps', 'show pci', and 'show ktr' ddb commands to use the new
pager callout instead of homerolling their own paging facility.
2003-07-31 17:29:42 +00:00
Thomas Moestl
3920999db7 Add a new PCI interface method, assign_interrupt, to determine the
interrupt to be used for a device. This is intended solely for internal
use of PCI bus implementations, and exists so that PCI bus drivers
implementing special interrupt assignment methods which require
additional work at the bus level to work right can be easily derived
from the generic driver (or any other one) without resorting to hacks.

It will be used in the sparc64 ofw_pcibus driver, which will be
committed shortly.

Make use of this method in the generic implementation, and add it to
the method table of bus drivers derived from the PCI one.

Reviewed by:	imp, -hackers
2003-07-01 14:08:33 +00:00
Thomas Moestl
036c2cfbfa Allow to write the intpin ivar using the pci_set_intpin() accessor. There
are some Sun PCI devices around which bogusly set intpin to 0, although
they use the intline mechanism; this allows the device driver to correct
that.

Reviewed by:	imp
2003-07-01 13:54:10 +00:00