Thomas Moestl a935ed4fae When sending cache flushing IPIs, don't try to IPI the triggering CPU ... itself; this causes undefined behaviour on UltraSPARCs. In particular, the interrupt packet data words will not necessarily be delivered correctly, which would result in a crash. This bug also caused the cache-flushing work to be done twice on the triggering CPU (when it did not cause crashes). Reviewed by: jake		2002-07-12 16:26:49 +00:00
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compile	Obrien created this directory, but I didn't cvs add cvsignore	2001-07-01 23:37:03 +00:00
conf	Remove ALT_BREAK_TO_DEBUGGER. This was inconsistent (both in form	2002-06-30 04:12:21 +00:00
ebus	Make the OpenFirmware interrupt mapping code more generic, to reduce	2002-03-24 02:11:06 +00:00
include	When sending cache flushing IPIs, don't try to IPI the triggering CPU	2002-07-12 16:26:49 +00:00
isa	Remove a debugging panic that was triggered when a resource that was out	2002-04-02 17:23:45 +00:00
pci	Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI	2002-06-12 19:20:57 +00:00
sbus	Revamp the busdma implementation a bit:	2002-03-24 02:50:53 +00:00
sparc64	thread_exit() requires PROC_LOCK to be held, so lock it.	2002-07-11 22:13:33 +00:00