2002-06-05 19:52:45 +00:00
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/*
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* Product specific probe and attach routines for:
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* aic7901 and aic7902 SCSI controllers
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*
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* Copyright (c) 1994-2001 Justin T. Gibbs.
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2002-08-31 06:52:27 +00:00
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* Copyright (c) 2000-2002 Adaptec Inc.
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2002-06-05 19:52:45 +00:00
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
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* $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#66 $
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2002-06-05 19:52:45 +00:00
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*
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* $FreeBSD$
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*/
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#ifdef __linux__
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#include "aic79xx_osm.h"
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#include "aic79xx_inline.h"
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#else
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#include <dev/aic7xxx/aic79xx_osm.h>
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#include <dev/aic7xxx/aic79xx_inline.h>
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#endif
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static __inline uint64_t
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ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
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{
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uint64_t id;
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id = subvendor
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| (subdevice << 16)
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| ((uint64_t)vendor << 32)
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| ((uint64_t)device << 48);
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return (id);
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}
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#define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
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#define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
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#define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
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#define ID_AIC7901 0x800F9005FFFF9005ull
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2002-08-31 06:52:27 +00:00
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#define ID_AIC7901A 0x801E9005FFFF9005ull
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2002-12-01 07:59:01 +00:00
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#define ID_AIC7901A_IROC 0x809E9005FFFF9005ull
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2002-08-31 06:52:27 +00:00
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#define ID_AHA_29320A 0x8000900500609005ull
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2002-12-01 07:59:01 +00:00
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#define ID_AHA_29320LP 0x8014900500449005ull
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#define ID_AHA_29320LP_IROC 0x8094900500449005ull
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2002-06-05 19:52:45 +00:00
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#define ID_AIC7902 0x801F9005FFFF9005ull
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2002-12-01 07:59:01 +00:00
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#define ID_AIC7902_IROC 0x809F9005FFFF9005ull
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#define ID_AIC7902_B 0x801D9005FFFF9005ull
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#define ID_AIC7902_B_IROC 0x809D9005FFFF9005ull
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2002-06-05 19:52:45 +00:00
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#define ID_AHA_39320 0x8010900500409005ull
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aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
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#define ID_AHA_39320A 0x8016900500409005ull
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2002-06-05 19:52:45 +00:00
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#define ID_AHA_39320D 0x8011900500419005ull
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2002-12-01 07:59:01 +00:00
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#define ID_AHA_39320D_B 0x801C900500419005ull
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#define ID_AHA_39320D_HP 0x8011900500AC0E11ull
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#define ID_AHA_39320D_B_HP 0x801C900500AC0E11ull
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2002-08-31 06:52:27 +00:00
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#define ID_AHA_29320 0x8012900500429005ull
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#define ID_AHA_29320B 0x8013900500439005ull
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2002-06-05 19:52:45 +00:00
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#define ID_AIC7902_PCI_REV_A4 0x3
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2002-08-31 06:52:27 +00:00
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#define ID_AIC7902_PCI_REV_B0 0x10
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2002-12-01 07:59:01 +00:00
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#define SUBID_HP 0x0E11
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2002-06-05 19:52:45 +00:00
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#define DEVID_9005_TYPE(id) ((id) & 0xF)
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#define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
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#define DEVID_9005_TYPE_HBA_2EXT 0x1 /* 2 External Ports */
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#define DEVID_9005_TYPE_IROC 0x8 /* Raid(0,1,10) Card */
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#define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
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#define DEVID_9005_MFUNC(id) ((id) & 0x10)
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#define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
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#define SUBID_9005_TYPE(id) ((id) & 0xF)
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#define SUBID_9005_TYPE_HBA 0x0 /* Standard Card */
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#define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
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#define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
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#define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
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#define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
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#define SUBID_9005_SEEPTYPE_NONE 0x0
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#define SUBID_9005_SEEPTYPE_4K 0x1
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2002-08-31 06:52:27 +00:00
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static ahd_device_setup_t ahd_aic7901A_setup;
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2002-12-01 07:59:01 +00:00
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static ahd_device_setup_t ahd_aic7902_setup;
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2002-06-05 19:52:45 +00:00
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struct ahd_pci_identity ahd_pci_ident_table [] =
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{
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2002-12-01 07:59:01 +00:00
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/* aic7901A based controllers */
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{
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ID_AHA_29320LP,
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ID_ALL_MASK,
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"Adaptec 29320LP Ultra320 SCSI adapter",
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ahd_aic7901A_setup
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},
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2002-06-05 19:52:45 +00:00
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{
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2002-08-31 06:52:27 +00:00
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ID_AHA_29320A,
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2002-06-05 19:52:45 +00:00
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ID_ALL_MASK,
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2002-08-31 06:52:27 +00:00
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"Adaptec 29320A Ultra320 SCSI adapter",
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2002-12-01 07:59:01 +00:00
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ahd_aic7901A_setup
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2002-06-05 19:52:45 +00:00
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},
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/* aic7902 based controllers */
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{
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ID_AHA_39320,
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ID_ALL_MASK,
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"Adaptec 39320 Ultra320 SCSI adapter",
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ahd_aic7902_setup
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},
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aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
{
|
|
|
|
|
ID_AHA_39320A,
|
|
|
|
|
ID_ALL_MASK,
|
|
|
|
|
"Adaptec 39320A Ultra320 SCSI adapter",
|
|
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
2002-06-05 19:52:45 +00:00
|
|
|
{
|
|
|
|
|
ID_AHA_39320D,
|
|
|
|
|
ID_ALL_MASK,
|
|
|
|
|
"Adaptec 39320D Ultra320 SCSI adapter",
|
|
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
|
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
ID_AHA_39320D_HP,
|
2002-06-05 19:52:45 +00:00
|
|
|
ID_ALL_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
2002-08-31 06:52:27 +00:00
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
ID_AHA_39320D_B,
|
2002-08-31 06:52:27 +00:00
|
|
|
ID_ALL_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec 39320D Ultra320 SCSI adapter",
|
2002-08-31 06:52:27 +00:00
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
|
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
ID_AHA_39320D_B_HP,
|
2002-08-31 06:52:27 +00:00
|
|
|
ID_ALL_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
|
2002-08-31 06:52:27 +00:00
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
|
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
ID_AHA_29320,
|
2002-08-31 06:52:27 +00:00
|
|
|
ID_ALL_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec 29320 Ultra320 SCSI adapter",
|
2002-08-31 06:52:27 +00:00
|
|
|
ahd_aic7902_setup
|
|
|
|
|
},
|
|
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
ID_AHA_29320B,
|
|
|
|
|
ID_ALL_MASK,
|
|
|
|
|
"Adaptec 29320B Ultra320 SCSI adapter",
|
|
|
|
|
ahd_aic7902_setup
|
2002-08-31 06:52:27 +00:00
|
|
|
},
|
2002-06-05 19:52:45 +00:00
|
|
|
/* Generic chip probes for devices we don't know 'exactly' */
|
|
|
|
|
{
|
2002-12-04 22:51:29 +00:00
|
|
|
ID_AIC7901A & ID_DEV_VENDOR_MASK,
|
|
|
|
|
ID_DEV_VENDOR_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec AIC7901A Ultra320 SCSI adapter",
|
|
|
|
|
ahd_aic7901A_setup
|
2002-06-05 19:52:45 +00:00
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
ID_AIC7902 & ID_9005_GENERIC_MASK,
|
|
|
|
|
ID_9005_GENERIC_MASK,
|
2002-12-01 07:59:01 +00:00
|
|
|
"Adaptec AIC7902 Ultra320 SCSI adapter",
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_aic7902_setup
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
|
|
|
|
|
|
|
|
|
|
#define DEVCONFIG 0x40
|
|
|
|
|
#define PCIXINITPAT 0x0000E000ul
|
|
|
|
|
#define PCIXINIT_PCI33_66 0x0000E000ul
|
|
|
|
|
#define PCIXINIT_PCIX50_66 0x0000C000ul
|
|
|
|
|
#define PCIXINIT_PCIX66_100 0x0000A000ul
|
|
|
|
|
#define PCIXINIT_PCIX100_133 0x00008000ul
|
|
|
|
|
#define PCI_BUS_MODES_INDEX(devconfig) \
|
|
|
|
|
(((devconfig) & PCIXINITPAT) >> 13)
|
|
|
|
|
static const char *pci_bus_modes[] =
|
|
|
|
|
{
|
|
|
|
|
"PCI bus mode unknown",
|
|
|
|
|
"PCI bus mode unknown",
|
|
|
|
|
"PCI bus mode unknown",
|
|
|
|
|
"PCI bus mode unknown",
|
|
|
|
|
"PCI-X 101-133Mhz",
|
|
|
|
|
"PCI-X 67-100Mhz",
|
|
|
|
|
"PCI-X 50-66Mhz",
|
|
|
|
|
"PCI 33 or 66Mhz"
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define TESTMODE 0x00000800ul
|
|
|
|
|
#define IRDY_RST 0x00000200ul
|
|
|
|
|
#define FRAME_RST 0x00000100ul
|
|
|
|
|
#define PCI64BIT 0x00000080ul
|
|
|
|
|
#define MRDCEN 0x00000040ul
|
|
|
|
|
#define ENDIANSEL 0x00000020ul
|
|
|
|
|
#define MIXQWENDIANEN 0x00000008ul
|
|
|
|
|
#define DACEN 0x00000004ul
|
|
|
|
|
#define STPWLEVEL 0x00000002ul
|
|
|
|
|
#define QWENDIANSEL 0x00000001ul
|
|
|
|
|
|
|
|
|
|
#define DEVCONFIG1 0x44
|
|
|
|
|
#define PREQDIS 0x01
|
|
|
|
|
|
|
|
|
|
#define CSIZE_LATTIME 0x0c
|
|
|
|
|
#define CACHESIZE 0x000000fful
|
|
|
|
|
#define LATTIME 0x0000ff00ul
|
|
|
|
|
|
|
|
|
|
static int ahd_check_extport(struct ahd_softc *ahd);
|
|
|
|
|
static void ahd_configure_termination(struct ahd_softc *ahd,
|
|
|
|
|
u_int adapter_control);
|
|
|
|
|
static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
|
|
|
|
|
|
|
|
|
|
struct ahd_pci_identity *
|
|
|
|
|
ahd_find_pci_device(ahd_dev_softc_t pci)
|
|
|
|
|
{
|
|
|
|
|
uint64_t full_id;
|
|
|
|
|
uint16_t device;
|
|
|
|
|
uint16_t vendor;
|
|
|
|
|
uint16_t subdevice;
|
|
|
|
|
uint16_t subvendor;
|
|
|
|
|
struct ahd_pci_identity *entry;
|
|
|
|
|
u_int i;
|
|
|
|
|
|
|
|
|
|
vendor = ahd_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
|
|
|
|
|
device = ahd_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
|
|
|
|
|
subvendor = ahd_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
|
|
|
|
|
subdevice = ahd_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
|
|
|
|
|
full_id = ahd_compose_id(device,
|
|
|
|
|
vendor,
|
|
|
|
|
subdevice,
|
|
|
|
|
subvendor);
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ahd_num_pci_devs; i++) {
|
|
|
|
|
entry = &ahd_pci_ident_table[i];
|
|
|
|
|
if (entry->full_id == (full_id & entry->id_mask)) {
|
|
|
|
|
/* Honor exclusion entries. */
|
|
|
|
|
if (entry->name == NULL)
|
|
|
|
|
return (NULL);
|
|
|
|
|
return (entry);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
return (NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
|
|
|
|
|
{
|
|
|
|
|
struct scb_data *shared_scb_data;
|
|
|
|
|
u_long l;
|
|
|
|
|
u_int command;
|
|
|
|
|
uint32_t devconfig;
|
|
|
|
|
uint16_t subvendor;
|
|
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
shared_scb_data = NULL;
|
2002-12-01 07:59:01 +00:00
|
|
|
ahd->description = entry->name;
|
|
|
|
|
/*
|
|
|
|
|
* Record if this is an HP board.
|
|
|
|
|
*/
|
|
|
|
|
subvendor = ahd_pci_read_config(ahd->dev_softc,
|
|
|
|
|
PCIR_SUBVEND_0, /*bytes*/2);
|
|
|
|
|
if (subvendor == SUBID_HP)
|
|
|
|
|
ahd->flags |= AHD_HP_BOARD;
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
error = entry->setup(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
|
|
|
|
|
if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
|
|
|
|
|
ahd->chip |= AHD_PCI;
|
|
|
|
|
/* Disable PCIX workarounds when running in PCI mode. */
|
|
|
|
|
ahd->bugs &= ~AHD_PCIX_BUG_MASK;
|
|
|
|
|
} else {
|
|
|
|
|
ahd->chip |= AHD_PCIX;
|
|
|
|
|
}
|
|
|
|
|
ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
|
|
|
|
|
|
|
|
|
|
ahd_power_state_change(ahd, AHD_POWER_STATE_D0);
|
|
|
|
|
|
|
|
|
|
error = ahd_pci_map_registers(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If we need to support high memory, enable dual
|
|
|
|
|
* address cycles. This bit must be set to enable
|
|
|
|
|
* high address bit generation even if we are on a
|
|
|
|
|
* 64bit bus (PCI64BIT set in devconfig).
|
|
|
|
|
*/
|
|
|
|
|
if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
|
|
|
|
|
uint32_t devconfig;
|
|
|
|
|
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: Enabling 39Bit Addressing\n",
|
|
|
|
|
ahd_name(ahd));
|
|
|
|
|
devconfig = ahd_pci_read_config(ahd->dev_softc,
|
|
|
|
|
DEVCONFIG, /*bytes*/4);
|
|
|
|
|
devconfig |= DACEN;
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, DEVCONFIG,
|
|
|
|
|
devconfig, /*bytes*/4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Ensure busmastering is enabled */
|
|
|
|
|
command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
|
|
|
|
|
command |= PCIM_CMD_BUSMASTEREN;
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/1);
|
|
|
|
|
|
|
|
|
|
error = ahd_softc_init(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
ahd->bus_intr = ahd_pci_intr;
|
|
|
|
|
|
|
|
|
|
error = ahd_reset(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
|
|
|
|
|
ahd->pci_cachesize =
|
|
|
|
|
ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
|
|
|
|
|
/*bytes*/1) & CACHESIZE;
|
|
|
|
|
ahd->pci_cachesize *= 4;
|
|
|
|
|
|
|
|
|
|
ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
|
|
|
|
|
/* See if we have a SEEPROM and perform auto-term */
|
|
|
|
|
error = ahd_check_extport(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
/* Core initialization */
|
|
|
|
|
error = ahd_init(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Allow interrupts now that we are completely setup.
|
|
|
|
|
*/
|
|
|
|
|
error = ahd_pci_map_int(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
ahd_list_lock(&l);
|
|
|
|
|
/*
|
|
|
|
|
* Link this softc in with all other ahd instances.
|
|
|
|
|
*/
|
|
|
|
|
ahd_softc_insert(ahd);
|
|
|
|
|
ahd_list_unlock(&l);
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
2002-12-01 07:59:01 +00:00
|
|
|
/*
|
|
|
|
|
* Perform some simple tests that should catch situations where
|
|
|
|
|
* our registers are invalidly mapped.
|
|
|
|
|
*/
|
|
|
|
|
int
|
|
|
|
|
ahd_pci_test_register_access(struct ahd_softc *ahd)
|
|
|
|
|
{
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_mode_state saved_modes;
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
uint32_t cmd;
|
2002-12-04 22:51:29 +00:00
|
|
|
int error;
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
uint8_t hcntrl;
|
2002-12-04 22:51:29 +00:00
|
|
|
|
|
|
|
|
saved_modes = ahd_save_modes(ahd);
|
|
|
|
|
error = EIO;
|
|
|
|
|
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
/*
|
|
|
|
|
* Enable PCI error interrupt status, but suppress NMIs
|
|
|
|
|
* generated by SERR raised due to target aborts.
|
|
|
|
|
*/
|
|
|
|
|
cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
|
|
|
|
|
cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
|
2002-12-01 07:59:01 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* First a simple test to see if any
|
|
|
|
|
* registers can be read. Reading
|
|
|
|
|
* HCNTRL has no side effects and has
|
|
|
|
|
* at least one bit that is guaranteed to
|
|
|
|
|
* be zero so it is a good register to
|
|
|
|
|
* use for this test.
|
|
|
|
|
*/
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
hcntrl = ahd_inb(ahd, HCNTRL);
|
|
|
|
|
if (hcntrl == 0xFF)
|
2002-12-04 22:51:29 +00:00
|
|
|
goto fail;
|
2002-12-01 07:59:01 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Next create a situation where write combining
|
|
|
|
|
* or read prefetching could be initiated by the
|
|
|
|
|
* CPU or host bridge. Our device does not support
|
|
|
|
|
* either, so look for data corruption and/or flaged
|
|
|
|
|
* PCI errors.
|
|
|
|
|
*/
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
|
|
|
|
|
while (ahd_is_paused(ahd) == 0)
|
|
|
|
|
;
|
|
|
|
|
ahd_outb(ahd, SEQCTL0, PERRORDIS);
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
|
|
|
|
|
if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
|
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
|
|
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
|
|
|
|
|
u_int targpcistat;
|
|
|
|
|
|
|
|
|
|
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
|
|
|
|
|
targpcistat = ahd_inb(ahd, TARGPCISTAT);
|
|
|
|
|
if ((targpcistat & STA) != 0)
|
|
|
|
|
goto fail;
|
|
|
|
|
}
|
2002-12-01 07:59:01 +00:00
|
|
|
|
2002-12-04 22:51:29 +00:00
|
|
|
error = 0;
|
2002-12-01 07:59:01 +00:00
|
|
|
|
2002-12-04 22:51:29 +00:00
|
|
|
fail:
|
2002-12-01 07:59:01 +00:00
|
|
|
if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
|
2002-12-04 22:51:29 +00:00
|
|
|
u_int targpcistat;
|
|
|
|
|
u_int pci_status1;
|
2002-12-01 07:59:01 +00:00
|
|
|
|
|
|
|
|
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
|
|
|
|
|
targpcistat = ahd_inb(ahd, TARGPCISTAT);
|
|
|
|
|
|
|
|
|
|
/* Silently clear any latched errors. */
|
|
|
|
|
ahd_outb(ahd, TARGPCISTAT, targpcistat);
|
|
|
|
|
pci_status1 = ahd_pci_read_config(ahd->dev_softc,
|
|
|
|
|
PCIR_STATUS + 1, /*bytes*/1);
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
|
|
|
|
|
pci_status1, /*bytes*/1);
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_outb(ahd, CLRINT, CLRPCIINT);
|
2002-12-01 07:59:01 +00:00
|
|
|
}
|
|
|
|
|
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_restore_modes(ahd, saved_modes);
|
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
2003-01-20 20:17:35 +00:00
|
|
|
ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
|
2002-12-04 22:51:29 +00:00
|
|
|
return (error);
|
2002-12-01 07:59:01 +00:00
|
|
|
}
|
|
|
|
|
|
2002-06-05 19:52:45 +00:00
|
|
|
/*
|
|
|
|
|
* Check the external port logic for a serial eeprom
|
|
|
|
|
* and termination/cable detection contrls.
|
|
|
|
|
*/
|
|
|
|
|
static int
|
|
|
|
|
ahd_check_extport(struct ahd_softc *ahd)
|
|
|
|
|
{
|
|
|
|
|
struct seeprom_config *sc;
|
|
|
|
|
u_int adapter_control;
|
|
|
|
|
int have_seeprom;
|
|
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
sc = ahd->seep_config;
|
|
|
|
|
have_seeprom = ahd_acquire_seeprom(ahd);
|
|
|
|
|
if (have_seeprom) {
|
|
|
|
|
u_int start_addr;
|
|
|
|
|
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: Reading SEEPROM...", ahd_name(ahd));
|
|
|
|
|
|
|
|
|
|
/* Address is always in units of 16bit words */
|
|
|
|
|
start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
|
|
|
|
|
|
|
|
|
|
error = ahd_read_seeprom(ahd, (uint16_t *)sc,
|
|
|
|
|
start_addr, sizeof(*sc)/2);
|
|
|
|
|
|
|
|
|
|
if (error != 0) {
|
|
|
|
|
printf("Unable to read SEEPROM\n");
|
|
|
|
|
have_seeprom = 0;
|
|
|
|
|
} else {
|
|
|
|
|
have_seeprom = ahd_verify_cksum(sc);
|
|
|
|
|
|
|
|
|
|
if (bootverbose) {
|
|
|
|
|
if (have_seeprom == 0)
|
|
|
|
|
printf ("checksum error\n");
|
|
|
|
|
else
|
|
|
|
|
printf ("done.\n");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
ahd_release_seeprom(ahd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!have_seeprom) {
|
|
|
|
|
u_int nvram_scb;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Pull scratch ram settings and treat them as
|
|
|
|
|
* if they are the contents of an seeprom if
|
|
|
|
|
* the 'ADPT', 'BIOS', or 'ASPI' signature is found
|
|
|
|
|
* in SCB 0xFF. We manually compose the data as 16bit
|
|
|
|
|
* values to avoid endian issues.
|
|
|
|
|
*/
|
|
|
|
|
ahd_set_scbptr(ahd, 0xFF);
|
|
|
|
|
nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
|
|
|
|
|
if (nvram_scb != 0xFF
|
|
|
|
|
&& ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
|
|
|
|
|
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
|
|
|
|
|
|| (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
|
|
|
|
|
&& ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
|
|
|
|
|
uint16_t *sc_data;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
ahd_set_scbptr(ahd, nvram_scb);
|
|
|
|
|
sc_data = (uint16_t *)sc;
|
|
|
|
|
for (i = 0; i < 64; i += 2)
|
|
|
|
|
*sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
|
|
|
|
|
have_seeprom = ahd_verify_cksum(sc);
|
|
|
|
|
if (have_seeprom)
|
|
|
|
|
ahd->flags |= AHD_SCB_CONFIG_USED;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#if AHD_DEBUG
|
|
|
|
|
if (have_seeprom != 0
|
|
|
|
|
&& (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
|
|
|
|
|
uint8_t *sc_data;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
printf("%s: Seeprom Contents:", ahd_name(ahd));
|
|
|
|
|
sc_data = (uint8_t *)sc;
|
|
|
|
|
for (i = 0; i < (sizeof(*sc)); i += 2)
|
|
|
|
|
printf("\n\t0x%.4x",
|
|
|
|
|
sc_data[i] | (sc_data[i+1] << 8));
|
|
|
|
|
printf("\n");
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
if (!have_seeprom) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: No SEEPROM available.\n", ahd_name(ahd));
|
|
|
|
|
ahd->flags |= AHD_USEDEFAULTS;
|
|
|
|
|
error = ahd_default_config(ahd);
|
|
|
|
|
adapter_control = CFAUTOTERM|CFSEAUTOTERM;
|
|
|
|
|
free(ahd->seep_config, M_DEVBUF);
|
|
|
|
|
ahd->seep_config = NULL;
|
|
|
|
|
} else {
|
|
|
|
|
error = ahd_parse_cfgdata(ahd, sc);
|
|
|
|
|
adapter_control = sc->adapter_control;
|
|
|
|
|
}
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
|
|
|
|
|
ahd_configure_termination(ahd, adapter_control);
|
|
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
|
|
|
|
|
{
|
|
|
|
|
int error;
|
|
|
|
|
u_int sxfrctl1;
|
|
|
|
|
uint8_t termctl;
|
|
|
|
|
uint32_t devconfig;
|
|
|
|
|
|
|
|
|
|
devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
|
|
|
|
|
devconfig &= ~STPWLEVEL;
|
2002-08-31 06:52:27 +00:00
|
|
|
if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
|
2002-06-05 19:52:45 +00:00
|
|
|
devconfig |= STPWLEVEL;
|
2002-08-31 06:52:27 +00:00
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: STPWLEVEL is %s\n",
|
|
|
|
|
ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
|
|
|
|
|
|
|
|
|
|
/* Make sure current sensing is off. */
|
|
|
|
|
if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
|
|
|
|
|
(void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Read to sense. Write to set.
|
|
|
|
|
*/
|
|
|
|
|
error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
|
|
|
|
|
if ((adapter_control & CFAUTOTERM) == 0) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: Manual Primary Termination\n",
|
|
|
|
|
ahd_name(ahd));
|
|
|
|
|
termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
|
|
|
|
|
if ((adapter_control & CFSTERM) != 0)
|
|
|
|
|
termctl |= FLX_TERMCTL_ENPRILOW;
|
|
|
|
|
if ((adapter_control & CFWSTERM) != 0)
|
|
|
|
|
termctl |= FLX_TERMCTL_ENPRIHIGH;
|
|
|
|
|
} else if (error != 0) {
|
|
|
|
|
printf("%s: Primary Auto-Term Sensing failed! "
|
|
|
|
|
"Using Defaults.\n", ahd_name(ahd));
|
|
|
|
|
termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if ((adapter_control & CFSEAUTOTERM) == 0) {
|
|
|
|
|
if (bootverbose)
|
|
|
|
|
printf("%s: Manual Secondary Termination\n",
|
|
|
|
|
ahd_name(ahd));
|
|
|
|
|
termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
|
|
|
|
|
if ((adapter_control & CFSELOWTERM) != 0)
|
|
|
|
|
termctl |= FLX_TERMCTL_ENSECLOW;
|
|
|
|
|
if ((adapter_control & CFSEHIGHTERM) != 0)
|
|
|
|
|
termctl |= FLX_TERMCTL_ENSECHIGH;
|
|
|
|
|
} else if (error != 0) {
|
|
|
|
|
printf("%s: Secondary Auto-Term Sensing failed! "
|
|
|
|
|
"Using Defaults.\n", ahd_name(ahd));
|
|
|
|
|
termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now set the termination based on what we found.
|
|
|
|
|
*/
|
|
|
|
|
sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
|
|
|
|
|
if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
|
|
|
|
|
ahd->flags |= AHD_TERM_ENB_A;
|
|
|
|
|
sxfrctl1 |= STPWEN;
|
|
|
|
|
}
|
|
|
|
|
/* Must set the latch once in order to be effective. */
|
|
|
|
|
ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
|
|
|
|
|
ahd_outb(ahd, SXFRCTL1, sxfrctl1);
|
|
|
|
|
|
|
|
|
|
error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
|
|
|
|
|
if (error != 0) {
|
|
|
|
|
printf("%s: Unable to set termination settings!\n",
|
|
|
|
|
ahd_name(ahd));
|
|
|
|
|
} else if (bootverbose) {
|
|
|
|
|
printf("%s: Primary High byte termination %sabled\n",
|
|
|
|
|
ahd_name(ahd),
|
|
|
|
|
(termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
|
|
|
|
|
|
|
|
|
|
printf("%s: Primary Low byte termination %sabled\n",
|
|
|
|
|
ahd_name(ahd),
|
|
|
|
|
(termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
|
|
|
|
|
|
|
|
|
|
printf("%s: Secondary High byte termination %sabled\n",
|
|
|
|
|
ahd_name(ahd),
|
|
|
|
|
(termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
|
|
|
|
|
|
|
|
|
|
printf("%s: Secondary Low byte termination %sabled\n",
|
|
|
|
|
ahd_name(ahd),
|
|
|
|
|
(termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
|
|
|
|
|
}
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define DPE 0x80
|
|
|
|
|
#define SSE 0x40
|
|
|
|
|
#define RMA 0x20
|
|
|
|
|
#define RTA 0x10
|
|
|
|
|
#define STA 0x08
|
|
|
|
|
#define DPR 0x01
|
|
|
|
|
|
|
|
|
|
static const char *split_status_source[] =
|
|
|
|
|
{
|
|
|
|
|
"DFF0",
|
|
|
|
|
"DFF1",
|
|
|
|
|
"OVLY",
|
|
|
|
|
"CMC",
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const char *pci_status_source[] =
|
|
|
|
|
{
|
|
|
|
|
"DFF0",
|
|
|
|
|
"DFF1",
|
|
|
|
|
"SG",
|
|
|
|
|
"CMC",
|
|
|
|
|
"OVLY",
|
|
|
|
|
"NONE",
|
|
|
|
|
"MSI",
|
|
|
|
|
"TARG"
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const char *split_status_strings[] =
|
|
|
|
|
{
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
"%s: Received split response in %s.\n",
|
2002-06-05 19:52:45 +00:00
|
|
|
"%s: Received split completion error message in %s\n",
|
|
|
|
|
"%s: Receive overrun in %s\n",
|
|
|
|
|
"%s: Count not complete in %s\n",
|
|
|
|
|
"%s: Split completion data bucket in %s\n",
|
|
|
|
|
"%s: Split completion address error in %s\n",
|
|
|
|
|
"%s: Split completion byte count error in %s\n",
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
"%s: Signaled Target-abort to early terminate a split in %s\n"
|
2002-06-05 19:52:45 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const char *pci_status_strings[] =
|
|
|
|
|
{
|
|
|
|
|
"%s: Data Parity Error has been reported via PERR# in %s\n",
|
|
|
|
|
"%s: Target initial wait state error in %s\n",
|
|
|
|
|
"%s: Split completion read data parity error in %s\n",
|
|
|
|
|
"%s: Split completion address attribute parity error in %s\n",
|
|
|
|
|
"%s: Received a Target Abort in %s\n",
|
|
|
|
|
"%s: Received a Master Abort in %s\n",
|
|
|
|
|
"%s: Signal System Error Detected in %s\n",
|
|
|
|
|
"%s: Address or Write Phase Parity Error Detected in %s.\n"
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
ahd_pci_intr(struct ahd_softc *ahd)
|
|
|
|
|
{
|
|
|
|
|
uint8_t pci_status[8];
|
|
|
|
|
ahd_mode_state saved_modes;
|
|
|
|
|
u_int pci_status1;
|
|
|
|
|
u_int intstat;
|
|
|
|
|
u_int i;
|
|
|
|
|
u_int reg;
|
|
|
|
|
|
|
|
|
|
intstat = ahd_inb(ahd, INTSTAT);
|
|
|
|
|
|
|
|
|
|
if ((intstat & SPLTINT) != 0)
|
|
|
|
|
ahd_pci_split_intr(ahd, intstat);
|
|
|
|
|
|
|
|
|
|
if ((intstat & PCIINT) == 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
printf("%s: PCI error Interrupt\n", ahd_name(ahd));
|
|
|
|
|
saved_modes = ahd_save_modes(ahd);
|
|
|
|
|
ahd_dump_card_state(ahd);
|
|
|
|
|
ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
|
|
|
|
|
for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
|
|
|
|
|
|
|
|
|
|
if (i == 5)
|
|
|
|
|
continue;
|
|
|
|
|
pci_status[i] = ahd_inb(ahd, reg);
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
/* Clear latched errors. So our interrupt deasserts. */
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_outb(ahd, reg, pci_status[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
u_int bit;
|
|
|
|
|
|
|
|
|
|
if (i == 5)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
for (bit = 0; bit < 8; bit++) {
|
|
|
|
|
|
|
|
|
|
if ((pci_status[i] & (0x1 << bit)) != 0) {
|
|
|
|
|
static const char *s;
|
|
|
|
|
|
|
|
|
|
s = pci_status_strings[bit];
|
|
|
|
|
if (i == 7/*TARG*/ && bit == 3)
|
2002-12-04 22:51:29 +00:00
|
|
|
s = "%s: Signaled Target Abort\n";
|
2002-06-05 19:52:45 +00:00
|
|
|
printf(s, ahd_name(ahd), pci_status_source[i]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
pci_status1 = ahd_pci_read_config(ahd->dev_softc,
|
|
|
|
|
PCIR_STATUS + 1, /*bytes*/1);
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
|
|
|
|
|
pci_status1, /*bytes*/1);
|
|
|
|
|
ahd_restore_modes(ahd, saved_modes);
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_outb(ahd, CLRINT, CLRPCIINT);
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_unpause(ahd);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
|
|
|
|
|
{
|
|
|
|
|
uint8_t split_status[4];
|
|
|
|
|
uint8_t split_status1[4];
|
|
|
|
|
uint8_t sg_split_status[2];
|
|
|
|
|
uint8_t sg_split_status1[2];
|
|
|
|
|
ahd_mode_state saved_modes;
|
|
|
|
|
u_int i;
|
|
|
|
|
uint16_t pcix_status;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Check for splits in all modes. Modes 0 and 1
|
|
|
|
|
* additionally have SG engine splits to look at.
|
|
|
|
|
*/
|
|
|
|
|
pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
|
|
|
|
|
/*bytes*/2);
|
|
|
|
|
printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
|
|
|
|
|
ahd_name(ahd), pcix_status);
|
|
|
|
|
saved_modes = ahd_save_modes(ahd);
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
ahd_set_modes(ahd, i, i);
|
|
|
|
|
|
|
|
|
|
split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
|
|
|
|
|
split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
/* Clear latched errors. So our interrupt deasserts. */
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
|
|
|
|
|
ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
|
|
|
|
|
if (i != 0)
|
|
|
|
|
continue;
|
|
|
|
|
sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
|
|
|
|
|
sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
/* Clear latched errors. So our interrupt deasserts. */
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
|
|
|
|
|
ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
|
u_int bit;
|
|
|
|
|
|
|
|
|
|
for (bit = 0; bit < 8; bit++) {
|
|
|
|
|
|
|
|
|
|
if ((split_status[i] & (0x1 << bit)) != 0) {
|
|
|
|
|
static const char *s;
|
|
|
|
|
|
|
|
|
|
s = split_status_strings[bit];
|
|
|
|
|
printf(s, ahd_name(ahd),
|
|
|
|
|
split_status_source[i]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (i != 0)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if ((sg_split_status[i] & (0x1 << bit)) != 0) {
|
|
|
|
|
static const char *s;
|
|
|
|
|
|
|
|
|
|
s = split_status_strings[bit];
|
|
|
|
|
printf(s, ahd_name(ahd), "SG");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
/*
|
|
|
|
|
* Clear PCI-X status bits.
|
|
|
|
|
*/
|
|
|
|
|
ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
|
|
|
|
|
pcix_status, /*bytes*/2);
|
2002-12-04 22:51:29 +00:00
|
|
|
ahd_outb(ahd, CLRINT, CLRSPLTINT);
|
2002-06-05 19:52:45 +00:00
|
|
|
ahd_restore_modes(ahd, saved_modes);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
2002-12-01 07:59:01 +00:00
|
|
|
ahd_aic7901A_setup(struct ahd_softc *ahd)
|
2002-06-05 19:52:45 +00:00
|
|
|
{
|
2002-12-01 07:59:01 +00:00
|
|
|
int error;
|
|
|
|
|
|
|
|
|
|
error = ahd_aic7902_setup(ahd);
|
|
|
|
|
if (error != 0)
|
|
|
|
|
return (error);
|
|
|
|
|
ahd->chip = AHD_AIC7901A;
|
2002-06-05 19:52:45 +00:00
|
|
|
return (0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int
|
|
|
|
|
ahd_aic7902_setup(struct ahd_softc *ahd)
|
|
|
|
|
{
|
|
|
|
|
ahd_dev_softc_t pci;
|
|
|
|
|
u_int rev;
|
|
|
|
|
|
|
|
|
|
pci = ahd->dev_softc;
|
|
|
|
|
rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
|
2002-08-31 06:52:27 +00:00
|
|
|
if (rev < ID_AIC7902_PCI_REV_A4) {
|
2002-06-05 19:52:45 +00:00
|
|
|
printf("%s: Unable to attach to unsupported chip revision %d\n",
|
|
|
|
|
ahd_name(ahd), rev);
|
|
|
|
|
ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/1);
|
|
|
|
|
return (ENXIO);
|
|
|
|
|
}
|
2002-12-01 07:59:01 +00:00
|
|
|
ahd->channel = ahd_get_pci_function(pci) + 'A';
|
|
|
|
|
ahd->chip = AHD_AIC7902;
|
|
|
|
|
ahd->features = AHD_AIC7902_FE;
|
2002-06-05 19:52:45 +00:00
|
|
|
if (rev < ID_AIC7902_PCI_REV_B0) {
|
|
|
|
|
/*
|
|
|
|
|
* Enable A series workarounds.
|
|
|
|
|
*/
|
|
|
|
|
ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
|
|
|
|
|
| AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
|
|
|
|
|
| AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
|
|
|
|
|
| AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
|
|
|
|
|
| AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
|
2002-08-31 06:52:27 +00:00
|
|
|
| AHD_PCIX_CHIPRST_BUG|AHD_PKTIZED_STATUS_BUG
|
2002-09-26 22:54:00 +00:00
|
|
|
| AHD_PKT_LUN_BUG|AHD_MDFF_WSCBPTR_BUG
|
|
|
|
|
| AHD_REG_SLOW_SETTLE_BUG|AHD_SET_MODE_BUG
|
2002-12-01 07:59:01 +00:00
|
|
|
| AHD_BUSFREEREV_BUG|AHD_NONPACKFIFO_BUG
|
|
|
|
|
| AHD_PACED_NEGTABLE_BUG;
|
2002-06-05 19:52:45 +00:00
|
|
|
|
2002-12-01 07:59:01 +00:00
|
|
|
/*
|
|
|
|
|
* IO Cell paramter setup.
|
|
|
|
|
*/
|
|
|
|
|
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
|
2002-08-31 06:52:27 +00:00
|
|
|
|
2002-12-01 07:59:01 +00:00
|
|
|
if ((ahd->flags & AHD_HP_BOARD) == 0)
|
|
|
|
|
AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
|
|
|
|
|
} else {
|
|
|
|
|
u_int devconfig1;
|
|
|
|
|
|
|
|
|
|
ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
|
|
|
|
|
| AHD_NEW_DFCNTRL_OPTS;
|
|
|
|
|
ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_ABORT_LQI_BUG
|
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have
already handled the SCSIPERR. During some streaming operations
this status can be delayed until the stream ends. Without this
change, the driver would complain about a "Missing case in
ahd_handle_scsiint".
In the LQOBUSFREE handler...
Don't return the LQOMGR back to the idle state until after
we have cleaned up ENSELO and any status related to this
selection. The last thing we need is the LQO manager starting
another select-out before we have updated the execution queue.
It is not clear whether the LQOMGR would, or would not
start a new selection early.
Make sure ENSELO is off prior to clearing SELDO by flushing
device writes.
Move assignment of the next target SCB pointer inside of
an if to make the code clearer. The effect is the same.
Dump card state in both "Unexpected PKT busfree" paths.
In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1.
That register only exists in the SCSI mode. Also set the mode
explicitly to the SCSI mode after chip reset due to paranoia.
Re-arrange code so that SXFRCTL1 is restored as quickly after the
chip reset as possible.
S/G structurs must be 8byte aligned. Make this official by saying
so in our DMA tag.
Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come
true. This can cause a CIO bus lockup if a PCI or PCI-X error
occurs while the stretch is occurring - the host cannot service
the PCI-X error since the CIO bus is locked out and SHVALID will
never resolve. The stretch was added in the Rev B to simplify the
wait for SHVALID to resolve, but the code to do this in the open
source sequencer is so simple it was never removed.
Consistently use MAX_OFFSET for the user max syncrate set from
non-volatile storage. This ensures that the offset does not
conflict with AH?_OFFSET_UNKNOWN.
Have ahd_pause_and_flushwork set the mode to ensure that it has
access to the registers it checks. Also modify the checking of
intstat so that the check against 0xFF can actually succeed if
the INT_PEND mask is something other than 0xFF. Although there
are no cardbus U320 controllers, this check may be needed to
recover from a hot-plug PCI removal that occurs without informing
the driver.
Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes
an infinite loop at card initialization if the cacheline size is 0.
aic79xx.h:
Add AHD_EARLY_REQ_BUG bug flag.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the
curr->offset can never be, unlike '0' which we previously used.
This fixes code that only checks for a non-zero offset to
determine if a sync negotiation is required since it will fire
in the unknown case even if the goal is async.
aic79xx.reg:
Add comments for LQISTAT bits indicating their names in the 7902
data book. We use slightly different and more descriptive names
in the firmware.
Fix spelling errors.
Include the CDB's length just after the CDB pointer in the DMA'ed
CDB case.
aic79xx.seq:
Update comments regarding rundown of the GSFIFO to reflect reality.
Fix spelling errors.
Since we use an 8byte address and 1 byte length, shorten the size
of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes.
Remove code that, assuming the abort pending feature worked, would
set MK_MESSAGE in the SCB's control byte on completion to catch
invalid reselections. Since we don't see interrupts for completed
selections, this status update could occur prior to us noticing the
SELDO. The "select-out" queue logic will get confused by the
MK_MESSAGE bit being set as this is used to catch packatized
connections where we select-out with ATN. Since the abort pending
feature doesn't work on any released controllers yet, this code was
never executed.
Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ
assertions just because they were asserted within the bus settle delay
window. This allows us to tolerate devices like the GEM318 that
violate the SCSI spec.
Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit
should have no effect, but who knows...
On the Rev A, we must wait for HDMAENACK before loading additional
segments to avoid clobbering the address of the first segment in
the S/G FIFO. This resolves data-corruption issues with certain
IBM (now Hitachi) and Fujitsu U320 drives.
Rearrange calc_residual to avoid an extra jmp instruction.
On RevA Silicon, if the target returns us to data-out after we
have already trained for data-out, it is possible for us to
transition the free running clock to data-valid before the required
100ns P1 setup time (8 P1 assertions in fast-160 mode). This will
only happen if this L-Q is a continuation of a data transfer for
which we have already prefetched data into our FIFO (LQ/Data
followed by LQ/Data for the same write transaction). This can
cause some target implementations to miss the first few data
transfers on the bus. We detect this situation by noticing that
this is the first data transfer after an LQ (LQIWORKONLQ true),
that the data transfer is a continuation of a transfer already
setup in our FIFO (SAVEPTRS interrupt), and that the transaction
is a write (DIRECTION set in DFCNTRL). The delay is performed by
disabling SCSIEN until we see the first REQ from the target.
Only compile in snapshot savepointers handler for RevA silicon
where it is enabled.
Handle the cfg4icmd packetized interrupt. We just need to load
the address and count, start the DMA, and CLRCHN once the transfer
is complete.
Fix an oversight in the overrun handler for packetized status
operations. We need to wait for either CTXTDONE or an overrun
when checking for an overrun. The previous code did not wait
and thus could decide that no overrun had occurred even though
an overrun will occur on the next data-valid req. Add some
comment to this section for clarity.
Use LAST_SEG_DONE instead of LASTSDONE for testing transfer
completion in the packetized status case. LASTSDONE may come up
more quickly since it only records completion on the SCSI side,
but since LAST_SEG_DONE is used everywhere else (and needs to be),
this is less confusing.
Add a missing invalidation of the longjmp address in the non-pack
handler. This code needs additional review.
aic79xx_inline.h:
Fix spelling error.
aic79xx_osm.c:
Set the cdb length for CDBs dma'ed from host memory.
Add a comment indicating that, should CAM start supporting cdbs
larger than 16bytes, the driver could store the CDB in the status
buffer.
aic79xx_pci.c:
Add a table entry for the 39320A.
Added a missing comma to an error string table.
Fix spelling errors.
2003-02-27 23:23:16 +00:00
|
|
|
| AHD_INTCOLLISION_BUG|AHD_EARLY_REQ_BUG;
|
2002-12-01 07:59:01 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* IO Cell paramter setup.
|
|
|
|
|
*/
|
|
|
|
|
AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
|
|
|
|
|
AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
|
|
|
|
|
AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Set the PREQDIS bit for H2B which disables some workaround
|
|
|
|
|
* that doesn't work on regular PCI busses.
|
|
|
|
|
* XXX - Find out exactly what this does from the hardware
|
|
|
|
|
* folks!
|
|
|
|
|
*/
|
|
|
|
|
devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
|
|
|
|
|
ahd_pci_write_config(pci, DEVCONFIG1,
|
|
|
|
|
devconfig1|PREQDIS, /*bytes*/1);
|
|
|
|
|
devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
|
|
|
|
|
}
|
2002-08-31 06:52:27 +00:00
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
|
}
|
