2013-02-05 02:25:13 +00:00
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/*-
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2014-03-25 08:31:47 +00:00
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* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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2013-02-05 02:25:13 +00:00
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2012 Luiz Otavio O Souza.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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2015-01-31 19:32:14 +00:00
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#include <dev/gpio/gpiobusvar.h>
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2013-02-05 02:25:13 +00:00
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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2016-11-14 11:52:22 +00:00
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#include <dev/fdt/fdt_pinctrl.h>
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2013-02-05 02:25:13 +00:00
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2016-08-17 21:44:02 +00:00
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#include <arm/allwinner/aw_machdep.h>
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2016-02-17 18:28:03 +00:00
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#include <arm/allwinner/allwinner_pinctrl.h>
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2016-04-23 13:59:18 +00:00
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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2016-02-17 18:28:03 +00:00
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2016-07-11 20:09:17 +00:00
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#if defined(__aarch64__)
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#include "opt_soc.h"
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#endif
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2013-02-05 02:25:13 +00:00
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#include "gpio_if.h"
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#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
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2016-04-23 13:59:18 +00:00
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#define A10_GPIO_NONE 0
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#define A10_GPIO_PULLUP 1
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#define A10_GPIO_PULLDOWN 2
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2013-02-19 02:01:35 +00:00
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2016-04-23 13:59:18 +00:00
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#define A10_GPIO_INPUT 0
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#define A10_GPIO_OUTPUT 1
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2013-02-19 02:01:35 +00:00
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2016-04-23 13:59:18 +00:00
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#define AW_GPIO_DRV_MASK 0x3
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#define AW_GPIO_PUD_MASK 0x3
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2016-02-17 18:28:03 +00:00
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2016-04-23 13:59:18 +00:00
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#define AW_PINCTRL 1
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#define AW_R_PINCTRL 2
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2013-02-05 02:25:13 +00:00
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2016-02-17 18:28:03 +00:00
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/* Defined in a10_padconf.c */
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#ifdef SOC_ALLWINNER_A10
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extern const struct allwinner_padconf a10_padconf;
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#endif
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2016-07-08 23:38:25 +00:00
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/* Defined in a13_padconf.c */
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#ifdef SOC_ALLWINNER_A13
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extern const struct allwinner_padconf a13_padconf;
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#endif
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2016-02-17 18:28:03 +00:00
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/* Defined in a20_padconf.c */
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#ifdef SOC_ALLWINNER_A20
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extern const struct allwinner_padconf a20_padconf;
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#endif
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2016-02-25 12:17:41 +00:00
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/* Defined in a31_padconf.c */
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#ifdef SOC_ALLWINNER_A31
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extern const struct allwinner_padconf a31_padconf;
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#endif
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/* Defined in a31s_padconf.c */
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#ifdef SOC_ALLWINNER_A31S
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extern const struct allwinner_padconf a31s_padconf;
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#endif
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2016-04-23 13:59:18 +00:00
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#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
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extern const struct allwinner_padconf a31_r_padconf;
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#endif
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2017-01-04 03:35:39 +00:00
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/* Defined in a33_padconf.c */
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#ifdef SOC_ALLWINNER_A33
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extern const struct allwinner_padconf a33_padconf;
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#endif
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2016-05-13 18:20:54 +00:00
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/* Defined in h3_padconf.c */
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#ifdef SOC_ALLWINNER_H3
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extern const struct allwinner_padconf h3_padconf;
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extern const struct allwinner_padconf h3_r_padconf;
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#endif
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2016-05-05 09:41:57 +00:00
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/* Defined in a83t_padconf.c */
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#ifdef SOC_ALLWINNER_A83T
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extern const struct allwinner_padconf a83t_padconf;
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extern const struct allwinner_padconf a83t_r_padconf;
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#endif
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2016-07-11 20:09:17 +00:00
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/* Defined in a64_padconf.c */
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#ifdef SOC_ALLWINNER_A64
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extern const struct allwinner_padconf a64_padconf;
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extern const struct allwinner_padconf a64_r_padconf;
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#endif
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2016-04-23 13:59:18 +00:00
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static struct ofw_compat_data compat_data[] = {
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#ifdef SOC_ALLWINNER_A10
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{"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf},
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#endif
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2016-07-08 23:38:25 +00:00
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#ifdef SOC_ALLWINNER_A13
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{"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_padconf},
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#endif
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2016-04-23 13:59:18 +00:00
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#ifdef SOC_ALLWINNER_A20
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{"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A31
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{"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A31S
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{"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf},
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#endif
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#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
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{"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf},
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2016-05-05 09:41:57 +00:00
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#endif
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2017-01-04 03:35:39 +00:00
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#ifdef SOC_ALLWINNER_A33
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{"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_padconf},
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#endif
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2016-05-05 09:41:57 +00:00
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#ifdef SOC_ALLWINNER_A83T
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{"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf},
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{"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf},
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2016-05-13 18:20:54 +00:00
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#endif
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#ifdef SOC_ALLWINNER_H3
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{"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf},
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{"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf},
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2016-07-11 20:09:17 +00:00
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#endif
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#ifdef SOC_ALLWINNER_A64
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{"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf},
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{"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf},
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2016-04-23 13:59:18 +00:00
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#endif
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{NULL, 0}
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};
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2017-09-26 20:23:09 +00:00
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struct clk_list {
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TAILQ_ENTRY(clk_list) next;
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clk_t clk;
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};
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2016-04-23 13:59:18 +00:00
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struct a10_gpio_softc {
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device_t sc_dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource * sc_mem_res;
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struct resource * sc_irq_res;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_intrhand;
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const struct allwinner_padconf * padconf;
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2017-09-26 20:23:09 +00:00
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TAILQ_HEAD(, clk_list) clk_list;
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2016-04-23 13:59:18 +00:00
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};
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2015-07-13 18:19:26 +00:00
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#define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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2013-02-05 02:25:13 +00:00
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2015-07-13 18:19:26 +00:00
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#define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
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2013-02-05 02:25:13 +00:00
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#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
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2015-07-13 18:19:26 +00:00
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#define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
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#define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
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2013-02-05 02:25:13 +00:00
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#define A10_GPIO_GP_INT_CFG0 0x200
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#define A10_GPIO_GP_INT_CFG1 0x204
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#define A10_GPIO_GP_INT_CFG2 0x208
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#define A10_GPIO_GP_INT_CFG3 0x20c
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#define A10_GPIO_GP_INT_CTL 0x210
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#define A10_GPIO_GP_INT_STA 0x214
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#define A10_GPIO_GP_INT_DEB 0x218
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Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
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static int a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value);
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static int a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
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2017-09-16 14:08:20 +00:00
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static int a10_gpio_pin_get_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int *value);
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static int a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int value);
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Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
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2013-02-05 02:25:13 +00:00
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#define A10_GPIO_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
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#define A10_GPIO_READ(_sc, _off) \
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bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
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static uint32_t
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a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
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{
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uint32_t bank, func, offset;
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2015-07-13 18:19:26 +00:00
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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2016-02-17 18:28:03 +00:00
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if (pin > sc->padconf->npins)
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return (0);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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2013-02-05 02:25:13 +00:00
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offset = ((pin & 0x07) << 2);
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2015-07-13 18:19:26 +00:00
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func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
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2016-08-17 10:20:36 +00:00
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return ((func >> offset) & 0x7);
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2013-02-05 02:25:13 +00:00
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}
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2016-07-08 23:08:59 +00:00
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static int
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2013-02-05 02:25:13 +00:00
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a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
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{
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2015-07-13 18:19:26 +00:00
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uint32_t bank, data, offset;
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2013-02-05 02:25:13 +00:00
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2016-07-08 23:08:59 +00:00
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/* Check if the function exists in the padconf data */
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if (sc->padconf->pins[pin].functions[f] == NULL)
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return (EINVAL);
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2013-02-05 02:25:13 +00:00
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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2016-02-17 18:28:03 +00:00
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bank = sc->padconf->pins[pin].port;
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|
|
pin = sc->padconf->pins[pin].pin;
|
2013-02-05 02:25:13 +00:00
|
|
|
offset = ((pin & 0x07) << 2);
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
|
2013-02-05 02:25:13 +00:00
|
|
|
data &= ~(7 << offset);
|
|
|
|
data |= (f << offset);
|
2015-07-13 18:19:26 +00:00
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data);
|
2016-07-08 23:08:59 +00:00
|
|
|
|
|
|
|
return (0);
|
2015-07-13 18:19:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin)
|
|
|
|
{
|
|
|
|
uint32_t bank, offset, val;
|
|
|
|
|
|
|
|
/* Must be called with lock held. */
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
2015-07-13 18:19:26 +00:00
|
|
|
offset = ((pin & 0x0f) << 1);
|
|
|
|
|
|
|
|
val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
|
|
|
|
|
2016-08-17 10:20:36 +00:00
|
|
|
return ((val >> offset) & AW_GPIO_PUD_MASK);
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
|
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
uint32_t bank, offset, val;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
/* Must be called with lock held. */
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
2013-02-05 02:25:13 +00:00
|
|
|
offset = ((pin & 0x0f) << 1);
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
|
2016-02-17 18:28:03 +00:00
|
|
|
val &= ~(AW_GPIO_PUD_MASK << offset);
|
2013-02-05 02:25:13 +00:00
|
|
|
val |= (state << offset);
|
2015-07-13 18:19:26 +00:00
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val);
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
2016-08-17 10:20:36 +00:00
|
|
|
static uint32_t
|
|
|
|
a10_gpio_get_drv(struct a10_gpio_softc *sc, uint32_t pin)
|
|
|
|
{
|
|
|
|
uint32_t bank, offset, val;
|
|
|
|
|
|
|
|
/* Must be called with lock held. */
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
|
|
|
offset = ((pin & 0x0f) << 1);
|
|
|
|
|
|
|
|
val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
|
|
|
|
|
|
|
|
return ((val >> offset) & AW_GPIO_DRV_MASK);
|
|
|
|
}
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
static void
|
|
|
|
a10_gpio_set_drv(struct a10_gpio_softc *sc, uint32_t pin, uint32_t drive)
|
|
|
|
{
|
|
|
|
uint32_t bank, offset, val;
|
|
|
|
|
|
|
|
/* Must be called with lock held. */
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
|
|
|
offset = ((pin & 0x0f) << 1);
|
|
|
|
|
|
|
|
val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
|
|
|
|
val &= ~(AW_GPIO_DRV_MASK << offset);
|
|
|
|
val |= (drive << offset);
|
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val);
|
|
|
|
}
|
|
|
|
|
2016-07-08 23:08:59 +00:00
|
|
|
static int
|
2015-07-13 18:19:26 +00:00
|
|
|
a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags)
|
2013-02-05 02:25:13 +00:00
|
|
|
{
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
u_int val;
|
2016-07-08 23:08:59 +00:00
|
|
|
int err = 0;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
/* Must be called with lock held. */
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
2013-02-05 02:25:13 +00:00
|
|
|
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
if (pin > sc->padconf->npins)
|
|
|
|
return (EINVAL);
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
/* Manage input/output. */
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
if (flags & GPIO_PIN_INPUT) {
|
|
|
|
err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT);
|
|
|
|
} else if (flags & GPIO_PIN_OUTPUT) {
|
|
|
|
if (flags & GPIO_PIN_PRESET_LOW) {
|
2017-09-16 14:08:20 +00:00
|
|
|
a10_gpio_pin_set_locked(sc, pin, 0);
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
} else if (flags & GPIO_PIN_PRESET_HIGH) {
|
2017-09-16 14:08:20 +00:00
|
|
|
a10_gpio_pin_set_locked(sc, pin, 1);
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
} else {
|
|
|
|
/* Read the pin and preset output to current state. */
|
2016-07-08 23:08:59 +00:00
|
|
|
err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT);
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
if (err == 0) {
|
2017-09-16 14:08:20 +00:00
|
|
|
a10_gpio_pin_get_locked(sc, pin, &val);
|
|
|
|
a10_gpio_pin_set_locked(sc, pin, val);
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (err == 0)
|
|
|
|
err = a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT);
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
2016-07-08 23:08:59 +00:00
|
|
|
if (err)
|
|
|
|
return (err);
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
/* Manage Pull-up/pull-down. */
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
if (flags & GPIO_PIN_PULLUP)
|
|
|
|
a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP);
|
|
|
|
else if (flags & GPIO_PIN_PULLDOWN)
|
|
|
|
a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN);
|
|
|
|
else
|
2015-07-13 18:19:26 +00:00
|
|
|
a10_gpio_set_pud(sc, pin, A10_GPIO_NONE);
|
2016-07-08 23:08:59 +00:00
|
|
|
|
|
|
|
return (0);
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
2015-01-31 19:32:14 +00:00
|
|
|
static device_t
|
|
|
|
a10_gpio_get_bus(device_t dev)
|
|
|
|
{
|
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
return (sc->sc_busdev);
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_pin_max(device_t dev, int *maxpin)
|
|
|
|
{
|
2016-02-17 18:28:03 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
*maxpin = sc->padconf->npins - 1;
|
2013-02-05 02:25:13 +00:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
|
|
|
|
{
|
2016-02-17 18:28:03 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
*caps = A10_GPIO_DEFAULT_CAPS;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
|
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2016-08-17 10:20:36 +00:00
|
|
|
uint32_t func;
|
|
|
|
uint32_t pud;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
2016-08-17 10:20:36 +00:00
|
|
|
func = a10_gpio_get_function(sc, pin);
|
|
|
|
switch (func) {
|
|
|
|
case A10_GPIO_INPUT:
|
|
|
|
*flags = GPIO_PIN_INPUT;
|
|
|
|
break;
|
|
|
|
case A10_GPIO_OUTPUT:
|
|
|
|
*flags = GPIO_PIN_OUTPUT;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
*flags = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
pud = a10_gpio_get_pud(sc, pin);
|
|
|
|
switch (pud) {
|
|
|
|
case A10_GPIO_PULLDOWN:
|
|
|
|
*flags |= GPIO_PIN_PULLDOWN;
|
|
|
|
break;
|
|
|
|
case A10_GPIO_PULLUP:
|
|
|
|
*flags |= GPIO_PIN_PULLUP;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
|
|
|
|
{
|
2016-02-17 18:28:03 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin >= sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
snprintf(name, GPIOMAXNAME - 1, "%s",
|
|
|
|
sc->padconf->pins[pin].name);
|
2015-07-13 18:19:26 +00:00
|
|
|
name[GPIOMAXNAME - 1] = '\0';
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
|
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2016-07-08 23:08:59 +00:00
|
|
|
int err;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin > sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
A10_GPIO_LOCK(sc);
|
2016-07-08 23:08:59 +00:00
|
|
|
err = a10_gpio_pin_configure(sc, pin, flags);
|
2015-07-13 18:19:26 +00:00
|
|
|
A10_GPIO_UNLOCK(sc);
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-07-08 23:08:59 +00:00
|
|
|
return (err);
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2017-09-16 14:08:20 +00:00
|
|
|
a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin,
|
|
|
|
unsigned int value)
|
2013-02-05 02:25:13 +00:00
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
uint32_t bank, data;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2017-09-16 14:08:20 +00:00
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
if (pin > sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
|
|
|
|
if (value)
|
2015-07-13 18:19:26 +00:00
|
|
|
data |= (1 << pin);
|
2013-02-05 02:25:13 +00:00
|
|
|
else
|
2015-07-13 18:19:26 +00:00
|
|
|
data &= ~(1 << pin);
|
2013-02-05 02:25:13 +00:00
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2017-09-16 14:08:20 +00:00
|
|
|
a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
|
2013-02-05 02:25:13 +00:00
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2017-09-16 14:08:20 +00:00
|
|
|
int ret;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
2017-09-16 14:08:20 +00:00
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
|
|
|
ret = a10_gpio_pin_set_locked(sc, pin, value);
|
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_get_locked(struct a10_gpio_softc *sc,uint32_t pin,
|
|
|
|
unsigned int *val)
|
|
|
|
{
|
|
|
|
uint32_t bank, reg_data;
|
|
|
|
|
|
|
|
A10_GPIO_LOCK_ASSERT(sc);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
if (pin > sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
|
2015-07-13 18:19:26 +00:00
|
|
|
*val = (reg_data & (1 << pin)) ? 1 : 0;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2017-09-16 14:08:20 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
|
|
|
|
{
|
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
|
|
|
ret = a10_gpio_pin_get_locked(sc, pin, val);
|
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
|
|
{
|
2015-07-13 18:19:26 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
uint32_t bank, data;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (pin > sc->padconf->npins)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (EINVAL);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
bank = sc->padconf->pins[pin].port;
|
|
|
|
pin = sc->padconf->pins[pin].pin;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
|
|
|
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
|
2015-07-13 18:19:26 +00:00
|
|
|
if (data & (1 << pin))
|
|
|
|
data &= ~(1 << pin);
|
2013-02-05 02:25:13 +00:00
|
|
|
else
|
2015-07-13 18:19:26 +00:00
|
|
|
data |= (1 << pin);
|
2013-02-05 02:25:13 +00:00
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
|
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
|
|
|
|
uint32_t change_pins, uint32_t *orig_pins)
|
|
|
|
{
|
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
uint32_t bank, data, pin;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (first_pin > sc->padconf->npins)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We require that first_pin refers to the first pin in a bank, because
|
|
|
|
* this API is not about convenience, it's for making a set of pins
|
|
|
|
* change simultaneously (required) with reasonably high performance
|
|
|
|
* (desired); we need to do a read-modify-write on a single register.
|
|
|
|
*/
|
|
|
|
bank = sc->padconf->pins[first_pin].port;
|
|
|
|
pin = sc->padconf->pins[first_pin].pin;
|
|
|
|
if (pin != 0)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
|
|
|
data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
|
|
|
|
if ((clear_pins | change_pins) != 0)
|
|
|
|
A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank),
|
|
|
|
(data & ~clear_pins) ^ change_pins);
|
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
|
|
|
|
if (orig_pins != NULL)
|
|
|
|
*orig_pins = data;
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
|
|
|
|
uint32_t *pin_flags)
|
|
|
|
{
|
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
uint32_t bank, pin;
|
|
|
|
int err;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if (first_pin > sc->padconf->npins)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
bank = sc->padconf->pins[first_pin].port;
|
|
|
|
if (sc->padconf->pins[first_pin].pin != 0)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The configuration for a bank of pins is scattered among several
|
|
|
|
* registers; we cannot g'tee to simultaneously change the state of all
|
|
|
|
* the pins in the flags array. So just loop through the array
|
|
|
|
* configuring each pin for now. If there was a strong need, it might
|
|
|
|
* be possible to support some limited simultaneous config, such as
|
|
|
|
* adjacent groups of 8 pins that line up the same as the config regs.
|
|
|
|
*/
|
|
|
|
for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) {
|
|
|
|
if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT))
|
|
|
|
err = a10_gpio_pin_configure(sc, pin, pin_flags[pin]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
static int
|
|
|
|
aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < sc->padconf->npins; i++)
|
|
|
|
if (!strcmp(pinname, sc->padconf->pins[i].name))
|
|
|
|
return i;
|
|
|
|
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
|
|
|
|
if (sc->padconf->pins[pin].functions[i] &&
|
|
|
|
!strcmp(func, sc->padconf->pins[pin].functions[i]))
|
|
|
|
return (i);
|
|
|
|
|
|
|
|
return (-1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
|
|
|
|
{
|
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
phandle_t node;
|
|
|
|
const char **pinlist = NULL;
|
|
|
|
char *pin_function = NULL;
|
|
|
|
uint32_t pin_drive, pin_pull;
|
|
|
|
int pins_nb, pin_num, pin_func, i, ret;
|
|
|
|
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
node = OF_node_from_xref(cfgxref);
|
|
|
|
ret = 0;
|
|
|
|
|
|
|
|
/* Getting all prop for configuring pins */
|
2017-06-19 06:30:04 +00:00
|
|
|
pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist);
|
|
|
|
if (pins_nb <= 0) {
|
|
|
|
pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins",
|
|
|
|
&pinlist);
|
|
|
|
if (pins_nb <= 0)
|
|
|
|
return (ENOENT);
|
|
|
|
}
|
|
|
|
if (OF_getprop_alloc(node, "function",
|
2016-02-17 18:28:03 +00:00
|
|
|
sizeof(*pin_function),
|
|
|
|
(void **)&pin_function) == -1) {
|
2017-06-19 06:30:04 +00:00
|
|
|
if (OF_getprop_alloc(node, "allwinner,function",
|
|
|
|
sizeof(*pin_function),
|
|
|
|
(void **)&pin_function) == -1) {
|
|
|
|
ret = ENOENT;
|
|
|
|
goto out;
|
|
|
|
}
|
2016-02-17 18:28:03 +00:00
|
|
|
}
|
2017-06-19 06:30:04 +00:00
|
|
|
if (OF_getencprop(node, "drive",
|
2016-02-17 18:28:03 +00:00
|
|
|
&pin_drive, sizeof(pin_drive)) == -1) {
|
2017-06-19 06:30:04 +00:00
|
|
|
if (OF_getencprop(node, "allwinner,drive",
|
|
|
|
&pin_drive, sizeof(pin_drive)) == -1) {
|
|
|
|
ret = ENOENT;
|
|
|
|
goto out;
|
|
|
|
}
|
2016-02-17 18:28:03 +00:00
|
|
|
}
|
2017-06-19 06:30:04 +00:00
|
|
|
if (OF_getencprop(node, "pull",
|
2016-02-17 18:28:03 +00:00
|
|
|
&pin_pull, sizeof(pin_pull)) == -1) {
|
2017-06-19 06:30:04 +00:00
|
|
|
if (OF_getencprop(node, "allwinner,pull",
|
|
|
|
&pin_pull, sizeof(pin_pull)) == -1) {
|
|
|
|
ret = ENOENT;
|
|
|
|
goto out;
|
|
|
|
}
|
2016-02-17 18:28:03 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Configure each pin to the correct function, drive and pull */
|
|
|
|
for (i = 0; i < pins_nb; i++) {
|
|
|
|
pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
|
|
|
|
if (pin_num == -1) {
|
|
|
|
ret = ENOENT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
pin_func = aw_find_pin_func(sc, pin_num, pin_function);
|
|
|
|
if (pin_func == -1) {
|
|
|
|
ret = ENOENT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
A10_GPIO_LOCK(sc);
|
2016-08-17 10:20:36 +00:00
|
|
|
|
|
|
|
if (a10_gpio_get_function(sc, pin_num) != pin_func)
|
|
|
|
a10_gpio_set_function(sc, pin_num, pin_func);
|
|
|
|
if (a10_gpio_get_drv(sc, pin_num) != pin_drive)
|
|
|
|
a10_gpio_set_drv(sc, pin_num, pin_drive);
|
2016-08-17 13:09:31 +00:00
|
|
|
if (a10_gpio_get_pud(sc, pin_num) != pin_pull &&
|
2016-08-23 00:46:22 +00:00
|
|
|
(pin_pull == A10_GPIO_PULLUP ||
|
|
|
|
pin_pull == A10_GPIO_PULLDOWN))
|
2016-08-17 10:20:36 +00:00
|
|
|
a10_gpio_set_pud(sc, pin_num, pin_pull);
|
2016-02-17 18:28:03 +00:00
|
|
|
A10_GPIO_UNLOCK(sc);
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
2016-05-13 22:28:02 +00:00
|
|
|
OF_prop_free(pinlist);
|
|
|
|
OF_prop_free(pin_function);
|
2016-02-17 18:28:03 +00:00
|
|
|
return (ret);
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_probe(device_t dev)
|
|
|
|
{
|
2014-02-02 19:17:28 +00:00
|
|
|
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
|
|
return (ENXIO);
|
|
|
|
|
2016-02-10 09:19:29 +00:00
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
2013-02-05 02:25:13 +00:00
|
|
|
return (ENXIO);
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
|
2013-02-05 02:25:13 +00:00
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_attach(device_t dev)
|
|
|
|
{
|
2016-04-23 13:59:18 +00:00
|
|
|
int rid, error;
|
2013-02-05 02:25:13 +00:00
|
|
|
phandle_t gpio;
|
2015-07-13 18:19:26 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
2017-09-26 20:23:09 +00:00
|
|
|
struct clk_list *clkp, *clkp_tmp;
|
2016-04-23 13:59:18 +00:00
|
|
|
clk_t clk;
|
2017-09-26 20:23:09 +00:00
|
|
|
hwreset_t rst = NULL;
|
|
|
|
int off, err;
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
sc = device_get_softc(dev);
|
2013-02-05 02:25:13 +00:00
|
|
|
sc->sc_dev = dev;
|
|
|
|
|
2015-07-13 18:19:26 +00:00
|
|
|
mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN);
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
|
|
RF_ACTIVE);
|
|
|
|
if (!sc->sc_mem_res) {
|
|
|
|
device_printf(dev, "cannot allocate memory window\n");
|
2015-01-31 12:17:07 +00:00
|
|
|
goto fail;
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
|
|
|
|
sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
|
|
|
|
|
|
|
|
rid = 0;
|
|
|
|
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
|
|
RF_ACTIVE);
|
|
|
|
if (!sc->sc_irq_res) {
|
|
|
|
device_printf(dev, "cannot allocate interrupt\n");
|
2015-01-31 12:17:07 +00:00
|
|
|
goto fail;
|
2013-02-05 02:25:13 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Find our node. */
|
|
|
|
gpio = ofw_bus_get_node(sc->sc_dev);
|
|
|
|
if (!OF_hasprop(gpio, "gpio-controller"))
|
|
|
|
/* Node is not a GPIO controller. */
|
|
|
|
goto fail;
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
/* Use the right pin data for the current SoC */
|
2016-04-23 13:59:18 +00:00
|
|
|
sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev,
|
|
|
|
compat_data)->ocd_data;
|
|
|
|
|
2016-07-10 18:28:15 +00:00
|
|
|
if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
|
2016-04-23 13:59:18 +00:00
|
|
|
error = hwreset_deassert(rst);
|
|
|
|
if (error != 0) {
|
|
|
|
device_printf(dev, "cannot de-assert reset\n");
|
|
|
|
return (error);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-09-26 20:23:09 +00:00
|
|
|
TAILQ_INIT(&sc->clk_list);
|
|
|
|
for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) {
|
|
|
|
err = clk_enable(clk);
|
|
|
|
if (err != 0) {
|
|
|
|
device_printf(dev, "Could not enable clock %s\n",
|
|
|
|
clk_get_name(clk));
|
|
|
|
goto fail;
|
2016-04-23 13:59:18 +00:00
|
|
|
}
|
2017-09-26 20:23:09 +00:00
|
|
|
clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO);
|
|
|
|
clkp->clk = clk;
|
|
|
|
TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next);
|
2016-02-17 18:28:03 +00:00
|
|
|
}
|
|
|
|
|
2016-03-17 08:57:41 +00:00
|
|
|
sc->sc_busdev = gpiobus_attach_bus(dev);
|
|
|
|
if (sc->sc_busdev == NULL)
|
|
|
|
goto fail;
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
/*
|
|
|
|
* Register as a pinctrl device
|
|
|
|
*/
|
2017-06-19 06:30:04 +00:00
|
|
|
fdt_pinctrl_register(dev, "pins");
|
|
|
|
fdt_pinctrl_configure_tree(dev);
|
2016-02-17 18:28:03 +00:00
|
|
|
fdt_pinctrl_register(dev, "allwinner,pins");
|
|
|
|
fdt_pinctrl_configure_tree(dev);
|
|
|
|
|
2015-01-31 19:32:14 +00:00
|
|
|
return (0);
|
2013-02-05 02:25:13 +00:00
|
|
|
|
|
|
|
fail:
|
|
|
|
if (sc->sc_irq_res)
|
|
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
|
|
if (sc->sc_mem_res)
|
|
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
2015-01-31 12:17:07 +00:00
|
|
|
mtx_destroy(&sc->sc_mtx);
|
|
|
|
|
2017-09-26 20:23:09 +00:00
|
|
|
/* Disable clock */
|
|
|
|
TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) {
|
|
|
|
err = clk_disable(clkp->clk);
|
|
|
|
if (err != 0)
|
|
|
|
device_printf(dev, "Could not disable clock %s\n",
|
|
|
|
clk_get_name(clkp->clk));
|
|
|
|
err = clk_release(clkp->clk);
|
|
|
|
if (err != 0)
|
|
|
|
device_printf(dev, "Could not release clock %s\n",
|
|
|
|
clk_get_name(clkp->clk));
|
|
|
|
TAILQ_REMOVE(&sc->clk_list, clkp, next);
|
|
|
|
free(clkp, M_DEVBUF);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Assert resets */
|
|
|
|
if (rst) {
|
|
|
|
hwreset_assert(rst);
|
|
|
|
hwreset_release(rst);
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
return (ENXIO);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
a10_gpio_detach(device_t dev)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (EBUSY);
|
|
|
|
}
|
|
|
|
|
2015-07-11 21:09:43 +00:00
|
|
|
static phandle_t
|
|
|
|
a10_gpio_get_node(device_t dev, device_t bus)
|
|
|
|
{
|
|
|
|
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
|
|
return (ofw_bus_get_node(dev));
|
|
|
|
}
|
|
|
|
|
2015-08-30 22:38:06 +00:00
|
|
|
static int
|
|
|
|
a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
|
|
|
|
pcell_t *gpios, uint32_t *pin, uint32_t *flags)
|
|
|
|
{
|
2016-02-17 18:28:03 +00:00
|
|
|
struct a10_gpio_softc *sc;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
sc = device_get_softc(bus);
|
2015-08-30 22:38:06 +00:00
|
|
|
|
|
|
|
/* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
|
2016-02-17 18:28:03 +00:00
|
|
|
for (i = 0; i < sc->padconf->npins; i++)
|
|
|
|
if (sc->padconf->pins[i].port == gpios[0] &&
|
|
|
|
sc->padconf->pins[i].pin == gpios[1]) {
|
|
|
|
*pin = i;
|
|
|
|
break;
|
|
|
|
}
|
2015-08-30 22:38:06 +00:00
|
|
|
*flags = gpios[gcells - 1];
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
static device_method_t a10_gpio_methods[] = {
|
|
|
|
/* Device interface */
|
|
|
|
DEVMETHOD(device_probe, a10_gpio_probe),
|
|
|
|
DEVMETHOD(device_attach, a10_gpio_attach),
|
|
|
|
DEVMETHOD(device_detach, a10_gpio_detach),
|
|
|
|
|
|
|
|
/* GPIO protocol */
|
2015-01-31 19:32:14 +00:00
|
|
|
DEVMETHOD(gpio_get_bus, a10_gpio_get_bus),
|
2013-02-05 02:25:13 +00:00
|
|
|
DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
|
|
|
|
DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
|
|
|
|
DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
|
|
|
|
DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
|
|
|
|
DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
|
|
|
|
DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
|
|
|
|
DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
|
|
|
|
DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
|
Add gpio methods to read/write/configure up to 32 pins simultaneously.
Sometimes it is necessary to combine several gpio pins into an ad-hoc bus
and manipulate the pins as a group. In such cases manipulating the pins
individualy is not an option, because the value on the "bus" assumes
potentially-invalid intermediate values as each pin is changed in turn. Note
that the "bus" may be something as simple as a bi-color LED where changing
colors requires changing both gpio pins at once, or something as complex as
a bitbanged multiplexed address/data bus connected to a microcontroller.
In addition to the absolute requirement of simultaneously changing the
output values of driven pins, a desirable feature of these new methods is to
provide a higher-performance mechanism for reading and writing multiple
pins, especially from userland where pin-at-a-time access incurs a noticible
syscall time penalty.
These new interfaces are NOT intended to abstract away all the ugly details
of how gpio is implemented on any given platform. In fact, to use these
properly you absolutely must know something about how the gpio hardware is
organized. Typically there are "banks" of gpio pins controlled by registers
which group several pins together. A bank may be as small as 2 pins or as
big as "all the pins on the device, hundreds of them." In the latter case, a
driver might support this interface by allowing access to any 32 adjacent
pins within the overall collection. Or, more likely, any 32 adjacent pins
starting at any multiple of 32. Whatever the hardware restrictions may be,
you would need to understand them to use this interface.
In additional to defining the interfaces, two example implementations are
included here, for imx5/6, and allwinner. These represent the two primary
types of gpio hardware drivers. imx6 has multiple gpio devices, each
implementing a single bank of 32 pins. Allwinner implements a single large
gpio number space from 1-n pins, and the driver internally translates that
linear number space to a bank+pin scheme based on how the pins are grouped
into control registers. The allwinner implementation imposes the restriction
that the first_pin argument to the new functions must always be pin 0 of a
bank.
Differential Revision: https://reviews.freebsd.org/D11810
2017-09-10 18:08:25 +00:00
|
|
|
DEVMETHOD(gpio_pin_access_32, a10_gpio_pin_access_32),
|
|
|
|
DEVMETHOD(gpio_pin_config_32, a10_gpio_pin_config_32),
|
2015-08-30 22:38:06 +00:00
|
|
|
DEVMETHOD(gpio_map_gpios, a10_gpio_map_gpios),
|
2013-02-05 02:25:13 +00:00
|
|
|
|
2015-07-11 21:09:43 +00:00
|
|
|
/* ofw_bus interface */
|
|
|
|
DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node),
|
|
|
|
|
2016-02-17 18:28:03 +00:00
|
|
|
/* fdt_pinctrl interface */
|
|
|
|
DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
|
|
|
|
|
2013-02-05 02:25:13 +00:00
|
|
|
DEVMETHOD_END
|
|
|
|
};
|
|
|
|
|
|
|
|
static devclass_t a10_gpio_devclass;
|
|
|
|
|
|
|
|
static driver_t a10_gpio_driver = {
|
|
|
|
"gpio",
|
|
|
|
a10_gpio_methods,
|
|
|
|
sizeof(struct a10_gpio_softc),
|
|
|
|
};
|
|
|
|
|
2016-02-10 09:19:29 +00:00
|
|
|
EARLY_DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0,
|
2016-07-21 13:26:39 +00:00
|
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|