Commit Graph

1940 Commits

Author SHA1 Message Date
Konstantin Belousov
90edf67ecf POSIX states that #include <signal.h> shall make both mcontext_t and
ucontext_t available.  Our code even has XXX comment about this.

Add a bit of compliance by moving struct __ucontext definition into
sys/_ucontext.h and including it into signal.h and sys/ucontext.h.

Several machine/ucontext.h headers were changed to use namespace-safe
types (like uint64_t->__uint64_t) to not depend on sys/types.h.
struct __stack_t from sys/signal.h is made always visible in private
namespace to satisfy sys/_ucontext.h requirements.

Apparently mips _types.h pollutes global namespace with f_register_t
type definition.  This commit does not try to fix the issue.

PR:	207079
Reported and tested by:	Ting-Wei Lan <lantw44@gmail.com>
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
2016-02-12 07:38:19 +00:00
Andrew Turner
34096f3c06 Include the correct header to get a phandle_t needed by ofw_bus_if.h. While
here only include opt_platform.h once.

Sponsored by:	ABT Systems Ltd
2016-02-11 16:43:23 +00:00
Adrian Chadd
314d3ca236 Make bus_space_generic properly map/unmap memory (using pmap_mapdev and
pmap_unmapdev respectively) so that resources are properly managed.

This is work originally done by kan@.  Stanislav picked it up as part
of his Mediatek SoC work.

Tested:

* Carambola2, AR933x SoC

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan
Differential Revision:	https://reviews.freebsd.org/D5184
2016-02-11 06:24:34 +00:00
Adrian Chadd
6d525d0af8 Migrate the other MIPS24K SoC cores to use the CPU_MIPS24K option. 2016-02-11 06:23:02 +00:00
Adrian Chadd
67a2f29041 Missing commit - remove MIPS fdt bus space.
Differential Revision:	https://reviews.freebsd.org/D5184
2016-02-11 06:19:58 +00:00
Adrian Chadd
7519c628d3 Remove bus space fdt for MIPS.
This was originall done by kan@.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan
Differential Revision:	https://reviews.freebsd.org/D5184
2016-02-11 06:19:32 +00:00
Adrian Chadd
055ddb0304 Convert MIPS nexus and mips_pic to BUS_PASS
Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan
Differential Revision:	https://reviews.freebsd.org/D5196
2016-02-11 06:15:43 +00:00
Adrian Chadd
4d125f57e1 Teach the MIPS ticker to attach itself properly when using INTRNG.
Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan
Differential Revision:	https://reviews.freebsd.org/D5183
2016-02-11 06:13:53 +00:00
Adrian Chadd
9a8d0c1f0c Begin the MIPS_INTRNG support.
This is a prelude to intr-ng support for MIPS boards that need it -
notably the CI20 port from kan@ that's upcoming, but also work that
Stanislav is doing for the Mediatek platforms.

This is the initial platform dependent bits in include/intr.h, some
#defines for the nexus code for the intrng initialisation/runtime
bits, some changed naming (which I'll fix later to be the same, much
like what I did for ARM intr-ng) in exception.S, and the first cut
at a PIC.

Stanislav and I refactored out the common code for intrng support,
so the mips intrng definitions are quite small (sys/mips/include/intr.h.)

This is all work done by kan@, which stanislav has been cherry picking
into common code for his mediatek chipset work.

Tested:

* Carambola2 - no regressions (not intr-ng though!)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	kan (original author)
Differential Revision:	https://reviews.freebsd.org/D5182
2016-02-11 06:09:27 +00:00
Gleb Smirnoff
b28cc462ad Include sys/_task.h into uma_int.h, so that taskqueue.h isn't a
requirement for uma_int.h.

Suggested by:	jhb
2016-02-09 20:22:35 +00:00
Ruslan Bukin
46c9b07f22 Fix build. 2016-02-04 11:52:53 +00:00
Gleb Smirnoff
6c95c7903c Fix build. 2016-02-04 03:55:41 +00:00
Adrian Chadd
1436226800 Use MIPS24K now.
Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D5079
2016-02-02 16:25:53 +00:00
Adrian Chadd
ceb51257dd Use CPU_MIPS24K now in AR933x based boards.
I'll flip on other boards as i test them.

Tested:

* AR9331, Carambola 2
2016-02-02 16:22:35 +00:00
Adrian Chadd
56f9ec0685 Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for
clearing hazards.

This revision makes currently known MIPS32 Release 2 and Release 3 CPUs use
the EHB instruction when clearing hazards. So far the MIPS 74K and MIPS1004K
 (somewhat) were already using the EHB. Now we add more r2 and r3 CPUs to
this list.

Also, for the cases of MIPS coherent processing systems (currently 1004K,
1074K, interAptiv and proAptiv) - define proper CCA attributes.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5078
2016-02-02 16:00:42 +00:00
Adrian Chadd
04b5e02371 Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options
This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K

It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV

CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.

I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5077
2016-02-02 07:47:38 +00:00
Michal Meloun
cdf4ec6873 EHCI: Make core reset and port speed reading more generic.
Use driver settable callbacks for handling of:
- core post reset
- reading actual port speed

Typically, OTG enabled EHCI cores wants setting of USBMODE register,
but this register is not defined in EHCI specification and different
cores can have it on different offset.

Also, for cores with TT extension, actual port speed must be determinable.
But again, EHCI specification not covers this so this patch provides
function for two most common variant of speed bits layout.

Reviewed by: hselasky
Differential Revision: https://reviews.freebsd.org/D5088
2016-01-28 14:11:59 +00:00
John Baldwin
aa949be551 Convert ss_sp in stack_t and sigstack to void *.
POSIX requires these members to be of type void * rather than the
char * inherited from 4BSD.  NetBSD and OpenBSD both changed their
fields to void * back in 1998.  No new build failures were reported
via an exp-run.

PR:		206503 (exp-run)
Reviewed by:	kib
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D5092
2016-01-27 17:55:01 +00:00
Justin Hibbits
2dd1bdf183 Convert rman to use rman_res_t instead of u_long
Summary:
Migrate to using the semi-opaque type rman_res_t to specify rman resources.  For
now, this is still compatible with u_long.

This is step one in migrating rman to use uintmax_t for resources instead of
u_long.

Going forward, this could feasibly be used to specify architecture-specific
definitions of resource ranges, rather than baking a specific integer type into
the API.

This change has been broken out to facilitate MFC'ing drivers back to 10 without
breaking ABI.

Reviewed By: jhb
Sponsored by:	Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5075
2016-01-27 02:23:54 +00:00
Warner Losh
c8719df5f9 Add a comment about why at is turned off in the exception handler.
Only k0 and k1 may be touched until we save registers somewhere.

MFC After: 2 days
2016-01-26 18:39:23 +00:00
Mark Johnston
00b0fb8757 Remove a duplicate setting of the AH_DEBUG_ALQ option. 2016-01-26 01:16:45 +00:00
Andrew Turner
3184de419d Stop calling fdt_immr_addr from the xlp startup code. It's used to set
fdt_immr_{va,pa,size}, but these are not used outside a single ARM SoC.
2016-01-22 12:00:56 +00:00
Brooks Davis
bd3f34d4ba Shift saved floating point registers up in jmp_buf.
sigmask_t is 128-bits so requires two slots.

Approved by:	CheriBSD (93699cb9b6e73980ac369e379cea9772c9494ccc)
MFC after:	1 week
Sponsored by:	DARPA, AFRL
2016-01-20 22:23:08 +00:00
Dmitry Chagin
038c720553 Implement vsyscall hack. Prior to 2.13 glibc uses vsyscall
instead of vdso. An upcoming linux_base-c6 needs it.

Differential Revision:  https://reviews.freebsd.org/D1090

Reviewed by:	kib, trasz
MFC after:	1 week
2016-01-09 20:18:53 +00:00
Ian Lepore
69dcb7e771 Make the 'env' directive described in config(5) work on all architectures,
providing compiled-in static environment data that is used instead of any
data passed in from a boot loader.

Previously 'env' worked only on i386 and arm xscale systems, because it
required the MD startup code to examine the global envmode variable and
decide whether to use static_env or an environment obtained from the boot
loader, and set the global kern_envp accordingly.  Most startup code wasn't
doing so.  Making things even more complex, some mips startup code uses an
alternate scheme that involves calling init_static_kenv() to pass an empty
buffer and its size, then uses a series of kern_setenv() calls to populate
that buffer.

Now all MD startup code calls init_static_kenv(), and that routine provides
a single point where envmode is checked and the decision is made whether to
use the compiled-in static_kenv or the values provided by the MD code.

The routine also continues to serve its original purpose for mips; if a
non-zero buffer size is passed the routine installs the empty buffer ready
to accept kern_setenv() values.  Now if the size is zero, the provided buffer
full of existing env data is installed.  A NULL pointer can be passed if the
boot loader provides no env data; this allows the static env to be installed
if envmode is set to do so.

Most of the work here is a near-mechanical change to call the init function
instead of directly setting kern_envp.  A notable exception is in xen/pv.c;
that code was originally installing a buffer full of preformatted env data
along with its non-zero size (like mips code does), which would have allowed
kern_setenv() calls to wipe out the preformatted data.  Now it passes a zero
for the size so that the buffer of data it installs is treated as
non-writeable.
2016-01-02 02:53:48 +00:00
Adrian Chadd
50bf167022 Fix missing path conversion from the previous commit to shuffle mdio around.
It turns out the recent work to cut down the number of atheros kernels built
didnt include one with ARGE_MDIO defined..
2015-12-27 07:39:44 +00:00
Kevin Lo
ddb1359877 Fix typo (s/harware/hardware/) 2015-12-25 14:51:36 +00:00
Adrian Chadd
d5c2c0134b Add initial configuration files for the MT7620 and RT5350 SoCs.
These are all works in progress.  Notably - no wifi support just yet!

I've booted the MT7620 on a TP-Link Archer C2 via tftpboot.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-25 00:58:41 +00:00
Adrian Chadd
43747185a0 Add missing device rename. 2015-12-24 22:27:00 +00:00
Adrian Chadd
ba1ae59a17 [rt305x] Add initial RT5350 and MT7620 glue.
* Add in chipset awareness to the obio bus layout (ie, which devices are
  where);
* Add in some USB OTG changes to be aware of the newer stuff;
* Add in a configurable primary console - some chips use the normal UART,
  some use UARTLITE.

Tested (by Stanislav);

* RT3050 (NFS)
* RT5350 (NFS, MFS)
* MT7620 (USB)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:40:10 +00:00
Adrian Chadd
f9133e1d31 [MT7620] add ehci/ohci USB support.
The newer chips don't use OTG; they're more traditional USB.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:36:08 +00:00
Adrian Chadd
0f4da49e43 [MT7620] add SPI device support.
Submitted by:	Alexander A. Mityaev <sansan@adm.ua>
2015-12-24 18:34:46 +00:00
Adrian Chadd
f3213f44b2 [rt305x] add PCI bus / resource allocation code for the MT7620.
This is based on the sys/arm/mv/ pci resource/allocation code.

Submitted by:	Stanislav Galabov <galabov@gmail.com>
2015-12-24 18:33:08 +00:00
Adrian Chadd
c40db2e376 [rt305x] add register space definitions for later generation chips.
This adds definitions for the MT5350 and MT7620 SoCs.

Submitted by:	Stanislav Galabov <galabov@gmail.com>
2015-12-24 18:31:55 +00:00
Adrian Chadd
1bbf40fab5 [rt305x] Prepare for the upcoming regime change - add RT305x options.
Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 18:30:04 +00:00
Adrian Chadd
d06ccd84b3 Begin the initial support for the mips1004kc core.
* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.

Tested:

* MT7621A SoC (not yet in-tree)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 15:52:21 +00:00
Adrian Chadd
67f670190f Add missing \n.
Otherwise you end up with:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v80.150
  MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  L2 cache: disabled  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config2=0x80000000
  Config3=0x2420

Tested:

* MT7620 SoC
2015-12-24 04:37:19 +00:00
Adrian Chadd
7b61491a8d [mips] Add TLB pagemask probing code, and print out the allowable page sizes.
This is from Stacey's work on larger kernel stack sizes for MIPS.  Thanks!

Submitted by:	sson
2015-12-22 15:59:41 +00:00
Ian Lepore
9b4d9c162a Add a mips implementation of OF_decode_addr(). 2015-12-21 18:19:14 +00:00
Adrian Chadd
aefdcce869 [mips] print out l2 cache configuration if it exists.
The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board
has an L2 cache:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 8
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: Ingenic Xburst processor v79.2
  MMU: Standard TLB, 32 entries
  L1 i-cache: 8 ways of 128 sets, 32 bytes per line
  L1 d-cache: 8 ways of 128 sets, 32 bytes per line
  L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size
  Config1=0xbe67338b<WatchRegs,EJTAG,FPU>
  Config2=0x80000267
  Config3=0x20
2015-12-21 01:48:16 +00:00
Ian Lepore
f3be407b23 Tidy up mips ofw_machdep.h. Don't include openfirm.h because openfirm.h
is what includes machine/ofw_machdep.h.  Don't declare OF_decode_addr();
it isn't implemented yet on mips and the declaration for it is about to
be commonized into openfirm.h.
2015-12-20 19:09:12 +00:00
Alan Cox
c869e67208 Introduce a new mechanism for relocating virtual pages to a new physical
address and use this mechanism when:

1. kmem_alloc_{attr,contig}() can't find suitable free pages in the physical
   memory allocator's free page lists.  This replaces the long-standing
   approach of scanning the inactive and inactive queues, converting clean
   pages into PG_CACHED pages and laundering dirty pages.  In contrast, the
   new mechanism does not use PG_CACHED pages nor does it trigger a large
   number of I/O operations.

2. on 32-bit MIPS processors, uma_small_alloc() and the pmap can't find
   free pages in the physical memory allocator's free page lists that are
   covered by the direct map.  Tested by: adrian

3. ttm_bo_global_init() and ttm_vm_page_alloc_dma32() can't find suitable
   free pages in the physical memory allocator's free page lists.

In the coming months, I expect that this new mechanism will be applied in
other places.  For example, balloon drivers should use relocation to
minimize fragmentation of the guest physical address space.

Make vm_phys_alloc_contig() a little smarter (and more efficient in some
cases).  Specifically, use vm_phys_segs[] earlier to avoid scanning free
page lists that can't possibly contain suitable pages.

Reviewed by:	kib, markj
Glanced at:	jhb
Discussed with:	jeff
Sponsored by:	EMC / Isilon Storage Division
Differential Revision:	https://reviews.freebsd.org/D4444
2015-12-19 18:42:50 +00:00
Adrian Chadd
191f543e29 [qca953x] remove unneeded initialisation.
This was copied from another chip file and it's not required on Honeybee.

Tested:

* AP143, QCA9531 SoC.

Obtained from: OpenWRT
2015-12-15 04:45:00 +00:00
Adrian Chadd
2365b69ef7 [ar71xx] always count interrupts, spurious or otherwise.
This aids in debugging.
2015-12-15 04:44:06 +00:00
Adrian Chadd
ae3f04a5df [arge] add a comment about needing mdio busses in order to use the interface.
This is a holdover from how reset is handled in the ARGE_MDIO world.
You need to define the mdio bus device if you want to use the ethernet
device or the arge setup path doesn't bring the MAC out of reset.
2015-12-15 04:43:28 +00:00
Warner Losh
14f4e15704 Correct the CONFIG0_VI value. According to
http://www.t-es-t.hu/download/mips/md00090c.pdf this is bit 3 of the
config0 word, not bit 2.  This should fix virtually indexed caches
(relatively new in the MIPS world, so no current platforms used this
and current code just uses it as an optimization). It was causing
false positives on newer platforms that default to large values for
the kseg0 cache coherency attribute.

Submitted by: Stanislav Galabov
PR:	205249
2015-12-11 16:51:04 +00:00
Mark Johnston
711fbd17ec Add helper functions proc_readmem() and proc_writemem().
These helper functions can be used to read in or write a buffer from or to
an arbitrary process' address space. Without them, this can only be done
using proc_rwmem(), which requires the caller to fill out a uio. This is
onerous and results in code duplication; the new functions provide a simpler
interface which is sufficient for most existing callers of proc_rwmem().

This change also adds a manual page for proc_rwmem() and the new functions.

Reviewed by:	jhb, kib
Differential Revision:	https://reviews.freebsd.org/D4245
2015-12-07 21:33:15 +00:00
Adrian Chadd
cd15736797 Add support for the integrated wifi for the QCA953x base config and
AP143.

Tested:

* AP143 reference design board
2015-11-29 05:49:49 +00:00
Konstantin Belousov
724f4b62b0 Remove sv_prepsyscall, sv_sigsize and sv_sigtbl members of the struct
sysent.

sv_prepsyscall is unused.

sv_sigsize and sv_sigtbl translate signal number from the FreeBSD
namespace into the ABI domain.  It is only utilized on i386 for iBCS2
binaries.  The issue with this approach is that signals for iBCS2 were
delivered with the FreeBSD signal frame layout, which does not follow
iBCS2.  The same note is true for any other potential user if
sv_sigtbl.  In other words, if ABI needs signal number translation, it
really needs custom sv_sendsig method instead.

Sponsored by:	The FreeBSD Foundation
2015-11-28 08:49:07 +00:00
Svatopluk Kraus
eae22c4430 Revert r291142.
The not quite consistent logic for bounce pages allocation is utilizited
by re(4) interface which can hang now.

Approved by:	kib (mentor)
2015-11-23 11:19:00 +00:00