Commit Graph

166 Commits

Author SHA1 Message Date
adrian
02336162cd Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-04-20 22:44:00 +00:00
adrian
6152dc39f2 Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.

* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
  code does.

I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."

TODO:

* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
  Linux OpenWRT.  The current WAR has only been tested on the AR7240
  and I'm not sure the way the BAR register is treated is "right".
  The "fixup" method here is right when setting the BAR for local access -
  ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
  but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
  initial "fixup" BAR.  It then restores the original BAR.
  I'll have to read the ar724x PCI bus glue to see what other special cases
  await.
2012-04-20 08:26:05 +00:00
adrian
0e5c802c61 Style(9) and white space fixes. 2012-04-17 01:34:49 +00:00
adrian
23c6d6eeb0 Protect the PCI space registers behind a mutex.
Obtained from:	Linux/OpenWRT, Atheros
2012-04-17 01:22:59 +00:00
adrian
66d589b127 The AR913x MII speed configuration matches the AR71xx MII configuration.
So share the code.

Don't do it for the AR724x - that has a completely different set of PLL
and MII configuration parameters.
2012-04-15 22:34:22 +00:00
adrian
179e79fd20 Fix the mask logic when reading PCI configuration space registers. 2012-04-15 02:38:01 +00:00
adrian
6b1a85efd5 (ab)Use the firmware API to store away EEPROM calibration data for
future use by the ath(4) driver.

These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.

The particulars:

* Introduce ath_fixup_size, which is the size of the EEPROM area in
  bytes.
* Create a firmware image with a name based on the PCI device identifier
  (bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.

ath(4) can then use this to load in the EEPROM data.

This requires AR71XX_ATH_EEPROM to be defined.
2012-04-13 08:45:50 +00:00
adrian
ef9e8f2fea Remove an unused variable. Grr. 2012-04-13 06:13:37 +00:00
adrian
10450b4fc3 Sync this code against what's in OpenWRT trunk.
* the openwrt code doesn't treat 0/0/0 any differently
  from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
  so I've added it.
* The PCI workaround at attach time uses this LCONF code,
  which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
  Even though it's PCIR_COMMAND which is a two byte PCI register.

Tested on:	AR7161
TODO:		The other two AR71xx derivatives
TODO:		More thoroughly stare at the datasheets I do have
		and if it indeed is incorrect, push fixes to both
		FreeBSD and Linux/OpenWRT.

Obtained from:	Linux OpenWRT
2012-04-13 06:11:24 +00:00
jmallett
4544b2987d Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software.  MIPS builds which are little-endian
should require and exhibit no changes.  Big-endian TARGET_ARCHes must be
changed:
	From:		To:
	mipseb		mips
	mipsn32eb	mipsn32
	mips64eb	mips64

An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
2012-03-29 02:54:35 +00:00
gonzo
44ac3b71b6 Rework MIPS PMC code:
- Replace MIPS24K-specific code with more generic framework that will
    make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
    HWPMC_MIPS_BACKTRACE to override this limitation
2012-03-22 18:01:23 +00:00
gonzo
5098cfd078 Move PMC hook invocation to cpu_intr. The idea is the same as with ast()
call but there is no reason to implement it in assembler.
2012-03-22 17:47:52 +00:00
gonzo
fd6921cafa - Fix logic for detection if further processing of PMC should be performed.
pmc_intr returns one if one of the counters actually triggered the IRQ
- style(9) fixed
2012-03-18 01:43:41 +00:00
adrian
9608a1f31c style(9) changes. 2012-03-17 07:29:11 +00:00
adrian
7910492ee4 Begin fleshing out MII clock rate configuration changes.
These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
  been determined.
2012-03-17 07:25:23 +00:00
adrian
96d217f5d8 Remove a now unneeded ARGE_UNLOCK().
Whilst I'm here, remove a couple blank lines.
2012-03-13 06:50:56 +00:00
adrian
a7180c207d Fix link status handling on if_arge upon system boot to allow bootp/NFS to
function.

From the submitter:

This patch fixes an issue I encountered using an NFS root with an
ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails
to contact a DHCP/BOOTP server via if_arge when it otherwise should be able
to.  This may be the same issue that Monthadar Al Jaberi reported against
an RSPRO on 6 March, as the signature is the same:

%%%

DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
.
.
.
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers

%%%

The primary issue that I found is that the DHCP/BOOTP message that
bootpc_call() is sending never makes it onto the wire, which I believe is
due to the following:

- Last December, a change was made to the ifioctl that bootpc_call() uses
to adjust the netmask around the sosend().

- The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the
old one (SIOCSIFNETMASK) did not.

- if_arge maintains its own sense of link state in sc->arge_link_status.

- On a single-phy interface, sc->arge_link_status is initialized to 0 in
arge_init_locked().

- sc->arge_link_status remains 0 until a phy state change notification
causes arge_link_task to run, notice the link is up, and set it to 1.

- The inits caused by the ifioctls in bootpc_call are reinitializing the
interface, but not the phy, so sc->arge_link_status goes to 0 and remains
there.

- arge_start_locked() always sees sc->arge_link_status == 0 and returns
without queuing anything.

The attached patch changes arge_init_locked() such that in the single-phy
case, instead of initializing sc->arge_link_status to 0, it runs
arge_link_task() to set it according to the current phy state.  This change
has allowed my setup to mount an NFS root successfully.

Submitted by:	Patrick Kelsey <kelsey@ieee.org>
Reviewed by:	juli
2012-03-13 06:28:52 +00:00
adrian
d44d6b85dc Correctly (I hope) deallocate the if_arge RX buffer ring on arge_stop().
I had some interesting hangs until I realised I should try flushing the
DDR FIFO register and lo and behold, hangs stopped occuring.

I've put in a few DDR flushes here and there in case people decide to
reuse some of these functions.  It's very very likely they're almost
all superflous.

To test:

* Connect to a network with a _lot_ of broadcast traffic
* Do this:
  # while true; do ifconfig arge0 down; ifconfig arge0 up; done

This fixes the mbuf exhaustion that has been reported when the interface
state flaps up/down.
2012-03-13 06:15:20 +00:00
jmallett
195d122172 o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
   XXX This is implemented in a kind-of nasty way that involves including source
       files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
2012-03-12 21:25:32 +00:00
jmallett
ac2071063e Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.

Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
2012-03-12 07:34:15 +00:00
gonzo
2bb441e96e - Rename apb_intr to apb_filter since it's a filter handler
- Pass interrupt trapframe for handlers dow the chain
- Add PMC interrupt handler
    PMC interrupt is a special case, so we want handle it as soon as possible
    with minimum overhead. So we handle it apb filter routine.
2012-03-12 01:23:09 +00:00
ray
10e68a3224 Break long lines.
Approved by:	adri (mentor)
2012-03-06 22:45:54 +00:00
ray
9d353b86a5 Remove EoL whitespaces.
Approved by:	adri (mentor)
2012-03-06 22:16:10 +00:00
adrian
5e86568189 Stop overloading opt_global.h. 2012-01-16 05:07:32 +00:00
adrian
06e4ca1835 Some of the atheros based embedded devices use one or more PCI NICs
on-board, glued to the AR71xx CPU.  These may forgo separate WMAC EEPROMs
(which store configuration and calibration data) and instead store
it in the main board SPI flash.

Normally the NIC reads the EEPROM attached to it to setup various PCI
configuration registers.  If this isn't done, the device will probe as
something different (eg 0x168c:abcd, or 0x168c:ff??.)  Other setup registers
are also written to which may control important functions.

This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the
use of this particular code.  The ART offset in the SPI flash can be
specified as a hint against the relevant slot/device number, for example:

hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000

TODO:

* Think of a better name;
* Make the PCIe version of this fixup code also use this option;
* Maybe also check slot 19;
* This has to happen _before_ the SPI flash is set from memory-mapped
  to SPI-IO - so document that somewhere.
2012-01-15 19:29:33 +00:00
adrian
6707636c2f Fix the ar724x shift calculation when writing to the PCI config space.
This was preventing the ath driver from being loaded at runtime.
It worked fine when compiled statically into the kernel but not when
kldload'ed after the system booted.

The root cause was that PCIR_INTLINE (register 60) was being
overwritten by zeros when register 62 was being written to.
A subsequent read of this register would return 0, and thus
the rest of the PCI glue assumed an IRQ resource had already
been allocated.  This caused the device to fail to attach at
runtime as the device itself didn't contain any IRQ resources.

TODO: go back over the ar71xx and ar724x PCI config read/write
code and ensure it's correct.
2012-01-07 04:13:25 +00:00
adrian
d143e961c0 Remove these locks - they aren't strictly needed and cause measurable
performance issues.

* Access to the GPIO bus is already locked by requesting
  and releasing the bus - thus the lock isn't really needed
  for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
  the i2c bus code is already doing this by calling the upper
  layer callback to request/release the bus. This thus locks
  the bus for the entirety of the transaction.

TODO:

* Further verify that everything is correctly requesting/
  releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
  potentially by locking/unlocking the bus at the gpiobus
  layer.
2011-12-20 00:33:56 +00:00
adrian
1af383c5f6 Re-jiggle the GPIO code a little to remove the hard-coded AR71xx GPIO
config and function mask setup.

* "gpiomask" now specifies which GPIO pins to enable, for devices to bind to.
* "function_set" allows bits in the function register to be set at GPIO setup.
* "function_clear" allows bits in the function register to be cleared at
  GPIO setup.

The function_set/function_clear bits allow for individual GPIO pins to either
drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows
for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected,
or disabling JTAG for the AR7240 (which is apparently needed ..)

I've verified this on the AR71xx.
2011-12-15 01:03:49 +00:00
hselasky
7076389cec Implement better support for USB controller suspend and resume.
This patch should remove the need for kldunload of USB
controller drivers at suspend and kldload of USB controller
drivers at resume.

This patch also fixes some build issues in avr32dci.c

MFC after:	2 weeks
2011-12-14 00:28:54 +00:00
adrian
4cfa71433d Style(9) changes. 2011-12-13 05:13:51 +00:00
ray
d3734c7047 Simplify arge_flush_ddr to use updated ar71xx_device_flush_ddr_ge(unit).
Approved by: adrian (mentor)
2011-11-28 13:42:59 +00:00
glebius
953eb41fbd Fix build, fininshing r228018. 2011-11-28 08:10:12 +00:00
ray
39c8d59a00 Join chip depended methods for arge0 and arge1 into single call with unit.
Approved by: adrian (mentor)
2011-11-27 11:15:59 +00:00
adrian
8d1324f467 Introduce a new (global, sorry!) option which controls whether
the ar71xx platform code should assume a uboot or redboot environment.

The current code gets very confused (and just crashes) on a uboot
environment, where each attribute=value pair is in a single entry.
Redboot on the other hand stores it as "attribute", "value", "attribute",
"value", ...

This allows the kernel to boot on a TP-LINK TL-WR1043ND from flash,
where the uboot environment gets setup. This didn't show up during a netboot
as "tftpboot" and "go" don't setup the uboot environment variables.
2011-11-24 07:32:52 +00:00
hselasky
53a216b722 Rename device_delete_all_children() into device_delete_children().
Suggested by:	jhb @ and marius @
MFC after:	1 week
2011-11-22 21:56:55 +00:00
marius
17e14c6132 - There's no need to overwrite the default device method with the default
one. Interestingly, these are actually the default for quite some time
  (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9)
  since r52045) but even recently added device drivers do this unnecessarily.
  Discussed with: jhb, marcel
- While at it, use DEVMETHOD_END.
  Discussed with: jhb
- Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
yongari
4c371e596b Close a race where SIOCGIFMEDIA ioctl get inconsistent link status.
Because driver is accessing a common MII structure in
mii_pollstat(), updating user supplied structure should be done
before dropping a driver lock.

Reported by:	Karim (fodillemlinkarimi <> gmail dot com)
2011-10-17 19:49:00 +00:00
kevlo
827f99272d Remove duplicate header includes 2011-06-26 10:07:48 +00:00
adrian
94eb8448ed Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC.
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
2011-05-06 02:45:02 +00:00
marius
d0f32374e6 - Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP
(reporting IFM_LOOP based on BMCR_LOOP is left in place though as
  it might provide useful for debugging). For most mii(4) drivers it
  was unclear whether the PHYs driven by them actually support
  loopback or not. Moreover, typically loopback mode also needs to
  be activated on the MAC, which none of the Ethernet drivers using
  mii(4) implements. Given that loopback media has no real use (and
  obviously hardly had a chance to actually work) besides for driver
  development (which just loopback mode should be sufficient for
  though, i.e one doesn't necessary need support for loopback media)
  support for it is just dropped as both NetBSD and OpenBSD already
  did quite some time ago.
- Let mii_phy_add_media() also announce the support of IFM_NONE.
- Restructure the PHY entry points to use a structure of entry points
  instead of discrete function pointers, and extend this to include
  a "reset" entry point. Make sure any PHY-specific reset routine is
  always used, and provide one for lxtphy(4) which disables MII
  interrupts (as is done for a few other PHYs we have drivers for).
  This includes changing NIC drivers which previously just called the
  generic mii_phy_reset() to now actually call the PHY-specific reset
  routine, which might be crucial in some cases. While at it, the
  redundant checks in these NIC drivers for mii->mii_instance not being
  zero before calling the reset routines were removed because as soon
  as one PHY driver attaches mii->mii_instance is incremented and we
  hardly can end up in their media change callbacks etc if no PHY driver
  has attached as mii_attach() would have failed in that case and not
  attach a miibus(4) instance.
  Consequently, NIC drivers now no longer should call mii_phy_reset()
  directly, so it was removed from EXPORT_SYMS.
- Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe().
  The purpose of that function is to perform the common steps to attach
  a PHY driver instance and to hook it up to the miibus(4) instance and to
  optionally also handle the probing, addition and initialization of the
  supported media. So all a PHY driver without any special requirements
  has to do in its bus attach method is to call mii_phy_dev_attach()
  along with PHY-specific MIIF_* flags, a pointer to its PHY functions
  and the add_media set to one. All PHY drivers were updated to take
  advantage of mii_phy_dev_attach() as appropriate. Along with these
  changes the capability mask was added to the mii_softc structure so
  PHY drivers taking advantage of mii_phy_dev_attach() but still
  handling media on their own do not need to fiddle with the MII attach
  arguments anyway.
- Keep track of the PHY offset in the mii_softc structure. This is done
  for compatibility with NetBSD/OpenBSD.
- Keep track of the PHY's OUI, model and revision in the mii_softc
  structure. Several PHY drivers require this information also after
  attaching and previously had to wrap their own softc around mii_softc.
  NetBSD/OpenBSD also keep track of the model and revision on their
  mii_softc structure. All PHY drivers were updated to take advantage
  as appropriate.
- Convert the mebers of the MII data structure to unsigned where
  appropriate. This is partly inspired by NetBSD/OpenBSD.
- According to IEEE 802.3-2002 the bits actually have to be reversed
  when mapping an OUI to the MII ID registers. All PHY drivers and
  miidevs where changed as necessary. Actually this now again allows to
  largely share miidevs with NetBSD, which fixed this problem already
  9 years ago. Consequently miidevs was synced as far as possible.
- Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that
  weren't explicitly converted to support flow control before. It's
  unclear whether flow control actually works with these but typically
  it should and their net behavior should be more correct with these
  changes in place than without if the MAC driver sets MIIF_DOPAUSE.

Obtained from:	NetBSD (partially)
Reviewed by:	yongari (earlier version), silence on arch@ and net@
2011-05-03 19:51:29 +00:00
adrian
a10a894ed3 Some AR724x PCIe fixes, which should wrap up the first round
of endian-ness issues with the AR724x.

From Luiz:

* Fix the bus space tag used so endian-ness is correctly handled;
* Only do the workaround for the AR7240; AR7241/AR7242 (PB92)
  don't require this

From me:

* Add a read flush from openwrt

Submitted by:	Luiz Otavio O Souza
2011-05-01 23:32:37 +00:00
adrian
6ab4da9340 The AR724x SoC's require the irq status line to be acked/cleared.
This allows console IO to occur correctly once the kernel is in multi-user
mode.

Submitted by:	Luiz Otavio O Souza
2011-04-30 12:07:15 +00:00
adrian
d8b9be857c Call the DDR FIFO flush method when IP2 interrupts occur. 2011-04-30 11:56:04 +00:00
adrian
e032e84ff6 Flip off debugging for now. 2011-04-30 11:40:31 +00:00
adrian
ac09e9d74c Add some initial PCIe bridge support for the AR724x chipsets.
This is reported to work on the AR7240 based Ubiquiti Rocket M5
but I haven't tested it on that hardware. I also don't yet have
it fully working on the AR7242 based development board here;
probe/attach functions but the register space resource looks like
the endian-ness is wrong (0x10000000 instead of 0x00001000).o

Further digging will be required.

Submitted by:	Luiz Otavio O Souza
2011-04-30 11:36:16 +00:00
adrian
93ca97e7e5 In preparation for the AR724x PCIe bus code, make the AR71xx PCI bus
glue require 'device ar71xx_pci' .

Users of the AR71xx board configs will now require this for functioning
PCI:

device pci
device ar71xx_pci
2011-04-30 11:28:21 +00:00
adrian
b6b6fb669f Add a missing DDR FIFO method for the ar71xx. 2011-04-30 02:31:56 +00:00
adrian
1a0ab8d902 Tidy up the naming of the ip2 DDR flush routine, and add an inline
accessor method (which is currently unused) in there.
2011-04-29 06:25:11 +00:00
adrian
abc1b86fe6 Add the IP2 DDR flush handlers.
These aren't yet used in the interrupt handler path but should be.
2011-04-28 11:13:26 +00:00
hselasky
69b34d187e We don't need to call EOWRITE4(sc, EHCI_USBINTR, 0) directly from each EHCI
bus driver at detach, hence ehci_detach() does exactly this since r199718.

Submitted by:	Luiz Otavio O Souza
MFC after:	7 days
Approved by:	thompsa (mentor)
2011-04-12 07:49:11 +00:00