number in the irq register. While there are other issues with these
variants, avoiding writing to it helps interrupt generation on at
least one card, and doesn't hurt on the others. Flag ISA attachment
as needing INT_NO_REG written, and don't update the PC Card attachment
(which will have the effect of not touching it for PC Cards).
Document this in a comment, and tweak one or two formatting nits while
I'm here.
This is a sync to mesa/drm pre-gem, with a few fixes on top of that.
It also contains one local patch supplied by kib@ that I can't apply to
git.master shared code.
Approved by: flz
Obtained from: mesa/drm git.master
MFC after: 2 weeks
in a noticeable reduction in system time spent.
- If bus_dmamap_load_mbuf_sg(9) fails with EFBIG and we already have
defragmented the mbuf chain, don't bother to defragment and load it
a second time just yet as it's likely to fail again anyway.
MFC after: 3 days
night.
Free the children after each pci bus that is searched. Otherwise we
leak them. With free in the new place, we also have to free children
before going to done when we find the device we're looking for.
Also, if we can't get the children of a device, just ignore that bus.
When there's an error, we don't want to free the children, since it
will be stack garbage. While we did fail to dereference it by setting
devs to 0, we didn't fail to call free. We never failed to fail, it
was the easiest thing to do.
PHY only and not also in the case of an external PHY currently
doing full duplex, which accidentally got broken in r172334.
It's still not clear to me why we need to enable the buffer for
an internal PHY though.
- Count excess and late collisions as output errors. [1]
- Count receive errors as input errors. [1]
Obtained from: NetBSD [1]
MFC after: 3 days
only in low memory situations, so the error fork of these fixes is
lightly tested, but they should do the least-wrong thing...
Submitted by: Hans Petter Selasky
counters for Rx/Tx statistics. Various counters in ifnet is also
updated with these hardware counters.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
interrupt mask register again. This saves one register access per
each interrupt.
Also don't try to process frames when driver is not running.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the
rest of the kernel. It now also accepts parameters via function
arguments rather than global variables.
- Add a notion of minimum and maximum bus numbers and reject requests for
an out of range bus.
- Add more range checks on slot/func/reg/bytes parameters to the cfg reg
read/write routines. Don't panic on any invalid parameters, just fail
the request (writes do nothing, reads return -1). This matches the
behavior of the other cfg mechanisms.
- Port the memory mapped configuration space access to amd64. On amd64
we simply use the direct map (via pmap_mapdev()) for the memory mapped
window.
- During acpi_attach() just after loading the ACPI tables, check for a
MCFG table. If it exists, call pciereg_cfgopen() on each subtable
(memory mapped window). For now we only support windows for domain 0
that start with bus 0. This removes the need for more chipset-specific
quirks in the MD code.
- Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets
since these machines should all have MCFG tables via ACPI.
- Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen()
earlier.
MFC after: 2 weeks
link state and detach request.
While I'm here make sure established link is IFM_10_T or
IFM_100_TX as bfe(4) just supports 10/100Mbps media.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
o Removed unneeded header files.
o bus_dma(9) fix:
- created parent tag with 1GB dma address limit with no
alignment restrictions.
- set 4096 alignment limit for Tx/Rx descriptor rings.
- separate Rx buffer tag from Tx buffer tag such that Tx tag
allows up-to 16 segments while Rx buffer tag only allows
single segment.
- it seems the controller has no alignment restrictions on Tx/Rx
buffers. Remove ETHER_ALIGN alignment restriction in Tx/Rx
buffers.
- created a spare Rx dma map which would be used to cope with
failure of loading a dma map.
- make sure to load full Tx/Rx descriptor size for Tx/Rx
descriptor dma maps, previously bfe(4) used to load single
descriptor size for each descriptor rings. I have no idea how
it could be run without problems.
- don't blindly cast bus_addr_t type to 32bits in bfe_dma_map().
- created bfe_dma_free() to free allocated dma memory/tags.
- make sure to invoke bus_dmamap_sync(9) before/after processing
descriptor rings/buffers. Because the hardware has severe dma
address space limitation, bounce-buffers would be always used
on systems with more than 1GB memory during
descriptors/buffers access.
- added Tx descriptor ring initialization function,
bfe_list_tx_init().
- moved producer/consumer index initialization to
bfe_list_tx_init() and bfe_list_rx_init() from
bfe_chip_reset().
- added bfe_discard_buf() which will update loaded descriptors
without unloading/reloading the dma map to speed up error
recovery.
- implemented Tx side bus_dmamap_load_mbuf_sg(9). The number of
segments allowed was chosen to be 16 which should be enough for
non-TSO capable hardwares. Setting SOF bit of Tx descriptor is
done in the last to avoid potential race.
- don't give up sending frames in bfe_start() until the hardware
lacks free descriptors.
- added XXX comment to second kick command and possible workaround.
- implemented Rx side bus_dmamap_load_mbuf_sg(9).
- removed bfe_dma_map_desc() as it's not needed anymore after
the conversion to bus_dmamap_load_mbuf_sg(9).
- added endianness support. With this change bfe(4) should work
on any architectures that can create bounce buffers within 1GB
address range.
- add missing bus_dmamap_sync() in bfe_tx_eof()/bfe_rx_eof().
o Use PCI_BAR instead of hardcoded value to set BARs.
Simplified register access with bus_write_4(9)/bus_read_4(9) and
removed bfe_btag, bfe_bhandle, bfe_vhandle in softc as it's not
used anymore.
o Reorder device detach logic such that bfe_detach() is also used
for handling driver attach failure case.
o Remove unnecessary KASSERT in bfe_detach().
o Remove bfe_rx_cnt, bfe_up, bfe_vpd_prodname, bfe_vpd_readonly in
softc. It's not used at all.
o Remove BFE_RX_RING_SIZE/BFE_RX_RING_SIZE/BFE_LINK_DOWN.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
memory area's base and limit are optional. The low 4-bits of the "low"
prefetchable registers indicates whether or not a 32-bit or 64-bit
region is supported. The PCI-PCI driver had been assuming that all bridges
supported a 64-bit region (and thus the two upper 32-bit registers). Fix
the driver to only use those registers if the low 4-bits of the "low"
registers indicate that a 64-bit region is supported. The PCI-PCI bridge
in the XBox happens to be a bridge that only supports a 32-bit region.
Reported by: rink
MFC after: 1 week
I initially didn't want to integrate the Xen console driver, because it
did not receive any testing. Kip Macy suggested that I'd better check it
in right now, because this is the easiest way for him to test it while
he is working on the Xen import.
Requested by: kmacy
The last half year I've been working on a replacement TTY layer for the
FreeBSD kernel. The new TTY layer was designed to improve the following:
- Improved driver model:
The old TTY layer has a driver model that is not abstract enough to
make it friendly to use. A good example is the output path, where the
device drivers directly access the output buffers. This means that an
in-kernel PPP implementation must always convert network buffers into
TTY buffers.
If a PPP implementation would be built on top of the new TTY layer
(still needs a hooks layer, though), it would allow the PPP
implementation to directly hand the data to the TTY driver.
- Improved hotplugging:
With the old TTY layer, it isn't entirely safe to destroy TTY's from
the system. This implementation has a two-step destructing design,
where the driver first abandons the TTY. After all threads have left
the TTY, the TTY layer calls a routine in the driver, which can be
used to free resources (unit numbers, etc).
The pts(4) driver also implements this feature, which means
posix_openpt() will now return PTY's that are created on the fly.
- Improved performance:
One of the major improvements is the per-TTY mutex, which is expected
to improve scalability when compared to the old Giant locking.
Another change is the unbuffered copying to userspace, which is both
used on TTY device nodes and PTY masters.
Upgrading should be quite straightforward. Unlike previous versions,
existing kernel configuration files do not need to be changed, except
when they reference device drivers that are listed in UPDATING.
Obtained from: //depot/projects/mpsafetty/...
Approved by: philip (ex-mentor)
Discussed: on the lists, at BSDCan, at the DevSummit
Sponsored by: Snow B.V., the Netherlands
dcons(4) fixed by: kan
The PCM's sound.h file only seems to include <sys/tty.h>, because
channel_if seems to require selinfo. Just replace it with
<sys/selinfo.h>.
There's no real problem with including <sys/tty.h> here, even with
MPSAFE TTY, but <sys/tty.h> is something that should be used by the TTY
layer, its driver and code that integrated it with the process tree.
