Commit Graph

817 Commits

Author SHA1 Message Date
alc
6a3535c3fa Relax one of the new assertions in pmap_enter() a little. Specifically,
allow pmap_enter() to be performed on an unmanaged page that doesn't have
VPO_BUSY set.  Having VPO_BUSY set really only matters for managed pages.
(See, for example, pmap_remove_write().)
2010-06-11 15:49:39 +00:00
alc
7c212e010d Reduce the scope of the page queues lock and the number of
PG_REFERENCED changes in vm_pageout_object_deactivate_pages().
Simplify this function's inner loop using TAILQ_FOREACH(), and shorten
some of its overly long lines.  Update a stale comment.

Assert that PG_REFERENCED may be cleared only if the object containing
the page is locked.  Add a comment documenting this.

Assert that a caller to vm_page_requeue() holds the page queues lock,
and assert that the page is on a page queue.

Push down the page queues lock into pmap_ts_referenced() and
pmap_page_exists_quick().  (As of now, there are no longer any pmap
functions that expect to be called with the page queues lock held.)

Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever
be passed an unmanaged page.  Assert this rather than returning "0"
and "FALSE" respectively.

ARM:

Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH().

Push down the page queues lock inside of pmap_clearbit(), simplifying
pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write().
Additionally, this allows for avoiding the acquisition of the page
queues lock in some cases.

PowerPC/AIM:

moea*_page_exits_quick() and moea*_page_wired_mappings() will never be
called before pmap initialization is complete.  Therefore, the check
for moea_initialized can be eliminated.

Push down the page queues lock inside of moea*_clear_bit(),
simplifying moea*_clear_modify() and moea*_clear_reference().

The last parameter to moea*_clear_bit() is never used.  Eliminate it.

PowerPC/BookE:

Simplify mmu_booke_page_exists_quick()'s control flow.

Reviewed by:	kib@
2010-06-10 16:56:35 +00:00
alc
44bdecdec3 Don't set PG_WRITEABLE in init_pte_prot() (and thus pmap_enter()) unless
the page is managed.

Don't set the machine-independent layer's dirty field for the page being
mapped in init_pte_prot().  (The dirty field is only supposed to set when
a mapping is removed or write-protected and the page was managed and
modified.)

Determine whether or not to perform dirty bit emulation based on whether
or not the page is managed, i.e., pageable, not based on whether the page
is being mapped into the kernel address space.  Nearly all of the kernel
address space consists of unmanaged pages, so this has neglible impact on
the overhead of dirty bit emulation for the kernel address space.  However,
there can also exist unmanaged pages in the user address space.  Previously,
dirty bit emulation was unnecessarily performed on these pages.

Tested by:	jchandra@
2010-06-06 06:07:44 +00:00
jchandra
e9a1a12ab4 Make vm_contig_grow_cache() extern, and use it when vm_phys_alloc_contig()
fails to allocate MIPS page table pages.  The current usage of VM_WAIT in
case of vm_phys_alloc_contig() failure is not correct, because:

"There is no guarantee that any of the available free (or cached) pages
after the VM_WAIT will fall within the range of suitable physical
addresses.  Every time this function sleeps and a single page is freed
(or cached) by someone else, this function will be reawakened.  With
a little bad luck, you could spin indefinitely."

We also add low and high parameters to vm_contig_grow_cache() and
vm_contig_launder() so that we restrict vm_contig_launder() to the range
of pages we are interested in.

Reported by: alc

Reviewed by:	alc
Approved by:	rrs (mentor)
2010-06-04 06:35:36 +00:00
alc
2455e5f922 Fix a KASSERT() that was broken in r208665.
Reported by:	jmallett
2010-06-01 04:38:05 +00:00
alc
b5170d1a7e Eliminate a stale comment. 2010-05-31 06:06:10 +00:00
alc
607fc8f5ea Merge portions of r208645 and supporting code from the i386 pmap:
When I pushed down the page queues lock into pmap_is_modified(), I created
  an ordering dependence: A pmap operation that clears PG_WRITEABLE and calls
  vm_page_dirty() must perform the call first.  Otherwise, pmap_is_modified()
  could return FALSE without acquiring the page queues lock because the page
  is not (currently) writeable, and the caller to pmap_is_modified() might
  believe that the page's dirty field is clear because it has not seen the
  effect of the vm_page_dirty() call.

  When I pushed down the page queues lock into pmap_is_modified(), I
  overlooked one place where this ordering dependence is violated:
  pmap_enter().  In a rare situation pmap_enter() can be called to replace a
  dirty mapping to one page with a mapping to another page.  (I say rare
  because replacements generally occur as a result of a copy-on-write fault,
  and so the old page is not dirty.)  This change delays clearing PG_WRITEABLE
  until after vm_page_dirty() has been called.

  Fixing the ordering dependency also makes it easy to introduce a small
  optimization: When pmap_enter() used to replace a mapping to one page with a
  mapping to another page, it freed the pv entry for the first mapping and
  later called the pv entry allocator for the new mapping.  Now, pmap_enter()
  attempts to recycle the old pv entry, saving two calls to the pv entry
  allocator.
2010-05-31 01:43:02 +00:00
alc
5c8460ba2e Simplify the inner loop of get_pv_entry(): While iterating over the page's
pv list, there is no point in checking whether or not the pv list is empty,
wait instead until the loop completes.
2010-05-30 20:31:12 +00:00
jchandra
e2c40a3a8f Fix lock order reversal, unlock page queue and pmap locks before
calling uma_zfree().
Also if needed, acquire page queue lock before modifying pte page
attributes.

Approved by:	rrs (mentor)
2010-05-28 12:05:56 +00:00
neel
5260c24925 Get rid of unused variable 'virtual_sys_start'. 2010-05-28 05:34:43 +00:00
neel
bc054a3a48 If 'timer2hz' is zero then we don't need to call 'timer2clock()' directly. It
will be called automatically by 'timer1clock()'.

Do profiling as often as possible by running it as the same frequency as
'timer1hz'. The statistics clock is run as close to 128Hz as possible.

Pointed out by: mav@
2010-05-28 02:00:15 +00:00
jchandra
a2f7432987 Call VM_WAIT in pmap_ptpgzone_allocf() if M_WAITOK is set.
Removed unused variable.

Approved by:	rrs (mentor)
2010-05-27 10:05:40 +00:00
neel
24a8b9692f Simplify clock interrupt handling on mips by using the new KPI - timer1clock()
and timer2clock().

Dynamically adjust the tick frequency depending on the value of 'hz'. Tested
with hz values of 100, 1000 and 2000.
2010-05-27 01:27:25 +00:00
gonzo
7201725878 - Fix kseg0 address calculation - it doesn't always start at
page boundary
- Add cache ops to ensure memory validity before/after
    copy operation
2010-05-26 22:38:45 +00:00
alc
3f1d4b057c Push down page queues lock acquisition in pmap_enter_object() and
pmap_is_referenced().  Eliminate the corresponding page queues lock
acquisitions from vm_map_pmap_enter() and mincore(), respectively.  In
mincore(), this allows some additional cases to complete without ever
acquiring the page queues lock.

Assert that the page is managed in pmap_is_referenced().

On powerpc/aim, push down the page queues lock acquisition from
moea*_is_modified() and moea*_is_referenced() into moea*_query_bit().
Again, this will allow some additional cases to complete without ever
acquiring the page queues lock.

Reorder a few statements in vm_page_dontneed() so that a race can't lead
to an old reference persisting.  This scenario is described in detail by a
comment.

Correct a spelling error in vm_page_dontneed().

Assert that the object is locked in vm_page_clear_dirty(), and restrict the
page queues lock assertion to just those cases in which the page is
currently writeable.

Add object locking to vnode_pager_generic_putpages().  This was the one
and only place where vm_page_clear_dirty() was being called without the
object being locked.

Eliminate an unnecessary vm_page_lock() around vnode_pager_setsize()'s call
to vm_page_clear_dirty().

Change vnode_pager_generic_putpages() to the modern-style of function
definition.  Also, change the name of one of the parameters to follow
virtual memory system naming conventions.

Reviewed by:	kib
2010-05-26 18:00:44 +00:00
neel
8b66012ecb Get rid of empty and unused KSEG0TEXT macros. 2010-05-25 05:45:16 +00:00
neel
65c373c5d5 Fix mips kernel build breakage caused by revision 208504. 2010-05-25 05:42:12 +00:00
alc
32b13ee957 Roughly half of a typical pmap_mincore() implementation is machine-
independent code.  Move this code into mincore(), and eliminate the
page queues lock from pmap_mincore().

Push down the page queues lock into pmap_clear_modify(),
pmap_clear_reference(), and pmap_is_modified().  Assert that these
functions are never passed an unmanaged page.

Eliminate an inaccurate comment from powerpc/powerpc/mmu_if.m:
Contrary to what the comment says, pmap_mincore() is not simply an
optimization.  Without a complete pmap_mincore() implementation,
mincore() cannot return either MINCORE_MODIFIED or MINCORE_REFERENCED
because only the pmap can provide this information.

Eliminate the page queues lock from vfs_setdirty_locked_object(),
vm_pageout_clean(), vm_object_page_collect_flush(), and
vm_object_page_clean().  Generally speaking, these are all accesses
to the page's dirty field, which are synchronized by the containing
vm object's lock.

Reduce the scope of the page queues lock in vm_object_madvise() and
vm_page_dontneed().

Reviewed by:	kib (an earlier version)
2010-05-24 14:26:57 +00:00
jchandra
357362e713 Remove unused code in sys/mips/rmi :
- ehcireg.h,ehcivar.h : USB related files from old merge
 - pcibus.c : was merged into xlr_pci.c earlier
 - xlr_boot1_console.c : obsolete console code using bootloader hooks
 - sys/mips/rmi/perfmon* : obsolete custom performance monitoring code

Approved by:	rrs (mentor)
2010-05-24 06:01:37 +00:00
kib
4208ccbe79 Reorganize syscall entry and leave handling.
Extend struct sysvec with three new elements:
sv_fetch_syscall_args - the method to fetch syscall arguments from
  usermode into struct syscall_args. The structure is machine-depended
  (this might be reconsidered after all architectures are converted).
sv_set_syscall_retval - the method to set a return value for usermode
  from the syscall. It is a generalization of
  cpu_set_syscall_retval(9) to allow ABIs to override the way to set a
  return value.
sv_syscallnames - the table of syscall names.

Use sv_set_syscall_retval in kern_sigsuspend() instead of hardcoding
the call to cpu_set_syscall_retval().

The new functions syscallenter(9) and syscallret(9) are provided that
use sv_*syscall* pointers and contain the common repeated code from
the syscall() implementations for the architecture-specific syscall
trap handlers.

Syscallenter() fetches arguments, calls syscall implementation from
ABI sysent table, and set up return frame. The end of syscall
bookkeeping is done by syscallret().

Take advantage of single place for MI syscall handling code and
implement ptrace_lwpinfo pl_flags PL_FLAG_SCE, PL_FLAG_SCX and
PL_FLAG_EXEC. The SCE and SCX flags notify the debugger that the
thread is stopped at syscall entry or return point respectively.  The
EXEC flag augments SCX and notifies debugger that the process address
space was changed by one of exec(2)-family syscalls.

The i386, amd64, sparc64, sun4v, powerpc and ia64 syscall()s are
changed to use syscallenter()/syscallret(). MIPS and arm are not
converted and use the mostly unchanged syscall() implementation.

Reviewed by:	jhb, marcel, marius, nwhitehorn, stas
Tested by:	marcel (ia64), marius (sparc64), nwhitehorn (powerpc),
	stas (mips)
MFC after:	1 month
2010-05-23 18:32:02 +00:00
neel
c79ede9f60 - Use ptpgzone zone to allocate page table pages irrespective of the amount of
memory on a platform. Tested on the Sibyte with 256MB and 1GB memory
  configurations.

- Replace vtophys() with MIPS_KSEG0_TO_PHYS() to convert a page table
  page's virtual address to physical. We can safely do this because
  page table pages are allocated out of KSEG0.

- Add an assertion to verify that when a page table page is freed it
  contains all zeroes. We can now use it after allocation without
  zeroing it.
2010-05-22 21:38:57 +00:00
jhb
cf780ce267 - Adjust the whitespace for the lines that output fields in 'show pcpu' in
DDB so that all the fields line up.
- Print out the tid of the per-CPU idlethread instead of the pid since
  the idle process is now shared across all idle threads.

MFC after:	1 month
2010-05-21 17:17:56 +00:00
jchandra
2f9e8c891f Changes to boot on a subset of threads on an XLR/XLS core.
- Adds re-partitioning TLB per core for enabled threads.
- Adds hardware thread id to cpuid mapping
- updates rge driver packet distribution and message ring handling
  threads to be started based on hardware thread id.
- remove unused early debugging code to set control registers.
- coding style fixes

Approved by:	rrs (mentor)
2010-05-21 05:34:19 +00:00
rpaulo
fe046906e6 Add a device description. 2010-05-18 17:01:07 +00:00
neel
3e50c01a7f Fix Sibyte SMP kernel breakage caused by r208249.
We need to include the header file that provides declaration of the
smp_topo_none() function.
2010-05-18 05:12:54 +00:00
rrs
73cd3a45a2 Adds the file I forgot to add... that handles
the mpwait.S for RMI

Approved by:	JC
2010-05-18 04:08:58 +00:00
rrs
18ee1164c8 Adds JC's cleanup patches that fix it so
we call an platform dependant topo function as
well as clean up all the XLR specific ifdefs around
smp platform init.

Obtained from:	JC
2010-05-18 04:02:34 +00:00
alc
f6c07c5b87 On entry to pmap_enter(), assert that the page is busy. While I'm
here, make the style of assertion used by pmap_enter() consistent
across all architectures.

On entry to pmap_remove_write(), assert that the page is neither
unmanaged nor fictitious, since we cannot remove write access to
either kind of page.

With the push down of the page queues lock, pmap_remove_write() cannot
condition its behavior on the state of the PG_WRITEABLE flag if the
page is busy.  Assert that the object containing the page is locked.
This allows us to know that the page will neither become busy nor will
PG_WRITEABLE be set on it while pmap_remove_write() is running.

Correct a long-standing bug in vm_page_cowsetup().  We cannot possibly
do copy-on-write-based zero-copy transmit on unmanaged or fictitious
pages, so don't even try.  Previously, the call to pmap_remove_write()
would have failed silently.
2010-05-16 23:45:10 +00:00
rrs
8ea4ab29a0 This pushes all of JC's patches that I have in place. I
am now able to run 32 cores ok.. but I still will hang
on buildworld with a NFS problem. I suspect I am missing
a patch for the netlogic rge driver.

JC check and see if I am missing anything except your
core-mask changes

Obtained from:	JC
2010-05-16 19:43:48 +00:00
imp
93177a0de2 Remove some stray ';'s
Submitted by:	marc balmer
2010-05-13 01:50:29 +00:00
alc
40b44f9713 Push down the page queues into vm_page_cache(), vm_page_try_to_cache(), and
vm_page_try_to_free().  Consequently, push down the page queues lock into
pmap_enter_quick(), pmap_page_wired_mapped(), pmap_remove_all(), and
pmap_remove_write().

Push down the page queues lock into Xen's pmap_page_is_mapped().  (I
overlooked the Xen pmap in r207702.)

Switch to a per-processor counter for the total number of pages cached.
2010-05-08 20:34:01 +00:00
alc
76fc3e2dd0 Eliminate dead code. 2010-05-06 04:23:52 +00:00
neel
d0c6c09b63 Fix DDB backtrace involving kernel modules.
We can no longer assume that all valid program counter values reside
within the kernel object file.
2010-05-05 04:37:45 +00:00
sobomax
213eac1f2c Add new tunable 'net.link.ifqmaxlen' to set default send interface
queue length. The default value for this parameter is 50, which is
quite low for many of today's uses and the only way to modify this
parameter right now is to edit if_var.h file. Also add read-only
sysctl with the same name, so that it's possible to retrieve the
current value.

MFC after:	1 month
2010-05-03 07:32:50 +00:00
marius
6637c2369d Remove redundant checking of sc_leaving (uart_intr() already handles this).
Approved by:	marcel
2010-05-02 19:07:19 +00:00
imp
17cb7ef363 Enable AH_RXCFG_SDMAMW_4BYTES option. See NOTES file for why this is
workaround (WAR) is needed.
2010-05-01 16:39:46 +00:00
imp
a54f37f512 Put the -current debugging options back into AR71XX. 2010-05-01 16:38:40 +00:00
rrs
c5fa73f93d Bug in the memory mapping module. The wrong
physaddr was being used in the macro (1 should be
used not 2)...

Obtained from:	JC
2010-04-30 17:12:20 +00:00
kmacy
1dc1263413 On Alan's advice, rather than do a wholesale conversion on a single
architecture from page queue lock to a hashed array of page locks
(based on a patch by Jeff Roberson), I've implemented page lock
support in the MI code and have only moved vm_page's hold_count
out from under page queue mutex to page lock. This changes
pmap_extract_and_hold on all pmaps.

Supported by: Bitgravity Inc.

Discussed with: alc, jeffr, and kib
2010-04-30 00:46:43 +00:00
alc
ab8f1a2302 Adapt i386 r207205 to mips: Clearing PV_TABLE_REF and setting the page's
PG_REFERENCED flag in pmap_protect() can't really be justified, so don't
do it.
2010-04-28 04:25:36 +00:00
kib
e20b2d597f Style: use #define<TAB> instead of #define<SPACE>.
Noted by:	bde, pluknet gmail com
MFC after:	11 days
2010-04-27 09:48:43 +00:00
alc
0a905b1db9 Resurrect pmap_is_referenced() and use it in mincore(). Essentially,
pmap_ts_referenced() is not always appropriate for checking whether or
not pages have been referenced because it clears any reference bits
that it encounters.  For example, in mincore(), clearing the reference
bits has two negative consequences.  First, it throws off the activity
count calculations performed by the page daemon.  Specifically, a page
on which mincore() has called pmap_ts_referenced() looks less active
to the page daemon than it should.  Consequently, the page could be
deactivated prematurely by the page daemon.  Arguably, this problem
could be fixed by having mincore() duplicate the activity count
calculation on the page.  However, there is a second problem for which
that is not a solution.  In order to clear a reference on a 4KB page,
it may be necessary to demote a 2/4MB page mapping.  Thus, a mincore()
by one process can have the side effect of demoting a superpage
mapping within another process!
2010-04-24 17:32:52 +00:00
kib
e91c695f77 Move the constants specifying the size of struct kinfo_proc into
machine-specific header files. Add KINFO_PROC32_SIZE for struct
kinfo_proc32 for architectures providing COMPAT_FREEBSD32. Add
CTASSERT for the size of struct kinfo_proc32.

Submitted by:	pluknet
Reviewed by:	imp, jhb, nwhitehorn
MFC after:	2 weeks
2010-04-24 12:49:52 +00:00
jmallett
671efe7b22 Most MIPS systems have a comparatively-sparse physical memory layout. Switch
to using the sparse physseg layout in the VM system.
2010-04-24 03:11:35 +00:00
jmallett
dadc7f0ec4 Build some nops into CLEAR_STATUS here to make sure that the following
instructions can't be interrupted.
2010-04-23 19:48:31 +00:00
jmallett
d92d4020c1 o) Remove default MAXMEM on SWARM; pmap can readily use lmem for >512M
physical addresses.
o) Set a local maxmem in sb_machdep.c to avoid trying to use pages over 2^64
   under 32-bit ABIs.  Our pmap needs corrected to use vm_paddr_t consistently,
   then we can make vm_paddr_t 64-bit under 32-bit ABIs and add code in pmap
   to limit phys_avail by the maximum PFN that a 32-bit PTE can hold.
2010-04-23 19:20:56 +00:00
jmallett
57dd8a9a91 Large memory mappings are always CPU local and always done with interrupts
disabled.  Be doubly-sure that we don't try to do a TLB shootdown on SMP
systems for those mappings.

Submitted by:	C. Jayachandran
2010-04-23 18:53:17 +00:00
neel
ea6f8179e3 Fix compilation error.
tick.c:298:5: error: "KDTRACE_HOOKS" is not defined
2010-04-23 01:34:01 +00:00
thompsa
bd3f3db8dd Change USB_DEBUG to #ifdef and allow it to be turned off. Previously this had
the illusion of a tunable setting but was always turned on regardless.

MFC after:	1 week
2010-04-22 21:31:34 +00:00
rpaulo
6731bb89eb Add the necessary hooks for dtrace cyclic module. 2010-04-20 17:22:20 +00:00
rpaulo
6e49a8c185 Remove svn:executable prop. 2010-04-20 10:42:08 +00:00
jmallett
80306ecde6 Fix MALTA64 build. 2010-04-19 09:03:34 +00:00
jmallett
e77e469af2 Remove unused file. 2010-04-19 07:51:57 +00:00
jmallett
f845b731f7 o) Eliminate the "stand" frame and its use. Use CALLFRAME_* everywhere.
o) Use <machine/asm.h> macros for register-width, etc., rather than doing it
   by hand in a few more assembly files.
o) Reduce diffs between various bits of TLB refill code in exception.S and
   between interrupt processing code.
o) Use PTR_* to operate on registers that are pointers (e.g. sp).
o) Add and use a macro, CLEAR_PTE_SWBITS rather than using the
   mysteriously-named WIRED_SHIFT to select bits to truncate when loading PTEs.
o) Don't doubly disable interrupts by moving zero to the status register,
   especially since that has the nasty side-effect of taking us out of 64-bit
   mode.
o) Use CLEAR_STATUS to disable interrupts the first time.
o) Keep SR_PX set as well as SR_[KSU]X when doing exception processing.  This
   is the bit that determines whether 64-bit operations are allowed.
o) Don't enable interrupts until configure_final(), like most other ports.
2010-04-19 07:34:26 +00:00
jmallett
7e6abd8eb5 o) Fix XKPHYS physical address extraction. Also define cache coherency
attributes for XKPHYS.
o) Make coprocessor 0 accessor function macros for register+selector registers
   take the full name so that e.g. (as done in this commit), prid selector 1
   can be written through mips_wr_ebase() rather than mips_wr_prid1().
o) Allow for sign extension of 32-bit segment addresses.
o) Remove an unused MIPS-I register number.
2010-04-19 06:01:58 +00:00
jmallett
4f9a815abe o) Add a VM find-space option, VMFS_TLB_ALIGNED_SPACE, which searches the
address space for an address as aligned by the new pmap_align_tlb()
   function, which is for constraints imposed by the TLB. [1]
o) Add a kmem_alloc_nofault_space() function, which acts like
   kmem_alloc_nofault() but allows the caller to specify which find-space
   option to use. [1]
o) Use kmem_alloc_nofault_space() with VMFS_TLB_ALIGNED_SPACE to allocate the
   kernel stack address on MIPS. [1]
o) Make pmap_align_tlb() on MIPS align addresses so that they do not start on
   an odd boundary within the TLB, so that they are suitable for insertion as
   wired entries and do not have to share a TLB entry with another mapping,
   assuming they are appropriately-sized.
o) Eliminate md_realstack now that the kstack will be appropriately-aligned on
   MIPS.
o) Increase the number of guard pages to 2 so that we retain the proper
   alignment of the kstack address.

Reviewed by:	[1] alc
X-MFC-after:	Making sure alc has not come up with a better interface.
2010-04-18 22:32:07 +00:00
rpaulo
9fd0c26e30 Delete svn:executable prop. 2010-04-18 18:43:36 +00:00
jmallett
e80036d4ce o) Make pcb_onfault a pointer rather than an obscure integer value.
o) Mask off PAGE_MASK bits in pmap_update_page, etc., rather than modifying the
   badvaddr in trapframe.  Some nearby interfaces already did this.
o) Make PTEs "unsigned int" for now, not "unsigned long" -- we are only ready
   for them to be 32-bit on 64-bit platforms.
o) Rather than using pmap_segmap and calculating the offset into the page table
   by hand in trap.c, use pmap_pte().
o) Remove unused quad_syscall variable in trap.c.
o) Log things for illegal instructions like we do for bad page faults.
o) Various cast cleanups related to how to print registers.
o) When logging page faults, show the page table information not just for the
   program counter, but for the fault address.
o) Modify support.S to use ABI-neutral macros for operating on pointers.
o) Consistently use CALLFRAME_SIZ rather than STAND_FRAME_SIZE, etc.
o) Remove unused insque/remque functions.
o) Remove some coprocessor 0 accessor functions implemented in assembly that
   are unused and have inline assembly counterparts.
2010-04-17 09:42:07 +00:00
jmallett
28ca0d5c4c o) Add NPDEPG, like NPTEPG but for PDEs.
o) Remove NBPG, PGOFSET and PGSHIFT.  Use the standard names.
o) Remove some unused macros and move things from param.h to vmparam.h that
   belong in the latter.  (Actually, all of the kernel segment values, virtual
   addresses, etc., belong in one place, but this is a step in the right
   direction.)
2010-04-17 07:20:01 +00:00
jmallett
20c142c863 o) Add SMP support for Octeon using U-Boot to launch all the processors at the
same time.
o) Remove some unused trivial uart functions from octeon_machdep now that the
   uart part is fully working and they are unused.
o) Use __func__ instead of __FUNCTION__.
o) Use intr_*() instead of other routines that do the same thing.
o) Remove some duplicate printfs from the Octeon port, as well as duplicate
   setting of Maxmem.
o) Use the right frequency divider on Octeon.
o) Use PCPU_GET(cpuid) consistently to get the cpuid of the running core.
o) Remove some unused macros in the Octeon port.
o) Use mips_sync() around use of the global dpcpu, whose value may not be
   visible to APs at first.
o) When loading the first thread's stack, use macros to make the code correct
   for n64 as well.
o) Remove stub, do-nothing FAU init/enable/disable functions from the RGMX
   driver.
2010-04-17 03:08:13 +00:00
jmallett
175b654e30 o) Back out my previous change to SWARM; some of it was to address an issue
that turned out to be unrelated, and the rest was, as pointed out by Neel,
   just wrong-headed.
o) Tweak mem.c to fix use of /dev/kmem for direct-mapped addresses.
2010-04-17 01:49:50 +00:00
jmallett
5605409291 o) Use inline functions to access coprocessor 0 registers rather than external
ones implemented using assembly.
o) Use TRAPF_USERMODE() consistently rather than USERMODE().  Eliminate
   <machine/psl.h> as a result.
o) Use intr_*() rather than *intr(), consistently.
o) Use register_t instead of u_int in some trap code.
o) Merge some more endian-related macros to machine/asm.h from NetBSD.
o) Add PTR_LI macro, which loads an address with the correct sign-extension for
   a pointer.
o) Restore interrupts when bailing out due to an excessive IRQ in
   nexus_setup_intr().
o) Remove unused functions from psraccess.S.
o) Enter temporary virtual entries for large memory access into the page tables
   rather than simply hoping they stay resident in the TLB and we don't need to
   do a refill for them.
o) Abstract out large memory mapping setup/teardown using some macros.
o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just
   like we do when we can use the direct map.
2010-04-17 01:17:31 +00:00
jmallett
37d2dea4b8 o) Remove code related to VM_ALLOC_WIRED_TLB_PG_POOL, VM_KERNEL_ALLOC_OFFSET
and floating pages.  They are unused and unsupported.
2010-04-17 00:05:22 +00:00
jmallett
1bf63ac57f Adjust limits and formats for ABIs with 64-bit longs. 2010-04-16 23:54:56 +00:00
jmallett
30418e2d5b o) Use the direct map where possible for uiomove_fromphys, based on code from
sparc64.
o) Use uiomove_fromphys rather than the broken fpage mechanism for /dev/mem.
o) Update sf_buf allocator to not share buffers and to do a pmap_qremove when
   done with an sf_buf so as to better track valid mappings.
2010-04-16 23:48:28 +00:00
jmallett
e6b677fd6b o) Fix the intr_* functions to not spam the whole status register, just the IE
bit.
o) Remove some unused inlines.
o) Generate CP0 access functions for 64-bit TLB registers when building for
   n64.
o) Add an inline function version of the COP0_SYNC macro.
2010-04-16 23:46:30 +00:00
jmallett
d65d74bd7e Set KERNLOADADDR and TARGET_BIG_ENDIAN for SWARM. 2010-04-16 23:42:19 +00:00
jmallett
d54e6dc056 Remove some unused header files. 2010-04-16 02:56:24 +00:00
neel
b9f6788a74 Destroy the pmap 'pm_mutex' in pmap_release() otherwise we will panic
subsequently in pmap_pinit() with the following signature:

panic: lock "pmap" 0xc7878bc8 already initialized

This bug was uncovered by the changes made to vm_map.c in r206140.
2010-04-14 01:57:53 +00:00
neel
88551608b7 Revert the vm_machdep.c part of r205072.
This causes a panic in vm_thread_dispose() when it tries to add this kstack
to the kstack cache. This happens only when 'td_kstack' is not (PAGE_SIZE * 2)
bytes aligned and we have unmapped the page at that address in cpu_thread_alloc.

Pointed out by: nwhitehorn@
2010-04-14 01:29:31 +00:00
nwhitehorn
4f086c2604 Fix a bug where bus_dma_load_xxx() would not bounce misaligned buffers
due to rounding the buffer's physical address to the beginning of its
page. This fixes a panic in arge(4) when using PPPoE.

Reported by:	Jakob van Santen <vansanten at wisc dot edu>
Reviewed by:	gonzo
Obtained from:	amd64
2010-04-09 01:14:11 +00:00
imp
7631143fbc Add BUS_SPACE_UNRESTRICTED and define it to be ~0, just like all the
other platforms.
2010-04-08 19:34:55 +00:00
gonzo
e6a0269fc1 - Fix mutex type for miibus_mtx: it's not spinlock, it's def lock 2010-04-08 18:32:13 +00:00
imp
edd9981893 Enable module builds now that the build completes for them. This
should get them into the universe rotation.
2010-03-29 22:03:55 +00:00
neel
8457716f88 Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.
Obtained from NetBSD.

Suggested by: jmallett@
2010-03-26 07:15:27 +00:00
nwhitehorn
d63c82a6ac Change the arguments of exec_setregs() so that it receives a pointer
to the image_params struct instead of several members of that struct
individually. This makes it easier to expand its arguments in the future
without touching all platforms.

Reviewed by:	jhb
2010-03-25 14:24:00 +00:00
neel
3f8aee1ae5 Fix periodic "t_delta 16.01359db7eb5eb3c0 too long" messages on the console by
accounting for the "lost time" between when the timer interrupt fired
and when clock_intr() actually started executing.
2010-03-24 04:52:15 +00:00
neel
e17e52b7e2 Sibyte provides a 64-bit read-only counter that counts at half the processor
frequency. This counter can be accessed coherently from both cores.

Use this as the preferred timecounter for the SWARM kernels.

The CP0 COUNT register is unusable as the timecounter on SMP platforms because
the COUNT registers on different CPUs are not guaranteed to be in sync.
2010-03-20 05:49:06 +00:00
neel
acca987bde Make sure that the registers 'v0' and 'v1' are properly sign-extended
when sb_load64() returns.

Some 32-bit arithmetic operations (e.g. subu) have unpredicatable results
when operating on 64-bit registers that are not properly sign-extended.
2010-03-20 05:21:14 +00:00
neel
7d29901d9a Get rid of unused macro MIPS_MEM_RID.
Suggested by: Alexandr Rybalko (ray@dlink.ua)
2010-03-20 05:10:44 +00:00
neel
e2666e6dbe This change enables use of physical memory that is beyond the direct
mapped kseg0 region.

The basic idea is to use KVA from the kseg2 region for mapping page
table pages that lie beyond the direct mapped region.

The TLB miss handler can now recursively fault into the TLB invalid
handler if it dereferences a kseg2 page table page address that is not
in the TLB.

Tested by: JC (c.jayachandran@gmail.com)
2010-03-20 05:07:15 +00:00
imp
40e45eec2f Go ahead and add USB support to the generic config. 2010-03-14 19:04:42 +00:00
jmallett
82f04b0d18 o) Use octeon_fpa_alloc_phys in a situation in which we don't need a usable
pointer, rather than octeon_fpa_alloc.
o) Report half duplex status properly.
o) Do not unconditionally update the last known link status in the softc.  If
   report_link isn't set, when octeon_rgmx_config_speed is called the first
   time it will tell the driver (essentially) that we have already marked the
   interface up.  Likewise, don't change media speed and duplex if only the
   link status is at issue. [1]
o) Remove manual changing of link state and let octeon_rgmx_config_speed do the
   heavy lifting. [1]

Reviewed by:	[1] imp
Sponsored by:	Packet Forensics
2010-03-13 04:55:47 +00:00
neel
68a0cae516 - Enable kernel stack guard page.
- Unmap the unused kernel stack page that we cannot use because it is
  not aligned on a (PAGE_SIZE * 2) boundary.
2010-03-12 07:08:20 +00:00
neel
7ca6d1bcd1 Make the ddb command "show tlb" SMP friendly.
It now accepts an argument to dump out the tlb of a particular cpu.
2010-03-12 03:49:17 +00:00
jmallett
378ca3a5ee o) Send packets being queued for transmission up to BPF if there's a listener.
o) Properly configure the CAM to handle IFF_PROMISC and note where IFF_ALLMULTI
   handling would go if we didn't already force the NIC to receive all
   multicast traffic.

Reviewed by:	imp
Sponsored by:	Packet Forensics
2010-03-12 02:56:45 +00:00
jmallett
afbdfb0b20 Add bpf and random to Octeon configurations, since they're needed to run
dhclient and ssh respectively.

Reviewed by:	imp
2010-03-11 22:29:45 +00:00
jmallett
cff76e4af9 Don't force single user on Octeon anymore. 2010-03-11 22:25:53 +00:00
jmallett
39d70443d4 o) Eliminate use of sc->typestr, which is always NULL.
o) Inline octeon_rgmx_mark_ready into octeon_rgmx_init.
o) Add a media status handler that reports link and media status.
o) Set link state when if_init is called.
o) Remove some printfs related to driver state changes.
o) Remove some gratuitous comments.

Reviewed by:	imp
Sponsored by:	Packet Forensics
2010-03-11 22:22:06 +00:00
neel
8d52301484 Stash the context of the running thread at the time an IPI_STOP is received
in 'stoppcbs[]'. We use the 'stoppcbs[]' context to generate the backtrace
of such stopped threads.
2010-03-11 07:17:14 +00:00
jmallett
296312c0a9 Check for device faults and for failures to set DRQ when expected, rather
than spinning forever.  This fixes booting with CF ejected.

NB: I've made the driver pretty chatty about errors in case there's hardware
    that operates differently to mine, so we can easily track down any issues.

Reviewed by:	imp
Sponsored by:	Packet Forensics
2010-03-06 05:49:15 +00:00
jmallett
411b18842a o) Consistently use MIPS_KSEGn_TO_PHYS instead of MIPS_{,UN}CACHED_TO_PHYS etc.
Get rid of the macros that spell KSEG0 CACHED and KSEG1 UNCACHED.
o) Get rid of some nearby duplicated and unused macros.

Reviewed by:	imp
2010-03-06 05:45:49 +00:00
jmallett
c941139fc2 o) Simplify the implementation of bus read/write functions, and eliminate some
redundant implementations.
o) Use ABI, not ISA, to determine address length.
o) Disable and restore interrupts around any operation that uses all 64 bits of
   a register.  In kernels using the O32 ABI, the upper 32 bits of those
   registers is likely to be corrupted by an interrupt.

Sponsored by:	Packet Forensics
2010-03-05 22:48:34 +00:00
jmallett
5a6a2a2345 Properly detect a type of real board that claims to have a 0.0 revision.
This fixes at least memory detection on that board.

Sponsored by:	Packet Forensics
2010-03-05 22:46:11 +00:00
jmallett
f1bff6675f Do not mask off the low byte of the chipid, it makes some of the case
statements unreachable and seems to be wrong.  Fixes detection of the number
of ports available on some models.

Sponsored by:	Packet Forensics
2010-03-05 22:44:49 +00:00
neel
5eff74740c Remove some unused cruft. 2010-03-04 05:37:19 +00:00
neel
78a2d25433 Add support for CPUs with cache coherent DMA. The two main changes are:
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
  requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp
2010-03-04 05:23:08 +00:00
imp
9b0f2419c1 Looks like S8 and SP are reversed in setjmp, so longjmp doesn't work
as well as one would hope....

Submitted by:	Arten Belevich
2010-03-03 21:28:55 +00:00
joel
2e980c4bcf The NetBSD Foundation has granted permission to remove clause 3 and 4 from
the software.

Obtained from:	NetBSD
2010-03-03 17:55:51 +00:00
gnn
acf511e4d0 Add support for hwpmc(4) on the MIPS 24K, 32 bit, embedded processor.
Add macros for properly accessing coprocessor 0 registers that
support performance counters.

Reviewed by:	jkoshy rpaulo fabien imp
MFC after:	1 month
2010-03-03 15:05:58 +00:00
imp
e901048f7a Spell START_FRAME CALLFRAME_SIZ now. 2010-03-03 02:46:36 +00:00
rrs
7a79101227 - Move rmi_pci_bus_space to header and avoid extern
- remove unused and commented code (MIPS_BUS_SPACE_PCI, pic_usb_ack)
- use rmi_pci_bus_space for USB too (needs byteswap)
- uncomment xls_ehci.c in files.xlr
- changes to xls_ehci.c - updated with dev/usb/controller/ehci_*.c as

Obtained from:	JC - c.jayachandran@gmail.com
2010-03-02 12:11:00 +00:00
imp
090d85f3f5 Update macros for multiple ABI support from NetBSD.
Also update SZREG define in ucontext
2010-03-02 07:27:30 +00:00
rrs
05c4bc6f8b Fix another fo-pa of mine... duplicate patches should
not be applied and randy needs coffee in the morning
when working to help keep things sorted out... obviously :-)
2010-02-21 17:27:20 +00:00
rrs
b41b03a2e0 Fix for the rge driver for boards without rge6 and rge7.
- changes to avoid adding theses instances on specific chips
Obtained from:	C. Jayachandran - JC - c.jayachandran@gmail.com
2010-02-20 17:24:33 +00:00
rrs
f70d155673 Changes for pci and pci-e support
- add bus_space_rmi_pci.c for PCI bus space
- files.xlr update for changes in files
- pcibus.c merged into xlr_pci.c (they were small files with inter-dependencies)
- xlr_pci.c - lot of changes here with few fixes, formatting cleanup
Obtained from:	C. Jayachandran (JC) - c.jayachandran@gmail.com
2010-02-20 17:19:16 +00:00
rrs
08e82a2182 Opps forgot to add this:
- add bus_space_rmi_pci.c for PCI bus space

Obtained from:	C. Jayachandran -  <c.jayachandran@gmail.com>
2010-02-20 17:12:07 +00:00
rrs
a1acb96630 Cleanups for sys/mips/rmi/bus_space_rmi.c
- remove pci related code from bus_space_rmi.c, we will have another
file for PCI bus space functions which will do byte-swapping.
- remove local SWAP implementation
- added TODO stub for unimplemented functions

Obtained from:	C. Jayachandran - c.jayachandran@gmail.com
2010-02-20 16:32:33 +00:00
rrs
c3a2e02803 Some fixes to the current RMI interrupt handling, changes in this patch are:
- (cleanup) remove rmi specific 'struct mips_intrhand' - this is no
longer needed since 'struct intr_event' have all the required hooks
- add xlr_cpu_establish_hardintr, which has args for pre/post ithread
and filter hooks, so that the PCI code can add the PCI controller
interrupt ack code here
- make 'cpu_establish_hardintr' use the above function.
- (fix) change type of eirr/eimr from register_t to uint64_t. These
have to be 64bit otherwise we cannot handle interrupts from 32.
- (fix) use eimr to mask eirr before checking interrupts, so that we
will not handle masked interrupts.

Obtained from:  C. Jayachandran - c.jayachandran@gmail.com
2010-02-20 16:30:29 +00:00
neel
60c69691d9 Fix DDB backtrace that includes a kernel exception frame.
The backtrace code tries to look for an instruction of the form "sw ra, x(sp)"
to figure out the program counter of the calling function. When we generate
the kernel exception frame we store the 'ra' at the time of the exception
using an instruction of the same form. The problem is that the 'ra' at the
time of the exception is not the same as the 'program counter' at the time
of the exception.

The fix is to save the 'exception program counter' register by staging
it through the 'ra' register.
2010-02-20 07:34:37 +00:00
neel
130eee4fb0 Get rid of unused options: KERNPHYSADDR, KERNVIRTADDR, PHYSADDR, PHYS_ADDR_64BIT
Discussed with: gonzo, imp
2010-02-20 06:39:14 +00:00
kan
6133908f1e Define DMA_RX_STATUS_OVERFLOW with correct value.
The RX overflow is reported in bit 2 on real hardware and Linux driver
for the same device already has this defined correctly.
This fixes frequent interrupt storms seen on RouterStation Pro boards.

Discussed with:	gonzo
2010-02-19 17:37:46 +00:00
imp
73f0ead32a Hack to make ALCHEMY compile again... 2010-02-18 19:41:38 +00:00
imp
e0d8c3f88b Make printfs work for both OCTEON1 and OCTEON1-32 2010-02-18 19:27:00 +00:00
imp
76db043a74 Parens around tertiary operator so that casting the result works... 2010-02-18 19:24:23 +00:00
imp
ad89e83094 Use proper structure type for 64-bit headers
# this fixes the MALTA64 build
2010-02-18 19:02:33 +00:00
neel
aa07cd3091 Kernel module support for mips.
Reviewed by: gonzo

Tested by: Alexandr Rybalko (ray@dlink.ua)
2010-02-18 05:49:52 +00:00
neel
35bb948988 Various fixes to get the SWARM config working on a big-endian Sibyte CPU.
Getting the little-endian PCI bus working on the big-endian CPU proved to be
quite challenging. We let the PCI devices be mapped in the "match byte lanes"
address window. This is where they are mapped by the CFE and DMA transfers
generated to or from addresses within this window are not subject to automatic
byte-swapping.

However any access by the driver to memory-mapped pci space is redirected
via the "match bit lanes" address window. We get the benefit of automatic
byte swapping through this address window and drivers don't need to change
to deal with CPU big-endianness.
2010-02-17 06:43:37 +00:00
gonzo
33dc2d8ede - Clean-up output of memory banks info 2010-02-16 00:08:42 +00:00
attilio
b9f41eb470 Adjust style (following the already existing rules) for the newly
introduced option DEADLKRES.

Reported by:	danfe, julian, avg
2010-02-15 23:44:48 +00:00
neel
f2eeadb198 Remove the PCI_IOSPACE_SIZE and PCI_IOSPACE_ADDR hack from nexus.c. Implement
this in the Sibyte PCI hostbridge driver instead.

The nexus driver sees resource allocation requests for memory and irq
resources only. These are legitimate resources on all MIPS platforms.

Suggested by: imp
2010-02-12 02:59:49 +00:00
attilio
184538e270 Add the options DEADLKRES (introducing the deadlock resolver thread) in
the 'debugging' section of any HEAD kernel and enable for the mainstream
ones, excluding the embedded architectures.
It may, of course, enabled on a case-by-case basis.

Sponsored by:	Sandvine Incorporated
Requested by:	emaste
Discussed with:	kib
2010-02-10 16:30:04 +00:00
rrs
1fff76b217 If a mbuf is split across two pages, we
have code that detects this and makes two
transmit descriptors. However its possible
that the algorithm detects when the second
page is not used (when the data aligns perfectly
to the bottom of the page). This caused a 0
len descriptor to be added which locks up the
rge device. Skip such things with a continue.

JC provided this patch... Thanks JC :-)
Obtained from:	JC (c.jayachandran@gmail.com)
2010-02-10 13:48:34 +00:00
neel
5087b7bd59 Code cleanup:
- make some variables static
- remove unused variables.
2010-02-10 06:57:05 +00:00
neel
823d0c1a02 Call profclock() and statclock() explicitly on all cpus. Prior to this
change these functions were called only on the BSP indirectly via hardclock().

top -P now shows usage statistics of all cpus.
2010-02-10 06:29:43 +00:00
neel
ae237abf20 Enable interrupts before doing AST processing to avoid a deadlock.
Specifically on an SMP kernel it was observed that if both the
processors are doing an exit1() via ast()->postsig()->sigexit()
then we will deadlock.

This happens because exit1() calls vmspace_exit() that in turn
calls pmap_invalidate_all(). This function tries to do a
smp_rendezvous() which blocks because the other processor is not
responding to IPIs - because it too is doing AST processing with
interrupts disabled.
2010-02-10 05:43:31 +00:00
neel
91212ae23c SMP support for the mips port.
The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.

Reviewed by: imp, rrs
2010-02-09 06:24:43 +00:00
neel
f6bab2156a Correct a comment - we are not setting the exception level but rather are
disabling interrupts.

Simplify register usage - we can directly load 'curpcb' into 'k1' after
interrupts are disabled. There is no need to do so indirectly through 'a1'.
2010-02-05 06:36:03 +00:00
neel
0178318026 Initialize interrupt controller early on. 2010-02-05 03:22:04 +00:00
neel
5b7a1d2513 Reimplement all functions to access the system control unit in C.
The only reason we need to have the sb_load64() and sb_store64()
functions in assembly is to cheat the compiler and generate the
'ld' and 'sd' instructions which it otherwise will not do when
compiling for a 32-bit architecture. There are some 64-bit
registers in the SCD unit that must be accessed using 64-bit
load and store instructions.
2010-02-05 03:20:47 +00:00
neel
39dbfe1f76 style: don't need to use braces for single line control statements. 2010-02-05 02:40:42 +00:00
neel
aaf539f687 Compile SWARM with KTRACE support. 2010-02-04 06:44:42 +00:00
neel
c111af420c Get system call tracing using ktrace working for mips. 2010-02-04 06:42:30 +00:00
neel
61210c7a07 Clean up all places in exception.S that fiddle with 'pcpup' directly. We now
use the GET_CPU_PCPU() macro exclusively.

This isolates the users of pcpu data from its implementation details.

Reviewed by: imp
2010-02-04 05:25:59 +00:00
neel
1638fb996a Reduce the size of the array used to store the TLB mappings for the kernel
stack from 3 to 2.

We only map in 2 pages for the kernel stack.

Approved by: imp (mentor)
2010-02-03 04:09:36 +00:00
neel
f0bf9d2db5 Provide access to pcpu structures for SMP kernels.
The basic idea is to use a the same virtual address as a window onto
distinct physical memory locations - one per processor. The physical
address that you access through this mapping depends on which cpu you
are currently executing on. We can now use the same virtual address
on any processor to access its per-cpu area.

The details are:

- The virtual address for 'struct pcpu *pcpup' is obtained by
  stealing 2 pages worth of KVA in pmap_bootstrap().

- The mapping from the constant virtual address to a distinct
  physical page is done in cpu_pcpu_init() through a wired TLB entry.

- A side-effect of this is that we reserve 2 pages worth of memory
  for the pcpu but in reality it needs much less than that. The unused
  memory is now used as the boot stack for the BSP and APs.

Remove SMP-specific bits from locore.S. The plan is to use a separate
mpboot.S for AP bootstrap.

Discussed on: freebsd-mips

Approved by: imp (mentor)
2010-01-30 01:54:29 +00:00
rrs
c449575654 Follow Neel's suggestion and switch to using
restoreint() in combination with saving off the
old level. That way we don't blast out the old
level.
2010-01-29 05:38:41 +00:00
rrs
1a77a4ef9a For our memory re-mapping trick to work
interrupts must be disabled through the
page_zero's or copys etc. Note that the
temporary mapping used by panic's may
cause us pain since int's may not be disabled.
When we get dumps working we may have to revist
this. Note that with this fix the build got
much much further.. until it hung on disk IO (I
would imagine thats the rge/msgring driver acting
up).
2010-01-29 04:07:38 +00:00
rrs
74e6490161 Its possible that our RMI box has memory extending
above 4Gig. If so when we add the base address with
the size we will wrap. So for now we just ignore
such memory and only use what we can. When we
get 64 bit working then we will be much better ;->
2010-01-29 04:05:17 +00:00
rrs
644ee9feb9 Move ID up into comment block.. per bsdimp 2010-01-29 04:03:36 +00:00
gonzo
f9b5b5cdd2 - Increase timeouts to 100 milliseconds, 1 millisecond is definitely not
enough for PCI controller to get into shape

Thanks to: adrian@
2010-01-28 21:55:56 +00:00
imp
8f2999d880 Add Cavium's standard copyright to those files that are currently
lacking a copyright/license statement.  All these files were in the
Cavium FreeBSD source drop and appear to be written by Cavium (some
are nearly verbatim copies of files from the cnusers' 1.9.0 SDK, which
also uses this copyright).
2010-01-28 20:46:40 +00:00
imp
1056a1e9f5 We make it to single user well, but not so well to multi-user. Force
single user for the moment since that's a better experience for people
trying this code out...
2010-01-28 20:39:50 +00:00
imp
bb75574462 trim unused members of the softc. 2010-01-28 20:38:52 +00:00
cognet
b007106a58 Comment out any reference to ALCHEMY.hints until it's committed, to unbreak
make universe.

Spotted out by:	gahr
2010-01-28 14:59:16 +00:00
rrs
b8876b1cbe Fix two of the extended memory hacks. The copy pages
routine in one place was setting the valid2 bit to
2 not 1. This meant the PTE was NOT valid and so
you would crash.

In Zero Page there was a incorrect setting of
the valid bit AFTER the actual zero (opps)..

Hopefully this will fix the 0xc0000000 crashes
that I have been seeing (unless of course there are
other problems with these old hacks of mine to get
to memory above 512Meg)
2010-01-28 14:09:16 +00:00
rrs
7fa7beba1e Adds additional hacks for proper bits so that
the RMI/XLR has the COP0 and COP2 bits enabled
Plus it needs SX too. Thanks again for JC in
catching this ;-)

Submitted by:	JC (jayachandranc@netlogicmicro.com
2010-01-28 14:03:06 +00:00
rrs
c764df610e Make compilable.. i.e. the FreeBSD id I added must
be in comments.
2010-01-28 14:01:47 +00:00
rrs
35fcb712f9 Changes the msg ring so its a filter not a
handler. Somehow rrs missed this.. Thanks
to JC for catching this ;-)

Obtained from:	JC (jayachandranc@netlogicmicro.com
2010-01-28 14:01:16 +00:00
kan
5f3c60fd26 Do not leave dirty cache lines behind if bus_dmamap_sync was called
to invalidate memory chunk that starts or ends in the middle of
cache line.

This was responsible for one half of the problem preventing umass
to work reliably on some MIPS32 platforms. USBng needs to stop
sharing cache lines between DMA-able memory and other structures
to cure the other half.

Discussed with: imp, gonzo
2010-01-27 17:15:17 +00:00
imp
df636c5061 Make a note that this file is the 64-bit version and experimental and
point people at the OCTEON1-32 file instead.
2010-01-27 16:21:32 +00:00
imp
ce43c11d59 Move back to physical address 0x01000000. 0x00100000 seems to have
problems sometimes for reasons I haven't tracked down.
2010-01-27 16:15:19 +00:00
rrs
8ebfc85b25 Spacing changes in pic_ack and pic_delayed_ack 2010-01-26 14:33:57 +00:00
rrs
af6640b78e My current conf, that comes up but
locks up in make buildworld.

You need to follow the mips wiki for building
the nfs partition and setup things to mount there
(in the conf and in your bootp setup).
2010-01-26 05:17:03 +00:00
rrs
1998b27896 1) Make sure static is init'd to 0
2) In one place make sure we call the backup
   startup routine (from the timer).
2010-01-26 05:14:50 +00:00
rrs
5db9bca76f To prevent a LOR we need to pass in
a lock flag in the pic routines. In
some places we hold the pic lock, others
we do not.
2010-01-26 05:11:48 +00:00
rrs
c7c33d974e Fix up the msg ring driver a bit tighter
so that we don't loose an interrupt which
we appeared to be doing.
2010-01-26 05:10:10 +00:00
rrs
7fcbb3e319 Fixes setup of clock. It was not properly
initialized, thus backward time warnings
were being spewed to the console.
2010-01-26 05:07:41 +00:00
neel
481c7be91d Install the XTLB exception handler for Sibyte processors.
This is a workaround for the fact that the CFE is compiled as a 64-bit
application and therefore sets the SR_KX bit every time we call into
it (for e.g. console).

A TLB miss for any address above 0xc0000000 with the SR_KX bit set will
end up at the XTLB exception vector. We workaround this by copying the
standard TLB handler at the XTLB exception vector.

Approved by: imp (mentor)
2010-01-26 03:39:10 +00:00
neel
ff32b1a57a Add a DDB command "show trapframe" to dump out contents of the trapframe
specified by the first argument.

Approved by: imp (mentor)
2010-01-26 03:29:52 +00:00
neel
a7e2122422 Print the address of the base of the stackframe in DDB backtrace output.
Approved by: imp (mentor)
2010-01-26 03:24:11 +00:00
imp
15b870b9d9 Doh. Remove extra pcpu initialization that I thought was needed, but
isn't needed since we moved all that into mips_pcpu0_init.
2010-01-26 02:39:14 +00:00
neel
c282e9faa8 Fix a problem seen when a new process was returning to userland
through fork_trampoline.

This was caused because we were clearing the SR_INT_IE and setting
SR_EXL bits of the status register at the same time. This meant
that if an interrupt happened while this MTC0 was making its way
through the pipeline the exception processing would see the
status register with SR_EXL bit set. This in turn would mean that
the COP_0_EXC_PC would not be updated so the return from exception
would be to an incorrect address.

It is easy to verify this fix by a program that forks in a loop
and the child just exits:

	while (1) {
	pid_t pid = vfork();
	if (pid == 0)
	       _exit(0);
	if (pid != -1)
	       waitpid(pid, NULL, 0);
	}

Also remove two instances where we set SR_EXL bit gratuitously in exception.S.

Approved by: imp (mentor)
2010-01-26 02:26:04 +00:00
imp
4ac34cbf90 Export knowledge of the special bus space we use for the console to
obio.  Take advantage of the fact that obio only really supports uart
at the moment to use the uart bus tag always for IOPORT allocations.

# this needs to be redone to conform to FreeBSD standards and allow for
# additional drivers for SoC hardware to attach
2010-01-25 19:27:20 +00:00
imp
894160498a Turn on debugging on the fpa unit. Fix some printfs that were only
enabled for debugging.  This should be turned off before we release,
but we need it for the moment.
2010-01-25 19:25:21 +00:00
imp
7adf9507d9 Store the mutex in the correct location. Before, we were storing it
in the pcb at the td_lock offset, rather than in the struct thread at
the td_lock offset.  And we were storing a pointer to the old thread
rather than to the mutex.  Why this didn't always kill us, I'll never
know.

Fix an obsolete comment and update the prototype in the comments.
Also note what variables are in what registers since this function is
a little complex...

neel@ found this problem and proposed this fix.  This cures a number
of different problem reports out there, and gets us booting octeon to
the login prompt...

Submitted by:	neel@
Reviewed by:	rrs@, gonzo@
2010-01-25 19:01:38 +00:00
imp
0367f51ba3 Fix device name for root....
Indent rgmii correctly.
Remove stale comments.
2010-01-25 16:55:31 +00:00
imp
99646c7cca Comment out the led wheel code for the moment. Likely it shouldn't
even be here in the first place, but it is cool to see FreeBSD
scrolling on the LED pannel of the octeon board when we're running...
2010-01-25 16:44:18 +00:00
gonzo
8a360e9b89 - Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
    it's not neccessary and might destroy data pased by trampoline or
    boot loader
2010-01-25 00:44:05 +00:00
imp
f02d63f346 o Write the soft reset bit in the cavium core to reset. [1]
o panic if the board boot descriptor is too old...

Obtained from:	[1] looking at the cavium sdk's executive code
2010-01-24 18:05:38 +00:00
gonzo
a5fe9358cb - Introduce kernel_kseg0_end variable that marks first address in KSEG0
available for use. All data below this address considered to be used
    by kernel. Along with kernel own data it might be symbol tables
    prepeared by trampoline code, boot loader service data passed for
    further analysis by kernel, etc... By default kernel_kseg0_end points
    to the end of loaded kernel.

- Introduce mips_postboot_fixup function. It checks for symbol information
    copied by ELF trampoline and passes it to KDB
2010-01-24 03:10:48 +00:00
gonzo
d184a1dc59 - Copy symbol-related tables (.symtab and .strtab) to the end of
relocated kernel. We use magic number to signal kernel that
    symbol data is present.
2010-01-24 02:59:22 +00:00
rrs
6bfde02405 Changes the order of the setting the int happened (inside
the lock).
2010-01-24 01:06:02 +00:00
imp
c88be204c7 Eliminate octeonregs.h. It was a copy of maltaregs.h with
s/malta/octeon/gi done...
2010-01-23 06:42:47 +00:00
neel
bd8fb9e267 Remove Sibyte specific code from locore.S that sets the k0seg coherency.
Move it to platform_start() instead.

Approved by: imp (mentor)
2010-01-23 03:19:13 +00:00
imp
9ab59f4d1a Migrate from old "DDB" style debugger to newer KDB style. 2010-01-23 00:24:31 +00:00
imp
9a3fba3cb8 Update from old DDB convetion to initialize debugger to new KDB way.
Always call kdb_init().  If we have KDB enabled, then provide a handy
place to break to the debugger.
2010-01-23 00:18:12 +00:00
gonzo
b0ad2d975d - Add driver for PCF2123, SPI real time clock/calendar 2010-01-22 22:14:12 +00:00
imp
a3046a69ae Declare octeon_get_clock_rate, now exported from octeon_machdep 2010-01-22 20:44:34 +00:00
imp
f7666a8970 Remove some irrelevant commented out make options. 2010-01-22 20:42:18 +00:00
imp
624996d120 make note of the nonsensical nature of the values in this hints file. 2010-01-22 20:41:43 +00:00
imp
3a7c404577 o Add support for memory above 256MB on the octeon.
o Force the ebase to be 0x80000000 (the base that we're booted with may
  need to be respected in the future).
o Initialize the clock early so we can initialize the console early
o use panic where we can now use it.
o Tag some code for parsing the boot records as belonging in the cavium sdk.
o remove support for booting on ancient boards...

# we make it further in bootstrapping now: interrupts being enabled in the
# uarts are now taking us out, it seems, for reasons unknown.
2010-01-22 20:40:07 +00:00
imp
9b415a1d51 Create a method of last resort for rebooting the mips processor: jump
to the reset vector.  This works for many SoCs where other reset
hardware is either missing or unknown.
2010-01-22 20:32:07 +00:00
rrs
3fd2819818 This hopefully will fix the network problem I was seeing.
Basically the msg ring interrupt was being re-enabled
inside a spinlock as the thread set it self up for rescheduling.
This won't work since inside the re-enable is another
spin lock.. which means on return from the reenable
the  interrupts have been reenabled. Thus you would
get a clock int and end up panicing holding a spin
lock to long :-o
2010-01-22 14:25:17 +00:00
rpaulo
2b2ffe1ba2 Remove duplicate bootverbose increment. 2010-01-22 11:52:12 +00:00
imp
b8b846aa50 Add a suggested improvement. 2010-01-22 09:55:13 +00:00
imp
1ccb8e2172 Don't clear bss/sbss. The boot loader already does this. In addition,
the Cavium version of the boot loader puts data just after &end, so
our rounding up to the next page in clearing memory overwrote their
data, which meant we'd get a lot of wrong values for parameters to the
system.

While I'm here, remove argc/argv parsing.  Those values aren't passed
in via a0 and a1, so it was a guaranted panic on some boards.
2010-01-22 09:23:34 +00:00
imp
299ddaaf43 Jump to the mips reset vector. OR in the 0x80000000 for kseg0 and
cast it to a long so it will work on 64-bit targets.

reset now works on octeon, so I don't have to power cycle the board as
often.
2010-01-22 09:19:57 +00:00
neel
92755e4d60 Get rid of redundant setting of interrupt enable bit when restoring the status
register from the PCB.

Remove a couple of misleading comments while I am here. The comments are
misleading because they imply that interrupts will be enabled after the
status register is restored from the PCB. This is not the case because
the processor is at the exception level (SR_EXL is set).

Approved by: imp (mentor)
2010-01-21 02:21:31 +00:00
gonzo
5a5053f56c - Remove unnecessary register writes in activate_device
and deactivate_device
- Save state before attaching driver and restore it when
    detaching
- Clear CLK bit after last bit of byte has been sent over
    the bus providing falling edge for last byte in transfer
- Fix several places where CS0 was always assumed
- Add $FreeBSD$ to ar71xxreg.h
2010-01-21 00:15:59 +00:00
neel
7213068773 Get rid of unused function MipsTLBInvalidException().
Approved by: imp (mentor)
2010-01-20 14:21:28 +00:00
neel
b3c30e3c1e Make sure that interrupts are enabled when thread0 is running.
Approved by: imp (mentor)
2010-01-20 14:17:41 +00:00
jhb
0ab6ce0ba0 Move the examples for the 'hints' and 'env' keywords from various GENERIC
kernel configs into NOTES.

Reviewed by:	imp
2010-01-19 17:20:34 +00:00
imp
9dc568d9ce Place proper svn:keywords tag on all these files. They were created
somehow without them on projects/mips, and that mistake was propigated
over to head.

Submitted by:	rpaulo@
2010-01-12 21:17:36 +00:00
rpaulo
eac8869edf Add a regular comment explaining what this file is. 2010-01-12 20:55:12 +00:00
rpaulo
91b18adf8e Fix svn properties and remove a P4 keyword. 2010-01-12 20:52:41 +00:00
imp
24dcc74198 Correct a path in an include I missed earlier
Remove references to if_watchdog.  The rge_watchdog routine was empty anyway.
2010-01-11 17:29:20 +00:00
imp
9c4467c6ab Remove redundant interrupt mapper code. We don't need to disable the
interrupt sources feeding into a hardintr anymore. The
mips_mask_hard_irq() function does that for us while an interrupt is
being processed.

Submitted by:	neel@
2010-01-11 17:14:46 +00:00
imp
c7ec83b0be Get sb_zbpci.c compiling again after the macros PCI_BUSMAX,
PCI_SLOTMAX and PCI_FUNCMAX were moved to pcireg.h.

Submitted by:	neel@
2010-01-11 17:14:10 +00:00
imp
5a323364a3 Attempt to cope with the dev/rmi -> mips/rmi/dev move. 2010-01-11 04:49:44 +00:00