The Intel 2d driver calls modeset before reinstalling the handler on
a vt switch. This means that vblank status ends up getting cleared
after it has been setup. Restore saved values for the pipestat registers
rather than just wiping them out.
MFC after: 3 days
Use the vbl_lock when maniputlating the refcount. Eventually I want to
convert this to use our internal refcount code. Continue to use atomic
ops for manipulating vblank count since we access it often just for
reading.
MFC after: 3 days
Intel agrees with my reading of the docs, make it so for all G4X chips.
The new register also has a 32 bit width as opposed to 24 bits. Fix
things up so that the counters roll over properly.
MFC after: 3 days
When a vt switch occurs the irq handler is uninstalled. Interrupts
and the state tracking of what was enabled/disabled wasn't working
properly. This should resolve the reports of "slow windows" after a
vt switch, among other things. The radeon 2d driver seems to work a
bit more correctly than the Intel driver. With the Intel driver,
vblank interrupts will be enabled at system startup and will only
be disabled after an additional modeset (vt switch, dpms, randr event).
With this patch, I am able to run glxgears synced to vblank and
vt switch while it is running without ill effects.
MFC after: 3 days
after vt switch or suspend. I can't really test this on Intel right now
but I think I've heard reports of it on radeon as well. I can't break
it on the radeon here.
MFC after: 3 days
Tested on an HD3850 (RV670) on loan from Warren Block.
Currently, you need one of the following for this to be useful:
x11-drivers/xf86-video-radeonhd-devel (not tested)
xf86-video-ati from git (EXA works, xv is too fast)
xf86-video-radeonhd from git (EXA works, xv works)
There is no 3d support available from dri just yet.
MFC after: 2 weeks
at irq install/uninstall time, but when we vt switch, we uninstall the
irq handler. When the irq handler is reinstalled, the modeset ioctl
happens first. The modeset ioctl is supposed to tell us that we can
disable vblank interrupts if there are no active consumers. This will
fail after a vt switch until another modeset ioctl is called via dpms
or xrandr. Leading to cases where either interrupts are on and can't
be disabled, or worse, no interrupts at all.
MFC after: 2 weeks
Intel 855 chips present the same pci id for both heads. This prevents
us from attaching to the dummy second head. All other chips that I
am aware of either only present a single pci id, or different ids
for each head so that we only match on the correct head.
Approved by: kib@
MFC after: 2 weeks
ati pci gart to use bus_dma to handle the allocations. This fixes
a garbled screen issue on at least some radeons (X1400 tested). It is
also likely that this is the correct fix for PR# 119324, though that
is not confirmed yet.
Reviewed by: jhb@ (mentor, prior version)
Approved by: kib@
MFC after: 2 weeks
rs400/rs480 should clear the RADEON_BUS_MASTER_DIS bit. This should get
the rs485 IGP chips going again.
Approved by: jhb (mentor)
Obtained from: drm git master
Olaf Kirch noticed that the i915_set_status_page() function of the i915
kernel driver calls ioremap with an address offset that is supplied by
userspace via ioctl. The function zeroes the mapped memory via memset
and tells the hardware about the address. Turns out that access to that
ioctl is not restricted to root so users could probably exploit that to
do nasty things. We haven't tried to write actual exploit code though.
It only affects the Intel G33 series and newer.
Approved by: bz (secteam)
Obtained from: Intel drm repo
Security: CVE-2008-3831
but I inadvertently overwrote the change when I synced to git. Commit
the fix in both places, so this doesn't happen again.
Approved by: jhb (mentor)
MFC after: 2 weeks
will ease the identification of memory leaks as the OS will be able to track
allocations for us by malloc type. vmstat -m will show all of the
allocations.
Convert the calls to drm_alloc() and friends, which are used in shared code
to static __inline__ while we are here.
Approved by: jhb (mentor)
from operating on a list with a single item. This code is used much more by
the i915 driver with xorg-7.4. Correct it to match the actual linux
implementation.
Approved by: jhb (mentor)
busmastering support. This also adds register definitions for MSI support,
which we will be using shortly.
Approved by: jhb (mentor)
Obtained from: drm git master
We don't explicity check for error here and M_WAITOK will just put the
process to sleep waiting on resources to become available.
Suggested by jhb@
Approved by: jhb (mentor)
This reverts a private patch which is causing issues with many Intel chipsets.
I will review that patch and see what we need to do to fix it up later, but
for the time being, we will just get these chips working again.
This update contains a lot of code cleanup and is post gem merge
(no, we don't have gem support). It should prove much easier to read the
code now. A lot of thanks goes to vehemens for that work. I have adapted
the code to use cdevpriv for tracking per open file data. That alleviates
the old ugly hack that we used to try and accomplish the task and helped to
clean up the open / close behavior a good bit. This also replaces the hack
that was put in place a year or so ago to prevent radeons from locking up
with AIGLX enabled. I have had a couple of radeon testers report that it
still works as expected, though I no longer have radeon hardware to test with
myself. Other various fixes from the linux crew and Intel, many of
which are muddled in with the gem merge.
Approved by: jhb (mentor)
Obtained from: mesa/drm git master
MFC after: 2 weeks
After I removed all the unit2minor()/minor2unit() calls from the kernel
yesterday, I realised calling minor() everywhere is quite confusing.
Character devices now only have the ability to store a unit number, not
a minor number. Remove the confusion by using dev2unit() everywhere.
This commit could also be considered as a bug fix. A lot of drivers call
minor(), while they should actually be calling dev2unit(). In -CURRENT
this isn't a problem, but it turns out we never had any problem reports
related to that issue in the past. I suspect not many people connect
more than 256 pieces of the same hardware.
Reviewed by: kib
be un-cached. Our previous memory barrier was not sufficient. This patch
allocates the IGP GART tables using the BUS_DMA_NOCACHE flag to get these
cards working.
Approved by: kib
calls to bus_dma. There were multiple paths that held different locks or
no locks at all. This patch ensures that all of the calling paths drop
their lock(s) before calling drm_pci_alloc().
Reviewed by: kib
anholt thinks that he added this check as part of some regression testing,
but it is failing at least some of the time. I don't want to remove it
just yet. I added a bit of debugging to help identify the issue.
Approved by: kib
