Commit Graph

1156 Commits

Author SHA1 Message Date
kib
ce081b037e In r197963, a race with thread being selected for signal delivery
while in kernel mode, and later changing signal mask to block the
signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race
exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls.

Use kern_sigprocmask() instead of direct manipulation of td_sigmask to
reschedule newly blocked signals, closing the race.

Reviewed by:	davidxu
Tested by:	pho
MFC after:	1 month
2009-10-27 10:47:58 +00:00
marcel
aca95fc6eb Review previous change. It has no relation to the I-cache coherency
changes and thus unintentional.

Spotted by: rdivacky@
2009-10-21 18:44:00 +00:00
marcel
51bb720939 o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
    vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
    that translates the vm_map_t argumument to pmap_t.
o   Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
    it replaces the pmap_page_executable() function, added to solve
    the I-cache problem in uiomove_fromphys().
o   In proc_rwmem() call vm_sync_icache() when writing to a page that
    has execute permissions. This assures that when breakpoints are
    written, the I-cache will be coherent and the process will actually
    hit the breakpoint.
o   This also fixes the Book-E PMAP implementation that was missing
    necessary locking while trying to deal with the I-cache coherency
    in pmap_enter() (read: mmu_booke_enter_locked).

The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.
2009-10-21 18:38:02 +00:00
jhb
46e48eac25 Sync with other GENERIC kernel configs:
- Move USB serial drivers earlier to match their placement in other kernel
  configs.
- Add descriptions to various USB drivers.
- Move the USB wireless drivers into a new section.
- Add ulscom to the list of USB serial drivers.
2009-10-13 19:04:01 +00:00
kib
3547dab066 Define architectural load bases for PIE binaries. Addresses were selected
by looking at the bases used for non-relocatable executables by gnu ld(1),
and adjusting it slightly.

Discussed with:	bz
Reviewed by:	kan
Tested by:	bz (i386, amd64), bsam (linux)
MFC after:	some time
2009-10-10 15:31:24 +00:00
stas
b956b86033 - Drop unused pmap_use_l1 function and comment out currently unused
pmap_dcache_wbinv_all/pmap_copy_page functions which we might want
  to take advatage of later.  This fixes the build with PMAP_DEBUG
  defined.

Discussed with:	cognet
2009-10-05 10:08:58 +00:00
rpaulo
dd6f0c84fe Remove remaining bits of performance counter support.
Submitted by:	Tom Judge <tom at tomjudge.com>
2009-10-03 13:59:15 +00:00
bz
8e183cd852 Make sure that the primary native brandinfo always gets added
first and the native ia32 compat as middle (before other things).
o(ld)brandinfo as well as third party like linux, kfreebsd, etc.
stays on SI_ORDER_ANY coming last.

The reason for this is only to make sure that even in case we would
overflow the MAX_BRANDS sized array, the native FreeBSD brandinfo
would still be there and the system would be operational.

Reviewed by:	kib
MFC after:	1 month
2009-10-03 11:57:21 +00:00
rpaulo
d3d5e9896c Remove performance counter headers. This code came from NetBSD, but our
hardware perf. counter support is different, so we don't need these
files.

Reviewed by:	freebsd-arm (no comments)
2009-10-02 11:10:05 +00:00
rpaulo
aedd167c2c Promote the cpu_class local variable to global and expose it in md_var.h
Reviewed by:	freebsd-arm
2009-09-26 16:37:23 +00:00
alc
309c5ab06f Add a new sysctl for reporting all of the supported page sizes.
Reviewed by:	jhb
MFC after:	3 weeks
2009-09-18 17:04:57 +00:00
phk
e645b495ed Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating an
architecture specific include file containing the _ALIGN*
stuff which <sys/socket.h> needs.
2009-09-08 20:45:40 +00:00
kib
bae5df8cbb Reintroduce the r196640, after fixing the problem with my testing.
Remove the altkstacks, instead instantiate threads with kernel stack
allocated with the right size from the start. For the thread that has
kernel stack cached, verify that requested stack size is equial to the
actual, and reallocate the stack if sizes differ [1].

This fixes the bug introduced by r173361 that was committed several days
after r173004 and consisted of kthread_add(9) ignoring the non-default
kernel stack size.

Also, r173361 removed the caching of the kernel stacks for a non-first
thread in the process. Introduce separate kernel stack cache that keeps
some limited amount of preallocated kernel stacks to lower the latency
of thread allocation. Add vm_lowmem handler to prune the cache on
low memory condition. This way, system with reasonable amount of the
threads get lower latency of thread creation, while still not exhausting
significant portion of KVA for unused kstacks.

Submitted by:	peter [1]
Discussed with:	jhb, julian, peter
Reviewed by:	jhb
Tested by:	pho (and retested according to new test scenarious)
MFC after:	1 week
2009-09-01 11:41:51 +00:00
kib
d105721a22 Reverse r196640 and r196644 for now. 2009-08-29 21:53:08 +00:00
kib
9e8ade6852 Remove the altkstacks, instead instantiate threads with kernel stack
allocated with the right size from the start. For the thread that has
kernel stack cached, verify that requested stack size is equial to the
actual, and reallocate the stack if sizes differ [1].

This fixes the bug introduced by r173361 that was committed several days
after r173004 and consisted of kthread_add(9) ignoring the non-default
kernel stack size.

Also, r173361 removed the caching of the kernel stacks for a non-first
thread in the process. Introduce separate kernel stack cache that keeps
some limited amount of preallocated kernel stacks to lower the latency
of thread allocation. Add vm_lowmem handler to prune the cache on
low memory condition. This way, system with reasonable amount of the
threads get lower latency of thread creation, while still not exhausting
significant portion of KVA for unused kstacks.

Submitted by:	peter [1]
Discussed with:	jhb, julian, peter
Reviewed by:	jhb
Tested by:	pho
MFC after:	1 week
2009-08-29 13:28:02 +00:00
sam
d36ba1e7a4 revert r196600; didn't notice it'd been done already
Submitted by:	jhay
2009-08-27 17:55:44 +00:00
sam
37593ef181 enable mesh by default 2009-08-27 17:33:44 +00:00
raj
5f0a3583a9 Introduce SheevaPlug support.
- The device is based on Marvell 88F6281 system on chip.
  - More info about the platform at http://www.plugcomputer.org

  - To build the FreeBSD kernel:
    make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG

  - Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 10:09:25 +00:00
raj
70c6d45902 Exclude common Kirkwood settings so they can be shared among various platforms
based on this SOC. This is a preliminary step for SheevaPlug support.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:39:11 +00:00
raj
f9b8acbebb Properly handle initial state of power mgmt.
Modules on Marvell SOC can be selectively PM-disabled, and we must not access
disabled devices' registers (attempt to initialize them) unconditionally, as
this leads to the system hang. This patch introduces graceful handling of the
PM state during devices init.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:35:50 +00:00
raj
c1a2d532dd Eliminate platform_pmap_init() to simplify Marvell bootstrap code. 2009-08-25 09:30:03 +00:00
cognet
e7e8031f23 KDB needs <machine/db_machdep.h>, so move it under #ifdef KDB.
While I'm there, remove dead code, we will never support acorn26.
2009-08-23 23:37:53 +00:00
cognet
58a0303f67 No need to remove the same flag multiple times. 2009-08-23 19:54:36 +00:00
stas
6e2c2e42f0 - Proprely intialize UART parameters at probe stage, so uart(4)
will initialize the FIFO memory correctly on attach.  Before
  that this values was intialized in only in at91_usart_bus_attach
  which is called after the uart(4) memory allocation happens.

Approved by:	re (kib)
MFC after:	1 week
2009-08-15 15:15:20 +00:00
raj
b1786d80d2 Use correct wbinv operation in pmap_l2cache_wbinv_range().
Submitted by:	Michal Hajduk
Reviewed by:	stas
Approved by:	re (kib)
Obtained from:	Semihalf
2009-08-13 15:56:09 +00:00
rwatson
fb9ffed650 Merge the remainder of kern_vimage.c and vimage.h into vnet.c and
vnet.h, we now use jails (rather than vimages) as the abstraction
for virtualization management, and what remained was specific to
virtual network stacks.  Minor cleanups are done in the process,
and comments updated to reflect these changes.

Reviewed by:	bz
Approved by:	re (vimage blanket)
2009-08-01 19:26:27 +00:00
jhb
44220d7e1e Add a new type of VM object: OBJT_SG. An OBJT_SG object is very similar to
a device pager (OBJT_DEVICE) object in that it uses fictitious pages to
provide aliases to other memory addresses.  The primary difference is that
it uses an sglist(9) to determine the physical addresses for a given offset
into the object instead of invoking the d_mmap() method in a device driver.

Reviewed by:	alc
Approved by:	re (kensmith)
MFC after:	2 weeks
2009-07-24 13:50:29 +00:00
raj
f7cf3989b3 Make dcache_inv_range() point to the proper routines on ARM9 and ARM9E/ARM10.
On some ARM variations CPU func dispatcher has the D-cache invalidate method
point to write-back invalidate, which is wrong, and can lead to a crash/panic
on affected platforms.

Spotted by:	HPS
Reviewed by:	cognet
Approved by:	re (kib)
2009-07-21 08:29:19 +00:00
raj
d1ac98198b ARM pmap fixes.
a)  nocache-remap problem

   When a page is remapped into a non-cacheable virtual memory region there
   was no associated write-back invalidate operation performed. We remove
   writeback of the original buffer size from bus_dmamem_alloc() and add
   appropriate L1/L2 flush operation.

b) missing write-back invalidate operation

   In pmap_kremove a page is removed so we must do a write-back
   invalidate operation aligned to the page virtual address.

Submitted by:	Michal Hajduk
Reviewed by:	Mark Tinguely, rpaulo, stas
Approved by:	re (kib)
Obtained from:	Semihalf
2009-07-20 07:53:07 +00:00
rpaulo
cb17ea0936 Add IEEE80211_SUPPORT_MESH, following similar change to nanobsd and
other GENERIC kernels.

Approved by:	re (kib)
2009-07-17 18:35:45 +00:00
alc
ea60573817 Add support to the virtual memory system for configuring machine-
dependent memory attributes:

Rename vm_cache_mode_t to vm_memattr_t.  The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.

Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.

Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes.  Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures.  The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map.  The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:

  kmem_alloc_contig() can now be used to allocate kernel memory with
  non-default memory attributes on amd64 and i386.

  vm_page_alloc() and the device pager will set the memory attributes
  for the real or fictitious page according to the object's default
  memory attributes.

Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.

Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386.  In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.

In collaboration with: jhb

Approved by:	re (kib)
2009-07-12 23:31:20 +00:00
sam
c67dff7aca Cleanup ALIGNED_POINTER:
o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v)
o define as "1" on amd64 and i386 where there is no restriction
o make the type returned consistent with ALIGN
o remove _ALIGNED_POINTER
o make associated comments consistent

Reviewed by:	bde, imp, marcel
Approved by:	re (kensmith)
2009-07-05 17:45:48 +00:00
raj
5f05e95e54 Map DPCPU pages into ARM kernel VA space.
DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.

Submitted by:	Michal Hajduk, Piotr Ziecik
Reviewed by:	cognet, stas
Approved by:	re (kib)
Obtained from:	Semihalf
2009-07-01 20:07:44 +00:00
alc
1ce12d013e Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
rwatson
be5740a255 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
alc
91cafd48b1 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00
sam
3627e1f44e temporarily disable optional uarts; apparently we hang when probing them
(and they are not present)
2009-06-25 18:07:19 +00:00
raj
2ee270938d Enable all populated TWSI (I2C) controllers on Marvell SOCs.
Obtained from:	Semihalf
2009-06-25 10:03:51 +00:00
cognet
4a7daf6d41 Fix typo. 2009-06-24 21:03:59 +00:00
cognet
cb4def77ea Fix typo. 2009-06-24 21:00:13 +00:00
raj
ea29110cd5 Introduce ata(4) support for Marvell integrated SATA controllers (found on
88F5xxx, 88F6xxx and MV78xxx system on chip devices).

Reviewed by:	stas
Obtained from:	Semihalf
2009-06-24 15:41:18 +00:00
jeff
5bc3a65e40 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
sam
5010737b39 Now that we have UARTs running with fast interrupt handlers the ata
driver's i/o ops must be locked to avoid chaos.  Extend the cambria
bus tag to support ata and add a spin lock.  The ata driver is
hacked to use that instead of it's builtin hack for ixp425.  Once
the ata driver is fixed to not be confused about byte order we can
generalize the cambria bus tag code and make it generally useful.

While here take advantage of our being ixp435-specific to remove
delays when switching between byte+word accesses and to eliminate
the 2us delay for the uarts (the spin lock overhead looks to do
this for us).
2009-06-23 19:29:23 +00:00
sam
880b7f2044 use consistent style 2009-06-23 19:05:02 +00:00
sam
f8f19f8c76 kill left over cruft 2009-06-22 23:22:38 +00:00
sam
3a5ae5dccd enable optional GPS+RS485 uarts 2009-06-22 22:54:44 +00:00
sam
0d93c7da52 o add a bus space tag that forces a 2usec delay between r/w ops; this is
used for the optional GPS+RS485 uarts on the Gateworks Cambria boards
  which otherwise are unreliable
o setup the hack bus space tag for the GPS+RS485 uarts
o program the gpio interrupts for the uarts to be edge-rising
o force timing on the expansion bus for the uarts to be "slow"

Thanks to Chris Lang of Gateworks for these tips.
2009-06-22 22:54:13 +00:00
sam
2fddb9e2cc fix typo 2009-06-22 22:47:06 +00:00
sam
b7d1149459 o remove hack to write UUE+RTOIE in the uart's IER; force them with hints
o honor hints for the rclk
2009-06-22 22:46:37 +00:00
sam
ff0565d717 hook arm_post_filter to ACK GPIO interrupts; this fixes the interrupt
storm observed on the GPS+RS485 uarts on Gateworks Cambria boards

Reviewed by:	cognet
2009-06-22 20:57:51 +00:00