blocked on it.
This is done by issuing a wakeup after clearing the 'vcpuid' from 'active_cpus'.
Also, use CPU_CLR_ATOMIC() to guarantee visibility of the updated 'active_cpus'
across all host cpus.
The NetBSD Foundation states "Third parties are encouraged to change the
license on any files which have a 4-clause license contributed to the
NetBSD Foundation to a 2-clause license."
This change removes clauses 3 and 4 from copyright / license blocks that
list The NetBSD Foundation as the only copyright holder.
Sponsored by: The FreeBSD Foundation
controller initialization.
The spec says OS drivers should send this command after controller
initialization completes successfully, but other NVMe OS drivers are
not sending this command. This change will therefore reduce differences
between the FreeBSD and other OS drivers.
Sponsored by: Intel
MFC after: 3 days
Fix logic error in the description of counter_u64_alloc: the command
may fail only if M_NOWAIT is specified, not M_WAITOK.
Reviewed by: glebius
MFC after: 2 weeks
Sponsored by: Spectra Logic Corporation
Replace usage of db_active in Xen console with kdb_active.
Reported by: Andrzej Tobola <ato@iem.pw.edu.pl>
Approved by: gibbs
Sponsored by: Citrix Systems R&D
- Display slice and partition as <auto> instead of 0 or -1 when they're
not set to specific values (the paritition=-1 was confusing folks).
- When loaderdev isn't set in the u-boot environment, say so rather
than displaying unknown device ''.
- Print the loader(8) ident/version info earlier, so that all device-
related info appears together afterwards.
The one change here that isn't purely cosmetic is to call setheap()
earlier. The comment says "Initialise heap as early as possible", now
that's more accurate. It shouldn't make any functional difference, but
may be safer if future changes lead to trying to allocate memory earlier.
As a prerequisite for multiple queues, the guest must have MSIX enabled.
Unfortunately, to work around device passthrough bugs, FreeBSD disables
MSIX when running as a VMWare guest due to the hw.pci.honor_msi_blacklist
tunable; this tunable must be disabled for multiple queues.
Also included is various minor changes from the projects/vmxnet branch.
MFC after: 1 month
don't do it also in ia64_handle_intr(). With ia64_handle_intr()
not saving and setting td_intr_frame, make sure to do it for
timer interrupts in ia64_ih_hardclock().
The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware. That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation. On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.
don't do it also in ia64_handle_intr(). With ia64_handle_intr()
not saving and setting td_intr_frame, make sure to do it for
clock interrupts in ia64_ih_clock().
helps when bits and pieces of GENERIC from i386 or amd64 are cut and
pasted into other architecture's config files (which in the case of
ARM had gotten rather akimbo).
are only used on armv6 when the vfp unit is detected. They will also be
available for the upcoming armv6hf platform, however while not used by
default there will need to be defined for any software that calls them
directly.
proprietary binary format.
* Add support for a diagnostic information error cause.
The code is sysctlable and the default is 0, which
means it is not sent.
This is joint work with rrs@.
MFC after: 1 week
further refinement is required as some device drivers intended to be
portable over FreeBSD versions rely on __FreeBSD_version to decide whether
to include capability.h.
MFC after: 3 weeks
draft POSIX.1e capability.h used on some systems (e.g., Linux). On
FreeBSD, leave a wrapper header so that current code continues to compile.
We will eventually want to deprecate the old header as the presence of a
capability.h may be confusing some configure scripts.
Suggested by: David Drysdale <drysdale at google.com>
Discussed on: cl-capsicum-discuss
MFC after: 3 weeks
chips have more.
So for now, let's allow more. We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.
later. If the interrupts are ACKed even if they're not masked, we get
the interrupts again later. Grr.
* The AR724x and later chips want the interrupt bits cleared by writing the
relevant bit to it, NOT by writing all but the current interrupt to it.
Tested:
* AR9344, DB120 reference board
TODO:
* Test ar724x and later chips to ensure no regressions have occured.
