Commit Graph

773 Commits

Author SHA1 Message Date
marius
d60b8a3096 Make the PCI code aware of PCI domains (aka PCI segments) so we can
support machines having multiple independently numbered PCI domains
and don't support reenumeration without ambiguity amongst the
devices as seen by the OS and represented by PCI location strings.
This includes introducing a function pci_find_dbsf(9) which works
like pci_find_bsf(9) but additionally takes a domain number argument
and limiting pci_find_bsf(9) to only search devices in domain 0 (the
only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are
changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order
to no longer report false positives when searching for siblings and
dupe devices in the same domain respectively.
Along with this change the sole host-PCI bridge driver converted to
actually make use of PCI domain support is uninorth(4), the others
continue to use domain 0 only for now and need to be converted as
appropriate later on.
Note that this means that the format of the location strings as used
by pciconf(8) has been changed and that consumers of <sys/pciio.h>
potentially need to be recompiled.

Suggested by:	jhb
Reviewed by:	grehan, jhb, marcel
Approved by:	re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
cognet
63a24fc32d Ok I hope I got it right this time.
After discussion with Sam, switch back to use firmware(9) instead of
having the firmware in hex format.
Put the binary firmware uuencoded into sys/contrib/dev/npe, and slap a
LICENSE file, as found on the Intel website.

Approved by:	re (blanket), mux (mentor)
MFC After:	1 week
2007-09-27 22:39:49 +00:00
cognet
a4964f6cfa Now that Intel changed the license for the NPE firmware, import it directly
hexed into our tree, instead of requiring the user to download it.

Approved by:	re (blanket)
MFC after:	1 week
2007-09-27 21:18:34 +00:00
cognet
8ce3a406bc Fix a comment to reflect the truth.
Spotted out by:	Marius Nuennerich <marius.nuennerich AT gmx D0T de>
Approved by:	re (blanket)
2007-09-27 20:52:17 +00:00
alc
d1bce06c64 Change the management of cached pages (PQ_CACHE) in two fundamental
ways:

(1) Cached pages are no longer kept in the object's resident page
splay tree and memq.  Instead, they are kept in a separate per-object
splay tree of cached pages.  However, access to this new per-object
splay tree is synchronized by the _free_ page queues lock, not to be
confused with the heavily contended page queues lock.  Consequently, a
cached page can be reclaimed by vm_page_alloc(9) without acquiring the
object's lock or the page queues lock.

This solves a problem independently reported by tegge@ and Isilon.
Specifically, they observed the page daemon consuming a great deal of
CPU time because of pages bouncing back and forth between the cache
queue (PQ_CACHE) and the inactive queue (PQ_INACTIVE).  The source of
this problem turned out to be a deadlock avoidance strategy employed
when selecting a cached page to reclaim in vm_page_select_cache().
However, the root cause was really that reclaiming a cached page
required the acquisition of an object lock while the page queues lock
was already held.  Thus, this change addresses the problem at its
root, by eliminating the need to acquire the object's lock.

Moreover, keeping cached pages in the object's primary splay tree and
memq was, in effect, optimizing for the uncommon case.  Cached pages
are reclaimed far, far more often than they are reactivated.  Instead,
this change makes reclamation cheaper, especially in terms of
synchronization overhead, and reactivation more expensive, because
reactivated pages will have to be reentered into the object's primary
splay tree and memq.

(2) Cached pages are now stored alongside free pages in the physical
memory allocator's buddy queues, increasing the likelihood that large
allocations of contiguous physical memory (i.e., superpages) will
succeed.

Finally, as a result of this change long-standing restrictions on when
and where a cached page can be reclaimed and returned by
vm_page_alloc(9) are eliminated.  Specifically, calls to
vm_page_alloc(9) specifying VM_ALLOC_INTERRUPT can now reclaim and
return a formerly cached page.  Consequently, a call to malloc(9)
specifying M_NOWAIT is less likely to fail.

Discussed with: many over the course of the summer, including jeff@,
   Justin Husted @ Isilon, peter@, tegge@
Tested by: an earlier version by kris@
Approved by: re (kensmith)
2007-09-25 06:25:06 +00:00
cognet
6055cf1f83 Make sure we do not call _arm_bzero() or _arm_memcpy() if the size is not at
least the minimum asked by the driver.

Approved by:	re (blanket)
2007-09-22 22:47:48 +00:00
cognet
20a45c5c15 Add various macros for the ADMA unit.
Approved by:	re (blanket)
2007-09-22 22:25:24 +00:00
cognet
6b6ebc8c90 Add a driver for the 7seg found on the CRB board, largely based on the
IQ31244 version.

Approved by:	re (blanket)
2007-09-22 16:25:43 +00:00
cognet
910d500785 Twist the RAS logic a bit to avoid branching.
MFC After:	1 week
Approved by:	re (blanket)
2007-09-22 14:23:52 +00:00
cognet
1c8ede1513 Remove dead code.
Approved by:	re (blanket)
Beer from:	jadawin
2007-09-19 15:30:25 +00:00
imp
cf6bc93f9b Kill bogus printf debugs.
Approved by: re@ (blanket)
2007-09-16 07:51:02 +00:00
imp
3bac12ad89 Kill overly verbose messages about setting bus width.
Approved by: re@ (blanket)
2007-09-16 07:48:58 +00:00
alc
20b10da706 It has been observed on the mailing lists that the different categories
of pages don't sum to anywhere near the total number of pages on amd64.
This is for the most part because uma_small_alloc() pages have never been
counted as wired pages, like their kmem_malloc() brethren.  They should
be.  This changes fixes that.

It is no longer necessary for the page queues lock to be held to free
pages allocated by uma_small_alloc().  I removed the acquisition and
release of the page queues lock from uma_small_free() on amd64 and ia64
weeks ago.  This patch updates the other architectures that have
uma_small_alloc() and uma_small_free().

Approved by: re (kensmith)
2007-09-15 18:47:02 +00:00
cognet
4e0d648ec9 It's probably time I learn C.
Fix a few while (!uart_getreg() & SR1_TNF) when
while (!(uart_getreg() & SR18TNF)) was really meant.
This driver should die anyway, it's awful, and uart_ns8250 should be fine
for the StrongArm 1110. I'll kill it later.

Submitted by:	Mikhael Skvorts
Approved by:	re (blanket)
2007-09-12 18:28:09 +00:00
cognet
31dec38dbc In __bswap16_var(), make sure the 16 upper bits are cleared; while
optimizing, gcc4 doesn't always do so.

Reported by:	Nathan Whitehorn
Approved by:	re (blanket)
2007-09-09 11:58:38 +00:00
cognet
79e92ec4ea There's no need to re-read PCIR_COMMAND once we set it.
Approved by:	re (blanket)
2007-09-04 18:45:27 +00:00
cognet
fad9eb8cfe Just wbinv if both PREREAD and PREWRITE are set.
In PREREAD, just invalidate the cache lines, and do not write back them, if
the buffer is properly aligned.

Approved by:	re (blanket)
2007-08-18 16:47:28 +00:00
cognet
1b5640bcfb Ooops, we need to define TD_LOCK here.
Approved by:	re (blanket)
Pointy hat to:	cognet
2007-08-08 09:27:52 +00:00
cognet
d893d60b08 Add cast to silent gcc warnings.
Approved by:	re (blanket)
2007-08-07 18:37:21 +00:00
cognet
14a1146e27 Use the third argument of cpu_switch(), as done for i386/amd63, as it is
required for ULE.

Approved by:	re (blanket)
2007-08-07 18:20:55 +00:00
imp
7e771d27fb Add in all the USB devices and all the wireless goo. The KB9202 has
only USB 1.1 speeds available, but this shouldn't hurt.  Now that we have
working usb support for this board, this is a natural followup.

Approved by: re (kensmith)
2007-07-31 17:45:54 +00:00
imp
4d0d4dac14 Make USB work on the KB9202{,A,B} boards. This has been in p4 for about
7 months.  You must have JP6 in the 1-2 position to supply power to the
USB devices, but I've used uftdi, uplcom and umass successfully.  If you
have it in 2-3, then nothing will show up.  Also, if you have the FQPA
packaging for the AT91RM9200 (like the KN9202 boards have), you will get
the following message

uhub0: device problem (IOERROR), disabling port 2

due to a hardware erratum.  It is safe to ignore as it is about pins that
aren't brought out on the FQPA package and aren't proeprly terminated either.
Alas, there's no register to read to tell the FQPA from the BGA versions.

Submitted by: Daan Vreeken
Approved by: re (kensmith)
2007-07-31 17:43:18 +00:00
cognet
99641742c6 MFppc:
revision 1.66
date: 2007/07/31 06:23:26;  author: marcel;  state: Exp;  lines: +2 -2
Fix backward compatibility of the "old" (i.e. FreeBSD6) lseek
syscall. It was broken when a new lseek syscall was introduced.
The problem is that we need to swap the 32-bit td_retval values
for the __syscall indirect syscall when the actual syscall has
a 32-bit return value. Hence, we need to exclude lseek(2). And
this means the "old" lseek(2) as well -- which we didn't.

Based on a patch from: grehan@

Approved by:	re (blanket)
2007-07-31 17:09:05 +00:00
cognet
d6b34bbb69 CRB config file.
Approved by:	re (blanket)
2007-07-27 14:57:03 +00:00
cognet
477cdd4e83 XScale core 3 definitions.
Approved by:	re (blanket)
2007-07-27 14:54:27 +00:00
cognet
a00e73f4ad Cleanup
Approved by:	re (blanket)
2007-07-27 14:53:42 +00:00
cognet
5d0ddbc52f Do not define NIRQ, it is already defined in include/intr.h
Approved by:	re (blanket)
2007-07-27 14:53:06 +00:00
cognet
fb0b75d6c4 Share the timer and watchdog drivers with the i81342. It's the same,
except it uses different registers.

Approved by:	re (blanket)
2007-07-27 14:52:04 +00:00
cognet
31da325f5f Add initial IOP342 support.
Thanks to Intel for providing sample hardware.

Approved by:	re (blanket)
2007-07-27 14:50:57 +00:00
cognet
1ee793cfc2 Say if the L2 cache is enabled or disabled as well.
Approved by:	re (blanket)
2007-07-27 14:49:11 +00:00
cognet
72f29f4f32 Handle supersections and L2 cache.
Approved by:	re (blanket)
2007-07-27 14:46:43 +00:00
cognet
70e7077c96 Use supersection instead of standard sections to map the whole memory
when available.

Approved by:	re (blanket)
2007-07-27 14:46:15 +00:00
cognet
123f2b86f7 Fix the cache mode description.
Approved by:	re (blanket)
2007-07-27 14:45:33 +00:00
cognet
8b22cea67f Properly handle supersections.
Make sure we cache entries in the L2 cache.

Approved by:	re (blanket)
2007-07-27 14:45:04 +00:00
cognet
d9f013dcfb Bring in two bandaids to get the elf trampoline to work again, until I find
a proper solution.
- Add a dummy entry point which just calls the C entry points, and try to make
sure it's the first code in the binary.
- Copy a bit more than func_end to try to copy the whole load_kernel()
function. gcc4 puts code behind the func_end symbol.

Approved by:	re (blanket)
2007-07-27 14:42:25 +00:00
cognet
30161fe629 Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.

Approved by:	re (blanket)
2007-07-27 14:39:41 +00:00
cognet
22beec041a Import xscale core 3 cache management functions.
Approved by:	re (blanket)
2007-07-27 14:28:15 +00:00
cognet
b1d9735f04 INTR_FILTER bits for arm
Approved by:	re (blanket)
2007-07-27 14:26:42 +00:00
cognet
25994fd742 The iop34x has 128 interrupts. 2007-06-16 15:03:33 +00:00
cognet
2349f48ce0 Introduce pmap_kenter_supersection(), which maps 16MB super-sections into
the kernel pmap.
Document a bit more the behavior of the xscale core 3.
2007-06-11 21:29:26 +00:00
imp
eed16ca559 Fix a spacing nit. 2007-06-11 19:36:37 +00:00
cognet
4042d45aba Initialize the dma tag's bounce_zone to NULL if we didn't allocate it. 2007-06-10 12:33:01 +00:00
marcel
75588c5a15 Add kdb_cpu_sync_icache(), intended to synchronize instruction
caches with data caches after writing to memory. This typically
is required to make breakpoints work on ia64 and powerpc. For
those architectures the function is implemented.
2007-06-09 21:55:17 +00:00
cognet
1f72bba084 There's no nobounce_dmamap on arm. 2007-06-07 21:51:09 +00:00
jeff
fe66d0ac91 - PCPU_ADD is no longer spelled with LAZY_ in the middle.
Submitted by:	attilio
2007-06-06 23:23:47 +00:00
jeff
be3241715a - Change comments and asserts to reflect the removal of the global
scheduler lock.

Tested by:      kris, current@
Tested on:      i386, amd64, ULE, 4BSD, libthr, libkse, PREEMPTION, etc.
Discussed with: kris, attilio, kmacy, jhb, julian, bde (small parts each)
2007-06-04 23:57:32 +00:00
attilio
e333d0ff0e Rework the PCPU_* (MD) interface:
- Rename PCPU_LAZY_INC into PCPU_INC
- Add the PCPU_ADD interface which just does an add on the pcpu member
  given a specific value.

Note that for most architectures PCPU_INC and PCPU_ADD are not safe.
This is a point that needs some discussions/work in the next days.

Reviewed by: alc, bde
Approved by: jeff (mentor)
2007-06-04 21:38:48 +00:00
marcel
c118c8a64b Revert to the previous version where the return value of uart_getenv()
is being ignored. It's optional and the lack of environment variable
is not an error condition.
2007-06-04 17:53:42 +00:00
alc
ccfe66d477 Add the machine-specific definitions for configuring the new physical
memory allocator.

Approved by:	re
2007-06-04 08:02:22 +00:00
attilio
7dd8ed88a9 Revert VMCNT_* operations introduction.
Probabilly, a general approach is not the better solution here, so we should
solve the sched_lock protection problems separately.

Requested by: alc
Approved by: jeff (mentor)
2007-05-31 22:52:15 +00:00