This gives +10% performance on simple tests, so definitly worth it.
A few percent more could be had by not using M_ZERO'd alloc's, but
we then need to clear fields all over the place to be safe, and
that was deemed not worth the trouble (and it makes life dangerous).
of the leftovers from the old version that really doesn't work anymore.
Add a reset function for host-end of the ATA channel. This is needed
for the SiI3112 in order to whack it back to reality if a device
locks up the SATA interface (thereby preventing that we can reset the
device). The result is that ATA now recovers from the timeouts that
happens with the SiI3112A and more or less all disks based on old
PATA electronics with a Marvell PATA->SATA converter. This includes
lots of the popular SATA dongles and the WDC Raptor disks..
Serialize access to the SATA channels, the chip messes up if
both channels are used at the same time.
The SiI3112 hereby takes the price as the most crappy SATA chip in
existance by a significant amount.
My advise to our userbase is to avoid this chip like the plague...
Setup decent transfer mode defaults as some BIOS's seem to put in
things that it *knows* doesn't work.
(Note to BIOS writers: stop doing that nonsense, we will get things
working with your crappy HW anyways, and then recommend users to buy
someone else's products that "just works", thankyou.. )
Limit the device transfer mode to ATA100/UDMA5 on generic SATA.
Since we dont know if the user is using a pure SATA device or an
old PATA drive with a SATA converter dongle, we need to limit the
speed used here to cover up the problems with Marvell ATA-SATA bridges
used in lots of SATA products.
This workaround is enabled for all detectable SATA controllers as they
seem to have semilar problems here. One notable exception is all the
Promise pdc2037x chips which just always work (cudos to Promise!).
in connection with Marvell based SATA->PATA dongles.
The problem was caused by a combination of things working
together to make it hard to spot...
The ATA driver has always started the ATA command, then build
the SG list for DMA and then finally started the DMA engine.
While this is according to specs, it poses a potential
problem as some controllers apparently do not allow for unlimitted
time between starting the ATA command and starting the DMA engine.
At about the same time as ATAng was committed there were lots
of other changes applied, some of which was locking in parts
that causes the busdma load functions to take significantly
longer to load the SG list.
This pushed the time spent between starting the ATA command and
starting the DMA engine over the hill for some controllers
(especially the Silicon Image DS3112a) and caused what looked
like lost interrupts.
The solution is to get all the SG list work or rather all
busdma related stuff done before we even try to start anything.
This has the nice side effect of seperating busdma out the
way it should be, so the working of the ATA machinery is not
cluttered up with busdma droppings, making the code easier
to read and understand.
Restructure the way ATA/ATAPI commands are processed, use a common
ata_request structure for both. This centralises the way requests
are handled so locking is much easier to handle.
The driver is now layered much more cleanly to seperate the lowlevel
HW access so it can be tailored to specific controllers without touching
the upper layers. This is needed to support some of the newer
semi-intelligent ATA controllers showing up.
The top level drivers (disk, ATAPI devices) are more or less still
the same with just corrections to use the new interface.
Pull ATA out from under Gaint now that locking can be done in a sane way.
Add support for a the National Geode SC1100. Thanks to Soekris engineering
for sponsoring a Soekris 4801 to make this support.
Fixed alot of small bugs in the chipset code for various chips now
we are around in that corner anyways.
real SATA disks now that I can test it.
Add support for the SiI 3112 SATA chip using memory mapped I/O.
Update the support for the SiI 0680 to use the memio interface as well.
Sponsored by: David Leimbach <leimy2k@mac.com> (3112 based controller)
Sponsored by: FreeBSD Systems (www.FreeBSDsystems.com) (SATA disks)
channel has been disabled by BIOS. This prevents a bus timeout
machine check on B&W G3 PowerMacs, which have a primary-only CMD646
on the motherboard.
Approved by: sos
Obtained from: NetBSD
project by providing documentation (under NDA) and hardware for
testing. This commit is the first result of the cooperation, and
adds support for several of their new controllers that we didn't
support before (and probably newer would have without this arrangement).
Add support for the Promise SATA150 TX2/TX4 and the Promise TX4000
controllers. This also adds support for various motherboard fitted
Promise SATA/ATA chips.
Note that this code uses memory mapped registers to minimize overhead.
I belive FreeBSD has made another first in the Open Source world
by being able to release support for this :)
Clean up the DMA interface too much unneeded stuff crept in with
the busdma code back when.
Modify the ATA_IN* / ATA_OUT* macros so that resource and offset
are gotten from a table. That allows for new chipsets that doesn't
nessesarily have things ordered the good old way. This also removes
the need for the wierd PC98 resource functions.
Tested on: i386, PC98, Alpha, Sparc64
This moves all chipset specific code to a new file 'ata-chipset.c'.
Extensive use of tables and pointers to avoid having the same switch
on chipset type in several places, and to allow substituting various
functions for different HW arch needs.
Added PIO mode setup and all DMA modes.
Support for all known SiS chipsets. Thanks to Christoph Kukulies for
sponsoring a nice ASUS P4S8X SiS648 based board for this work!
Tested on: i386, PC98, alpha and sparc64
