Commit Graph

2534 Commits

Author SHA1 Message Date
Luiz Otavio O Souza
f7eebb7730 Configure the analog input 7 which, on BBB, is connected to the 3V3B rail
through a voltage divisor (R163 and R164 on page 4 of BBB schematic).

Add a note about this on ti_adc(4) man page.  The ti_adc(4) man page will
first appear on 10.1-RELEASE.

MFC after:	1 week
Suggested by:	Sulev-Madis Silber (ketas)
Manual page reviewed by:	brueffer (D127)
2014-06-02 02:00:17 +00:00
Ruslan Bukin
0cd354a070 Add ident value. This fixes universe build.
Pointed out by:	andrew
2014-06-01 17:09:02 +00:00
Ruslan Bukin
53dc9d3d9c Fix i2c communication interface to be compatible with
vendor tools, e.g. embedded controller tool

Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-06-01 08:45:27 +00:00
Ruslan Bukin
08ae4ac990 Rename exynos uart driver filenames. 2014-06-01 08:34:45 +00:00
Ruslan Bukin
1e57235626 Add support for Exynos 5420 Octa - 8-core
heterogeneous (big.LITTLE) ARM machine
(4 x Cortex-A15 @ 1.8Ghz, 4 x Cortex-A7 @ 1Ghz)

Add configuration for Arndale Octa development board
2014-06-01 08:15:34 +00:00
Ruslan Bukin
058a928e4c Do only receive chars if there are some data in the buffer.
This fixes operation on newer Exynos boards.
2014-06-01 07:34:54 +00:00
Ganbold Tsagaankhuu
80ce0850f4 Silence tinderbox build.
Approved by:    stas (mentor)
2014-06-01 05:02:48 +00:00
Luiz Otavio O Souza
b1b4b37f4d Export two new settings for the AM335x PWM, the clock prescaler (clkdiv)
and the actual PWM frequency.

Enforce the maximum value for the period sysctl.

The frequency systcl now allows the direct setting of the PWM frequency (it
will try to find the better clkdiv and period for a given frequency, i.e.
the ones that will give the better PWM resolution).

This allows the use lower frequencies on the PWM.  Without changing the
clock prescaler the minimum PWM frequency was 1.52kHz.

PWM frequencies checked with an osciloscope.

PWM output tested with some R/C servos at 50Hz.
2014-06-01 03:57:57 +00:00
Ganbold Tsagaankhuu
75dc1c319b Add #NO_UNIVERSE to RADXA and RADXA-LITE kernel configs
since there aren't any new devices in those files so unhook them
from universe build.

Approved by:    stas (mentor)
2014-05-31 06:17:34 +00:00
Ruslan Bukin
45d909c6dc Reset HSIC hub during EHCI initialization. This makes devices connected
to external USB ports available to the system.

Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-30 07:48:55 +00:00
Ruslan Bukin
46eac58237 Fix off-by-one error that makes 0-th pins of each bank unreachable.
Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-30 07:43:55 +00:00
Ruslan Bukin
17f65b3a8d o Make keyboard-related properties to be compatible with vendor standard
o Allow setting keymap in FDT, use hardcoded one by default
o Represent fallback keymap as a list rather than directly usable M*N array

Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-30 06:45:50 +00:00
Ganbold Tsagaankhuu
1a31ec5e51 Add common kernel config file for Rockchip RK3188 systems by splitting
current RADXA config. Radxa Rock (RR) boards have few types such as
RR (full version), RR Lite and some variants of RR engineering samples.
Add kernel config and FDT file for RR Lite board.

Approved by:	stas (mentor)
2014-05-30 06:37:06 +00:00
Rui Paulo
38235b4177 Cleanup the RADXA kernel config file a bit and enable modules. 2014-05-30 05:17:14 +00:00
Olivier Houchard
d489d1f51f Do not hand the VM the memory used for stacks/page tables/etc. 2014-05-29 16:56:39 +00:00
Olivier Houchard
cb07f5b377 For old CPUs, map the 64 first MB of RAM as it used to be. Some ports
(XScale mainly) expects the memory located before the kernel to be mapped,
and use it to allocate the page tables, the various stacks, etc.
A better fix would probably be to rewrite the various bla_machdep.c to stop
using that RAM, but I'm not so inclined to do it, especially since I don't
have hardware for all of them.
2014-05-29 16:54:15 +00:00
Hans Petter Selasky
ad76ab4299 Factor out kernel configuration for DWC OTG FDT attach code. 2014-05-29 11:13:40 +00:00
Ruslan Bukin
3863e61d2e Add simple polling mechanism that works for KDB.
Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-28 06:15:45 +00:00
Ruslan Bukin
ff4590bed7 Describe I2C arbitrator device in DTS and use it for Chromebook Snow only.
Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-28 06:11:12 +00:00
Ruslan Bukin
0cd10310ad o Add kernel configuration for HP Chromebook 11
o Use machine codename in filenames
o Add GEOM_PART_GPT kernel option

Submitted by:	Maxim Ignatenko <gelraen.ua@gmail.com>
2014-05-28 06:00:55 +00:00
Andrew Turner
4eb12144c0 Rework the Ti GPIO driver to work on multiple SoCs. At the moment it could
work with OMAP4 and AM335x without needing to recompile.

Reviewed by:	loos
2014-05-26 18:02:36 +00:00
Zbigniew Bodek
1e17cf74b6 Delete obsolete and unused PJ4B CPU functions
Since PJ4Bv7 uses armv7_ CPU functions only pj4b_config
function is necessary. Remove obsolete routines.
2014-05-25 19:19:41 +00:00
Zbigniew Bodek
fd31d8bb75 Fix context switch on PJ4Bv7 and remove obsolete pj4b_/arm11 functions
Use armv7_setttb that sets proper PT attributes.
Get rid of unused CPU functions, put nullop instead.
Exchange obsolete pj4b_/arm11_ functions to the appropriate armv7_ ones.
2014-05-25 18:47:24 +00:00
Ian Lepore
cd21da8083 Fix whitespace glitches.
Pointed out by:	jhb
2014-05-25 14:01:30 +00:00
Andrew Turner
77a732bda5 Make ti_padconf_devmap static in both places it is defined. 2014-05-25 10:56:45 +00:00
Andrew Turner
0a8c1fdf5a Allow the OMAP4 and AM335x prcm drivers to be compiled in the same kernel
by renaming the structures used.
2014-05-25 10:49:07 +00:00
Andrew Turner
8166c218e6 Reduce the diff between the PandaBoard and BeableBone kernel configs to
help with the creation of a more generic Ti kernel config.
2014-05-25 10:17:26 +00:00
Zbigniew Bodek
94831f6d21 Enable automatic superpages promotion by default on ARMv6/v7
From now on superpages are enabled by default on ARM.
One can still disable superpages utilization by adding:

vm.pmap.sp_enabled=0

to loader.conf
2014-05-24 22:46:00 +00:00
Ian Lepore
11d47032ee Eliminate one of the causes of spurious interrupts on armv6. The arm weak
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.

This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.

Reviewed by:	cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after:	3 days
2014-05-24 16:21:16 +00:00
Warner Losh
32d5c97723 Remove NetBSD implementation details not relevant to FreeBSD. 2014-05-23 00:21:02 +00:00
Ian Lepore
97bbab9993 Map device memory using PTE_DEVICE attributes, and also ensure that the
shared flag is set on normal-memory mappings made via pmap_kenter() for SMP.

The "shared flag" part of this change isn't obvious from the diff, here's
the deal... by using the array of preformatted page table entry templates
instead of constructing the PTE from scratch, we automatically get the
right attribute bits set for both caching and shared.

MFC after:	1 week
2014-05-22 23:38:17 +00:00
Hans Petter Selasky
5c657683bb Optimise reading of pending interrupt registers. If there are no
pending interrupt bits, skip the bit iteration loop.

Reviewed by:	ian @
2014-05-20 15:03:23 +00:00
Andrew Turner
101355bc67 Allow us to compile the Ti iic driver for both OMAP4 and AM335x.
MFC after:	1 week
2014-05-17 18:52:20 +00:00
Andrew Turner
f37128c048 Move the Ti SoCs to use the ARM platform. This should help allowing a
single kernel to work on both PandaBoard and BeagleBone.
2014-05-17 18:35:22 +00:00
Andrew Turner
87ff982083 Add FDT_PLATFORM_DEF2 for when there are multiple platforms needing to use
the same platform methods.
2014-05-17 18:02:46 +00:00
Andrew Turner
92e7f50a4e Fix a comment s/initarm_/platform_/ 2014-05-17 11:29:44 +00:00
Andrew Turner
27521ff8e4 Add the start of the ARM platform code. This is based on the PowerPC
platform code, it is expected these will be merged in the future when the
ARM code is more complete.

Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.

Reviewed by:	ian@
2014-05-17 11:27:36 +00:00
Gavin Atkinson
015280f64c Fix spelling mistake in comment.
Spotted during:	http://www.bsdcan.org/2014/schedule/events/484.en.html
2014-05-16 21:20:13 +00:00
Ruslan Bukin
3d0bf6b1d0 Fix return value. Should be logic one or zero. 2014-05-15 10:06:59 +00:00
Mark Murray
7ff2eaaad3 Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.

The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.

One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.

Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.

Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.

Reviewed by:	ian@ (an earlier version)
Tested by:	ian@ (same earlier version)
Committed from:	WANDBOARD-QUAD
2014-05-14 19:11:15 +00:00
Ruslan Bukin
876ac29ddc Fix typo. 2014-05-14 14:19:57 +00:00
Aleksandr Rybalko
279204f2e0 Remove extra newlines.
No functional changes.

Sponsored by:	The FreeBSD Foundation
2014-05-14 11:15:48 +00:00
Ian Lepore
ad622f7078 Cleanup some style nits. 2014-05-12 13:08:37 +00:00
Ian Lepore
02bb9ba1cc Interrupts need to be disabled on entry to cpu_sleep() for ARM. Given
that and the need to be in a critical section when switching to idleclock
mode for event timers, use spinlock_enter()/exit() to achieve both needs.

The ARM WFI (wait for interrupt) instruction blocks until an interrupt is
asserted, and it will unblock even if interrupts are masked, and it will
unblock immediately if an interrupt is already pending.  It is necessary
to execute it with interrupts disabled, otherwise the interrupt that
should unblock it may occur and be serviced just prior to executing the
instruction.  At that point the system is inappropriately asleep until
the next timer tick or some other random interrupt happens.

In general, interrupts need to be disabled continuously from the time the
decision is made that there is no work to be done and sleeping is needed
until actually going to sleep, to avoid a race where handling a new
interrupt changes the basis for deciding there is no work to be done.

Submitted by:	hps@ (in slightly different form)
2014-05-12 13:05:03 +00:00
Ian Lepore
b07d0cbce3 Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().
On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus.  We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered.  Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller.  It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function.  It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.
2014-05-11 04:24:57 +00:00
Peter Grehan
ffd328487a Enable SMP for Exynos-based platforms (i.e. Chromebook)
Reviewed by:	br
2014-05-11 04:18:51 +00:00
Ian Lepore
6af0d51bce Make the hardware memory and instruction barrier functions work on armv4
and armv5 as well.
2014-05-11 00:43:06 +00:00
Andrew Turner
b36b897e51 Rename platform_gpio_init to be SoC specific 2014-05-10 21:30:19 +00:00
Andrew Turner
87ef4d1f85 Rename platform_gpio_init to be platform specific, and make it static as
it's only used from this file.
2014-05-10 20:31:05 +00:00
Andrew Turner
3664cbc0f0 Rename platform_gpio_init to be SoC specific, and make it static as it's
only called from this file.
2014-05-10 20:26:49 +00:00