taken from PR/121184 which was mechanically generated from similar
lists in the Linux ipaq driver. I then took the numbers we had in
usbdevs and filled in the right symbols and eliminated duplicates.
PR: 121184
When I was hacking on uart(4) to make it work with the MPSAFE TTY layer,
I noticed there was a difference between the way syscons and uart work
with respect to consoles:
- The uart(4) driver sets cn_name to the corresponding ttyu%r node,
which means init(8) (which opens /dev/console) will have its output
redirected to /dev/ttyu%r. After /etc/rc is done, it can spawn a getty
on that device node as well.
- Syscons used a little different approach. Apart from the /dev/ttyv%r
nodes, it creates a /dev/consolectl node. This device node is used by
moused and others to deliver their data, but for some reason it also
acts as a TTY, which shares its stat structure with ttyv0. This device
node is used as a console (run conscontrol).
There are a couple advantages of this approach:
- Because we use two different TTY's to represent the 0th syscons
window, we allocate two sets of TTY buffers. Even if you don't use
/dev/consolectl after the system has booted (systems that don't run
moused), it seems the buffers are still allocated.
- We have to apply an evil hack to redirect input to /dev/consolectl.
Because each window (stat) is associated not associated with one TTY,
syscons solves this by redirecting all input to closed TTY's to
consolectl.
This means that opening /dev/ttyv0 while in single user mode will
probably cause strange things to happen with respect to keyboard input
redirection.
The first patch that I discussed with philip@ turned consolectl into a
symlink to ttyv0, but this was not a good idea, because in theory we
would want consolectl to be a simple device node, which contains all the
`privileged' ioctl()'s. Apart from that, it didn't work, because each
time /dev/ttyv0 got revoked, moused also lost its descriptor to deliver
input, which meant you had to plug out/in your mouse to make it work
again. This version just leaves the consolectl device the way it is. It
can still be used to write output to ttyv0, but it can no longer receive
any input.
In my opinion this patch is not a complete solution, but it's already a
step in the good direction. It would allow us to turn consolectl into a
special (non-TTY) device node in the far future. It shaves off 15 KB of
wasted TTY buffer space.
Discussed with: philip
When I changed syscons(4) to work with the MPSAFE TTY code, I just
locked all device nodes down using the compatibility feature that allows
you to override the TTY's lock (Giant in this case). Upon closer
inspection, it seems sysmouse(4) only has two internal variables that
need locking: mouse_level and mouse_status.
I haven't done any performance benchmarks on this, though I think it
won't have any dramatic improvements on the system. It is good to get
rid of Giant here, because the third argument of tty_alloc() has only
been added to ease migration to MPSAFE TTY. It should not be used when
not needed.
While there, remove SC_MOUSE, which is a leftover from the MPSAFE TTY
import.
number in the irq register. While there are other issues with these
variants, avoiding writing to it helps interrupt generation on at
least one card, and doesn't hurt on the others. Flag ISA attachment
as needing INT_NO_REG written, and don't update the PC Card attachment
(which will have the effect of not touching it for PC Cards).
Document this in a comment, and tweak one or two formatting nits while
I'm here.
This is a sync to mesa/drm pre-gem, with a few fixes on top of that.
It also contains one local patch supplied by kib@ that I can't apply to
git.master shared code.
Approved by: flz
Obtained from: mesa/drm git.master
MFC after: 2 weeks
in a noticeable reduction in system time spent.
- If bus_dmamap_load_mbuf_sg(9) fails with EFBIG and we already have
defragmented the mbuf chain, don't bother to defragment and load it
a second time just yet as it's likely to fail again anyway.
MFC after: 3 days
night.
Free the children after each pci bus that is searched. Otherwise we
leak them. With free in the new place, we also have to free children
before going to done when we find the device we're looking for.
Also, if we can't get the children of a device, just ignore that bus.
When there's an error, we don't want to free the children, since it
will be stack garbage. While we did fail to dereference it by setting
devs to 0, we didn't fail to call free. We never failed to fail, it
was the easiest thing to do.
PHY only and not also in the case of an external PHY currently
doing full duplex, which accidentally got broken in r172334.
It's still not clear to me why we need to enable the buffer for
an internal PHY though.
- Count excess and late collisions as output errors. [1]
- Count receive errors as input errors. [1]
Obtained from: NetBSD [1]
MFC after: 3 days
only in low memory situations, so the error fork of these fixes is
lightly tested, but they should do the least-wrong thing...
Submitted by: Hans Petter Selasky
counters for Rx/Tx statistics. Various counters in ifnet is also
updated with these hardware counters.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
interrupt mask register again. This saves one register access per
each interrupt.
Also don't try to process frames when driver is not running.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
- Rename pciereg_cfgopen() to pcie_cfgregopen() and expose it to the
rest of the kernel. It now also accepts parameters via function
arguments rather than global variables.
- Add a notion of minimum and maximum bus numbers and reject requests for
an out of range bus.
- Add more range checks on slot/func/reg/bytes parameters to the cfg reg
read/write routines. Don't panic on any invalid parameters, just fail
the request (writes do nothing, reads return -1). This matches the
behavior of the other cfg mechanisms.
- Port the memory mapped configuration space access to amd64. On amd64
we simply use the direct map (via pmap_mapdev()) for the memory mapped
window.
- During acpi_attach() just after loading the ACPI tables, check for a
MCFG table. If it exists, call pciereg_cfgopen() on each subtable
(memory mapped window). For now we only support windows for domain 0
that start with bus 0. This removes the need for more chipset-specific
quirks in the MD code.
- Remove the chipset-specific quirks for the Intel 5000P/V/Z chipsets
since these machines should all have MCFG tables via ACPI.
- Updated pci_cfgregopen() to DTRT if ACPI had invoked pcie_cfgregopen()
earlier.
MFC after: 2 weeks
link state and detach request.
While I'm here make sure established link is IFM_10_T or
IFM_100_TX as bfe(4) just supports 10/100Mbps media.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
o Removed unneeded header files.
o bus_dma(9) fix:
- created parent tag with 1GB dma address limit with no
alignment restrictions.
- set 4096 alignment limit for Tx/Rx descriptor rings.
- separate Rx buffer tag from Tx buffer tag such that Tx tag
allows up-to 16 segments while Rx buffer tag only allows
single segment.
- it seems the controller has no alignment restrictions on Tx/Rx
buffers. Remove ETHER_ALIGN alignment restriction in Tx/Rx
buffers.
- created a spare Rx dma map which would be used to cope with
failure of loading a dma map.
- make sure to load full Tx/Rx descriptor size for Tx/Rx
descriptor dma maps, previously bfe(4) used to load single
descriptor size for each descriptor rings. I have no idea how
it could be run without problems.
- don't blindly cast bus_addr_t type to 32bits in bfe_dma_map().
- created bfe_dma_free() to free allocated dma memory/tags.
- make sure to invoke bus_dmamap_sync(9) before/after processing
descriptor rings/buffers. Because the hardware has severe dma
address space limitation, bounce-buffers would be always used
on systems with more than 1GB memory during
descriptors/buffers access.
- added Tx descriptor ring initialization function,
bfe_list_tx_init().
- moved producer/consumer index initialization to
bfe_list_tx_init() and bfe_list_rx_init() from
bfe_chip_reset().
- added bfe_discard_buf() which will update loaded descriptors
without unloading/reloading the dma map to speed up error
recovery.
- implemented Tx side bus_dmamap_load_mbuf_sg(9). The number of
segments allowed was chosen to be 16 which should be enough for
non-TSO capable hardwares. Setting SOF bit of Tx descriptor is
done in the last to avoid potential race.
- don't give up sending frames in bfe_start() until the hardware
lacks free descriptors.
- added XXX comment to second kick command and possible workaround.
- implemented Rx side bus_dmamap_load_mbuf_sg(9).
- removed bfe_dma_map_desc() as it's not needed anymore after
the conversion to bus_dmamap_load_mbuf_sg(9).
- added endianness support. With this change bfe(4) should work
on any architectures that can create bounce buffers within 1GB
address range.
- add missing bus_dmamap_sync() in bfe_tx_eof()/bfe_rx_eof().
o Use PCI_BAR instead of hardcoded value to set BARs.
Simplified register access with bus_write_4(9)/bus_read_4(9) and
removed bfe_btag, bfe_bhandle, bfe_vhandle in softc as it's not
used anymore.
o Reorder device detach logic such that bfe_detach() is also used
for handling driver attach failure case.
o Remove unnecessary KASSERT in bfe_detach().
o Remove bfe_rx_cnt, bfe_up, bfe_vpd_prodname, bfe_vpd_readonly in
softc. It's not used at all.
o Remove BFE_RX_RING_SIZE/BFE_RX_RING_SIZE/BFE_LINK_DOWN.
Tested by: kib, Gleb Kurtsou gleb.kurtsou at gmail dot com
Ulrich Spoerlein uspoerlein at gmail dot com
memory area's base and limit are optional. The low 4-bits of the "low"
prefetchable registers indicates whether or not a 32-bit or 64-bit
region is supported. The PCI-PCI driver had been assuming that all bridges
supported a 64-bit region (and thus the two upper 32-bit registers). Fix
the driver to only use those registers if the low 4-bits of the "low"
registers indicate that a 64-bit region is supported. The PCI-PCI bridge
in the XBox happens to be a bridge that only supports a 32-bit region.
Reported by: rink
MFC after: 1 week
