2018-01-29 13:11:30 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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2018-03-20 19:20:35 +00:00
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* Copyright 2015 Mellanox Technologies, Ltd
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2015-10-30 18:52:30 +00:00
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*/
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#ifndef RTE_PMD_MLX5_H_
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#define RTE_PMD_MLX5_H_
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#include <stddef.h>
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2019-07-05 13:10:30 +00:00
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#include <stdbool.h>
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2015-10-30 18:52:30 +00:00
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#include <stdint.h>
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#include <limits.h>
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#include <net/if.h>
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#include <netinet/in.h>
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2017-10-09 14:44:53 +00:00
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#include <sys/queue.h>
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2015-10-30 18:52:30 +00:00
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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2016-09-19 14:36:54 +00:00
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#pragma GCC diagnostic ignored "-Wpedantic"
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2015-10-30 18:52:30 +00:00
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#endif
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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2016-09-19 14:36:54 +00:00
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#pragma GCC diagnostic error "-Wpedantic"
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2015-10-30 18:52:30 +00:00
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#endif
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2017-07-07 00:04:20 +00:00
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#include <rte_pci.h>
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2015-10-30 18:52:30 +00:00
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#include <rte_ether.h>
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2018-01-22 00:16:22 +00:00
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#include <rte_ethdev_driver.h>
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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#include <rte_rwlock.h>
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2015-10-30 18:57:23 +00:00
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#include <rte_interrupts.h>
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2016-03-17 15:38:55 +00:00
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#include <rte_errno.h>
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2016-12-29 15:15:17 +00:00
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#include <rte_flow.h>
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2015-10-30 18:52:30 +00:00
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2020-01-29 12:38:27 +00:00
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#include <mlx5_glue.h>
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#include <mlx5_devx_cmds.h>
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#include <mlx5_prm.h>
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2020-01-29 12:38:49 +00:00
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#include <mlx5_nl.h>
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2020-04-13 21:17:47 +00:00
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#include <mlx5_common_mp.h>
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2020-04-13 21:17:48 +00:00
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#include <mlx5_common_mr.h>
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2020-01-29 12:38:27 +00:00
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#include "mlx5_defs.h"
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2015-10-30 18:52:30 +00:00
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#include "mlx5_utils.h"
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#include "mlx5_autoconf.h"
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2020-04-16 02:42:02 +00:00
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enum mlx5_ipool_index {
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2020-04-16 02:42:08 +00:00
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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2020-04-16 02:42:02 +00:00
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MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
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2020-04-16 02:42:03 +00:00
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MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
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2020-04-16 02:42:04 +00:00
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MLX5_IPOOL_TAG, /* Pool for tag resource. */
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2020-04-16 02:42:05 +00:00
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MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
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2020-04-16 02:42:06 +00:00
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MLX5_IPOOL_JUMP, /* Pool for jump resource. */
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2020-04-16 02:42:08 +00:00
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#endif
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2020-04-16 08:34:26 +00:00
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MLX5_IPOOL_MTR, /* Pool for meter resource. */
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2020-04-16 08:34:27 +00:00
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MLX5_IPOOL_MCP, /* Pool for metadata resource. */
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2020-04-16 02:42:07 +00:00
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MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
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2020-04-16 02:42:08 +00:00
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MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
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2020-04-16 08:34:30 +00:00
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MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
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2020-04-16 02:42:02 +00:00
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MLX5_IPOOL_MAX,
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};
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2019-04-01 21:12:54 +00:00
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/** Key string for IPC. */
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#define MLX5_MP_NAME "net_mlx5_mp"
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2018-07-10 16:04:52 +00:00
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2019-04-27 04:32:57 +00:00
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LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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2019-04-01 21:12:55 +00:00
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/* Shared data between primary and secondary processes. */
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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struct mlx5_shared_data {
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2019-04-01 21:12:55 +00:00
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rte_spinlock_t lock;
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/* Global spinlock for primary and secondary processes. */
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int init_done; /* Whether primary has done initialization. */
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unsigned int secondary_cnt; /* Number of secondary processes init'd. */
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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struct mlx5_dev_list mem_event_cb_list;
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rte_rwlock_t mem_event_rwlock;
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};
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2019-04-01 21:12:55 +00:00
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/* Per-process data structure, not visible to other processes. */
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struct mlx5_local_data {
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int init_done; /* Whether a secondary has done initialization. */
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};
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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extern struct mlx5_shared_data *mlx5_shared_data;
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2018-09-17 09:46:34 +00:00
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struct mlx5_counter_ctrl {
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/* Name of the counter. */
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char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
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/* Name of the counter on the device table. */
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char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
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uint32_t ib:1; /**< Nonzero for IB counters. */
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};
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2017-01-17 14:37:08 +00:00
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struct mlx5_xstats_ctrl {
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/* Number of device stats. */
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uint16_t stats_n;
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2018-09-17 09:46:34 +00:00
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/* Number of device stats identified by PMD. */
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uint16_t mlx5_stats_n;
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2017-01-17 14:37:08 +00:00
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/* Index in the device counters table. */
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uint16_t dev_table_idx[MLX5_MAX_XSTATS];
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uint64_t base[MLX5_MAX_XSTATS];
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2020-03-30 03:02:10 +00:00
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uint64_t xstats[MLX5_MAX_XSTATS];
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uint64_t hw_stats[MLX5_MAX_XSTATS];
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2018-09-17 09:46:34 +00:00
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struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
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2017-01-17 14:37:08 +00:00
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};
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2018-11-23 08:03:37 +00:00
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struct mlx5_stats_ctrl {
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/* Base for imissed counter. */
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uint64_t imissed_base;
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2020-03-30 03:02:10 +00:00
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uint64_t imissed;
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2018-11-23 08:03:37 +00:00
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};
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2018-01-10 09:16:58 +00:00
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/* Default PMD specific parameter value. */
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#define MLX5_ARG_UNSET (-1)
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2019-07-22 14:51:59 +00:00
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#define MLX5_LRO_SUPPORTED(dev) \
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(((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
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2019-12-18 07:51:39 +00:00
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/* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
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#define MLX5_LRO_SEG_CHUNK_SIZE 256u
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2019-11-11 17:47:34 +00:00
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/* Maximal size of aggregated LRO packet. */
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2019-12-18 07:51:39 +00:00
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#define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
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2019-11-11 17:47:34 +00:00
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2019-07-22 14:51:59 +00:00
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/* LRO configurations structure. */
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struct mlx5_lro_config {
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uint32_t supported:1; /* Whether LRO is supported. */
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uint32_t timeout; /* User configuration. */
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};
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|
2018-01-10 09:16:58 +00:00
|
|
|
/*
|
|
|
|
|
* Device configuration structure.
|
|
|
|
|
*
|
|
|
|
|
* Merged configuration from:
|
|
|
|
|
*
|
|
|
|
|
* - Device capabilities,
|
|
|
|
|
* - User device parameters disabled features.
|
|
|
|
|
*/
|
|
|
|
|
struct mlx5_dev_config {
|
|
|
|
|
unsigned int hw_csum:1; /* Checksum offload is supported. */
|
|
|
|
|
unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
|
2019-07-21 14:24:57 +00:00
|
|
|
unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
|
|
|
|
|
unsigned int hw_padding:1; /* End alignment padding is supported. */
|
2018-04-05 15:07:19 +00:00
|
|
|
unsigned int vf:1; /* This is a VF. */
|
2018-02-25 07:28:37 +00:00
|
|
|
unsigned int tunnel_en:1;
|
|
|
|
|
/* Whether tunnel stateless offloads are supported. */
|
2018-05-15 11:07:14 +00:00
|
|
|
unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int cqe_comp:1; /* CQE compression is enabled. */
|
2018-10-25 06:24:00 +00:00
|
|
|
unsigned int cqe_pad:1; /* CQE padding is enabled. */
|
2018-01-10 09:17:00 +00:00
|
|
|
unsigned int tso:1; /* Whether TSO is supported. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int rx_vec_en:1; /* Rx vector is enabled. */
|
2019-04-01 21:17:54 +00:00
|
|
|
unsigned int mr_ext_memseg_en:1;
|
|
|
|
|
/* Whether memseg should be extended for MR creation. */
|
2018-04-23 12:33:02 +00:00
|
|
|
unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
|
2018-04-05 15:07:21 +00:00
|
|
|
unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
|
2019-04-18 13:16:01 +00:00
|
|
|
unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
|
2018-09-24 23:17:54 +00:00
|
|
|
unsigned int dv_flow_en:1; /* Enable DV flow. */
|
net/mlx5: add devarg for extensive metadata support
The PMD parameter dv_xmeta_en is added to control extensive
metadata support. A nonzero value enables extensive flow
metadata support if device is capable and driver supports it.
This can enable extensive support of MARK and META item of
rte_flow. The newly introduced SET_TAG and SET_META actions
do not depend on dv_xmeta_en parameter, because there is
no compatibility issue for new entities. The dv_xmeta_en is
disabled by default.
There are some possible configurations, depending on parameter
value:
- 0, this is default value, defines the legacy mode, the MARK
and META related actions and items operate only within NIC Tx
and NIC Rx steering domains, no MARK and META information
crosses the domain boundaries. The MARK item is 24 bits wide,
the META item is 32 bits wide.
- 1, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The ``MARK`` item is 24 bits wide, the
META item width depends on kernel and firmware configurations
and might be 0, 16 or 32 bits. Within NIC Tx domain META data
width is 32 bits for compatibility, the actual width of data
transferred to the FDB domain depends on kernel configuration
and may be vary. The actual supported width can be retrieved
in runtime by series of rte_flow_validate() trials.
- 2, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The META item is 32 bits wide, the MARK
item width depends on kernel and firmware configurations and
might be 0, 16 or 24 bits. The actual supported width can be
retrieved in runtime by series of rte_flow_validate() trials.
If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is
ignored and the device is configured to operate in legacy mode (0).
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-07 17:09:54 +00:00
|
|
|
unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
|
2018-04-08 12:41:20 +00:00
|
|
|
unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
|
2019-01-03 15:06:37 +00:00
|
|
|
unsigned int devx:1; /* Whether devx interface is available or not. */
|
2019-07-22 14:52:02 +00:00
|
|
|
unsigned int dest_tir:1; /* Whether advanced DR API is available. */
|
2018-05-09 11:13:50 +00:00
|
|
|
struct {
|
|
|
|
|
unsigned int enabled:1; /* Whether MPRQ is enabled. */
|
|
|
|
|
unsigned int stride_num_n; /* Number of strides. */
|
2020-04-09 22:23:51 +00:00
|
|
|
unsigned int stride_size_n; /* Size of a stride. */
|
2018-05-09 11:13:50 +00:00
|
|
|
unsigned int min_stride_size_n; /* Min size of a stride. */
|
|
|
|
|
unsigned int max_stride_size_n; /* Max size of a stride. */
|
|
|
|
|
unsigned int max_memcpy_len;
|
|
|
|
|
/* Maximum packet size to memcpy Rx packets. */
|
|
|
|
|
unsigned int min_rxqs_num;
|
|
|
|
|
/* Rx queue count threshold to enable MPRQ. */
|
|
|
|
|
} mprq; /* Configurations for Multi-Packet RQ. */
|
2018-08-13 06:47:57 +00:00
|
|
|
int mps; /* Multi-packet send supported mode. */
|
2019-11-08 15:07:50 +00:00
|
|
|
int dbnc; /* Skip doorbell register write barrier. */
|
2018-07-12 09:30:49 +00:00
|
|
|
unsigned int flow_prio; /* Number of flow priorities. */
|
2019-11-07 17:09:53 +00:00
|
|
|
enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
|
|
|
|
|
/* Availibility of mreg_c's. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
|
|
|
|
|
unsigned int ind_table_max_size; /* Maximum indirection table size. */
|
2019-05-30 10:20:32 +00:00
|
|
|
unsigned int max_dump_files_num; /* Maximum dump files per queue. */
|
2020-03-24 12:59:01 +00:00
|
|
|
unsigned int log_hp_size; /* Single hairpin queue data size in total. */
|
2018-01-10 09:16:58 +00:00
|
|
|
int txqs_inline; /* Queue number threshold for inlining. */
|
2019-07-21 14:24:54 +00:00
|
|
|
int txq_inline_min; /* Minimal amount of data bytes to inline. */
|
|
|
|
|
int txq_inline_max; /* Max packet size for inlining with SEND. */
|
|
|
|
|
int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
|
2019-04-18 13:16:01 +00:00
|
|
|
struct mlx5_hca_attr hca_attr; /* HCA attributes. */
|
2019-07-22 14:51:59 +00:00
|
|
|
struct mlx5_lro_config lro; /* LRO configuration. */
|
2018-01-10 09:16:58 +00:00
|
|
|
};
|
|
|
|
|
|
2019-10-30 23:53:15 +00:00
|
|
|
|
2018-01-22 12:33:38 +00:00
|
|
|
/**
|
2019-07-18 19:40:52 +00:00
|
|
|
* Type of object being allocated.
|
2018-01-22 12:33:38 +00:00
|
|
|
*/
|
|
|
|
|
enum mlx5_verbs_alloc_type {
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_NONE,
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
|
|
|
|
|
};
|
|
|
|
|
|
2019-07-30 09:20:24 +00:00
|
|
|
/* Structure for VF VLAN workaround. */
|
|
|
|
|
struct mlx5_vf_vlan {
|
|
|
|
|
uint32_t tag:12;
|
|
|
|
|
uint32_t created:1;
|
|
|
|
|
};
|
|
|
|
|
|
2018-01-22 12:33:38 +00:00
|
|
|
/**
|
|
|
|
|
* Verbs allocator needs a context to know in the callback which kind of
|
|
|
|
|
* resources it is allocating.
|
|
|
|
|
*/
|
|
|
|
|
struct mlx5_verbs_alloc_ctx {
|
|
|
|
|
enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
|
|
|
|
|
const void *obj; /* Pointer to the DPDK object. */
|
|
|
|
|
};
|
|
|
|
|
|
2018-07-12 09:30:48 +00:00
|
|
|
/* Flow drop context necessary due to Verbs API. */
|
|
|
|
|
struct mlx5_drop {
|
|
|
|
|
struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
|
2019-07-22 14:52:11 +00:00
|
|
|
struct mlx5_rxq_obj *rxq; /* Rx queue object. */
|
2018-07-12 09:30:48 +00:00
|
|
|
};
|
|
|
|
|
|
2019-07-16 14:34:53 +00:00
|
|
|
#define MLX5_COUNTERS_PER_POOL 512
|
2019-07-16 14:34:55 +00:00
|
|
|
#define MLX5_MAX_PENDING_QUERIES 4
|
2020-04-07 03:59:42 +00:00
|
|
|
#define MLX5_CNT_CONTAINER_RESIZE 64
|
|
|
|
|
/*
|
|
|
|
|
* The pool index and offset of counter in the pool array makes up the
|
|
|
|
|
* counter index. In case the counter is from pool 0 and offset 0, it
|
|
|
|
|
* should plus 1 to avoid index 0, since 0 means invalid counter index
|
|
|
|
|
* currently.
|
|
|
|
|
*/
|
|
|
|
|
#define MLX5_MAKE_CNT_IDX(pi, offset) \
|
|
|
|
|
((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
|
2020-04-07 03:59:46 +00:00
|
|
|
#define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \
|
|
|
|
|
((pool) + 1))[((cnt) - (pool)->counters_raw)])
|
|
|
|
|
#define MLX5_GET_POOL_CNT_EXT(pool, offset) \
|
|
|
|
|
(&((struct mlx5_flow_counter_ext *) \
|
|
|
|
|
((pool) + 1))[offset])
|
2019-07-16 14:34:53 +00:00
|
|
|
|
|
|
|
|
struct mlx5_flow_counter_pool;
|
|
|
|
|
|
|
|
|
|
struct flow_counter_stats {
|
|
|
|
|
uint64_t hits;
|
|
|
|
|
uint64_t bytes;
|
|
|
|
|
};
|
|
|
|
|
|
2020-04-07 03:59:46 +00:00
|
|
|
/* Generic counters information. */
|
2019-07-16 14:34:53 +00:00
|
|
|
struct mlx5_flow_counter {
|
|
|
|
|
TAILQ_ENTRY(mlx5_flow_counter) next;
|
|
|
|
|
/**< Pointer to the next flow counter structure. */
|
2020-04-07 03:59:46 +00:00
|
|
|
union {
|
|
|
|
|
uint64_t hits; /**< Reset value of hits packets. */
|
|
|
|
|
int64_t query_gen; /**< Generation of the last release. */
|
|
|
|
|
};
|
|
|
|
|
uint64_t bytes; /**< Reset value of bytes. */
|
|
|
|
|
void *action; /**< Pointer to the dv action. */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Extend counters information for none batch counters. */
|
|
|
|
|
struct mlx5_flow_counter_ext {
|
2019-07-16 14:34:53 +00:00
|
|
|
uint32_t shared:1; /**< Share counter ID with other flow rules. */
|
|
|
|
|
uint32_t batch: 1;
|
|
|
|
|
/**< Whether the counter was allocated by batch command. */
|
|
|
|
|
uint32_t ref_cnt:30; /**< Reference counter. */
|
2020-04-07 03:59:46 +00:00
|
|
|
uint32_t id; /**< User counter ID. */
|
2019-07-16 14:34:53 +00:00
|
|
|
union { /**< Holds the counters for the rule. */
|
|
|
|
|
#if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
|
|
|
|
|
struct ibv_counter_set *cs;
|
|
|
|
|
#elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
|
|
|
|
|
struct ibv_counters *cs;
|
|
|
|
|
#endif
|
|
|
|
|
struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2020-04-07 03:59:46 +00:00
|
|
|
|
2019-07-16 14:34:53 +00:00
|
|
|
TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
|
|
|
|
|
|
2020-04-07 03:59:46 +00:00
|
|
|
/* Generic counter pool structure - query is in pool resolution. */
|
2019-07-16 14:34:53 +00:00
|
|
|
struct mlx5_flow_counter_pool {
|
|
|
|
|
TAILQ_ENTRY(mlx5_flow_counter_pool) next;
|
|
|
|
|
struct mlx5_counters counters; /* Free counter list. */
|
2019-07-16 14:34:55 +00:00
|
|
|
union {
|
|
|
|
|
struct mlx5_devx_obj *min_dcs;
|
|
|
|
|
rte_atomic64_t a64_dcs;
|
|
|
|
|
};
|
|
|
|
|
/* The devx object of the minimum counter ID. */
|
2020-04-07 03:59:41 +00:00
|
|
|
rte_atomic64_t start_query_gen; /* Query start round. */
|
|
|
|
|
rte_atomic64_t end_query_gen; /* Query end round. */
|
2020-04-07 03:59:44 +00:00
|
|
|
uint32_t index; /* Pool index in container. */
|
2019-07-16 14:34:55 +00:00
|
|
|
rte_spinlock_t sl; /* The pool lock. */
|
|
|
|
|
struct mlx5_counter_stats_raw *raw;
|
|
|
|
|
struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
|
2020-04-07 03:59:46 +00:00
|
|
|
struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL];
|
|
|
|
|
/* The pool counters memory. */
|
2019-07-16 14:34:53 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct mlx5_counter_stats_raw;
|
|
|
|
|
|
|
|
|
|
/* Memory management structure for group of counter statistics raws. */
|
|
|
|
|
struct mlx5_counter_stats_mem_mng {
|
|
|
|
|
LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
|
|
|
|
|
struct mlx5_counter_stats_raw *raws;
|
|
|
|
|
struct mlx5_devx_obj *dm;
|
|
|
|
|
struct mlx5dv_devx_umem *umem;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Raw memory structure for the counter statistics values of a pool. */
|
|
|
|
|
struct mlx5_counter_stats_raw {
|
|
|
|
|
LIST_ENTRY(mlx5_counter_stats_raw) next;
|
|
|
|
|
int min_dcs_id;
|
|
|
|
|
struct mlx5_counter_stats_mem_mng *mem_mng;
|
|
|
|
|
volatile struct flow_counter_stats *data;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
|
|
|
|
|
|
|
|
|
|
/* Container structure for counter pools. */
|
|
|
|
|
struct mlx5_pools_container {
|
2019-07-16 14:34:55 +00:00
|
|
|
rte_atomic16_t n_valid; /* Number of valid pools. */
|
2019-07-16 14:34:53 +00:00
|
|
|
uint16_t n; /* Number of pools. */
|
|
|
|
|
struct mlx5_counter_pools pool_list; /* Counter pool list. */
|
|
|
|
|
struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
|
|
|
|
|
struct mlx5_counter_stats_mem_mng *init_mem_mng;
|
|
|
|
|
/* Hold the memory management for the next allocated pools raws. */
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Counter global management structure. */
|
|
|
|
|
struct mlx5_flow_counter_mng {
|
2019-07-16 14:34:55 +00:00
|
|
|
uint8_t mhi[2]; /* master \ host container index. */
|
|
|
|
|
struct mlx5_pools_container ccont[2 * 2];
|
|
|
|
|
/* 2 containers for single and for batch for double-buffer. */
|
2019-07-16 14:34:53 +00:00
|
|
|
struct mlx5_counters flow_counters; /* Legacy flow counter list. */
|
2019-07-16 14:34:55 +00:00
|
|
|
uint8_t pending_queries;
|
|
|
|
|
uint8_t batch;
|
|
|
|
|
uint16_t pool_index;
|
|
|
|
|
uint8_t query_thread_on;
|
2019-07-16 14:34:53 +00:00
|
|
|
LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
|
2019-07-16 14:34:55 +00:00
|
|
|
LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
|
2019-07-16 14:34:53 +00:00
|
|
|
};
|
|
|
|
|
|
2019-03-27 13:15:39 +00:00
|
|
|
/* Per port data of shared IB device. */
|
|
|
|
|
struct mlx5_ibv_shared_port {
|
|
|
|
|
uint32_t ih_port_id;
|
2019-10-22 07:33:35 +00:00
|
|
|
uint32_t devx_ih_port_id;
|
2019-03-27 13:15:39 +00:00
|
|
|
/*
|
|
|
|
|
* Interrupt handler port_id. Used by shared interrupt
|
|
|
|
|
* handler to find the corresponding rte_eth device
|
|
|
|
|
* by IB port index. If value is equal or greater
|
|
|
|
|
* RTE_MAX_ETHPORTS it means there is no subhandler
|
|
|
|
|
* installed for specified IB port index.
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
|
2019-11-08 15:23:08 +00:00
|
|
|
/* Table key of the hash organization. */
|
|
|
|
|
union mlx5_flow_tbl_key {
|
|
|
|
|
struct {
|
|
|
|
|
/* Table ID should be at the lowest address. */
|
|
|
|
|
uint32_t table_id; /**< ID of the table. */
|
|
|
|
|
uint16_t reserved; /**< must be zero for comparison. */
|
|
|
|
|
uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
|
|
|
|
|
uint8_t direction; /**< 1 - egress, 0 - ingress. */
|
|
|
|
|
};
|
|
|
|
|
uint64_t v64; /**< full 64bits value of key */
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-04 13:04:25 +00:00
|
|
|
/* Table structure. */
|
|
|
|
|
struct mlx5_flow_tbl_resource {
|
|
|
|
|
void *obj; /**< Pointer to DR table object. */
|
|
|
|
|
rte_atomic32_t refcnt; /**< Reference counter. */
|
|
|
|
|
};
|
|
|
|
|
|
2019-09-11 11:03:36 +00:00
|
|
|
#define MLX5_MAX_TABLES UINT16_MAX
|
2019-11-08 03:49:12 +00:00
|
|
|
#define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
|
|
|
|
|
#define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
|
2019-10-30 23:53:22 +00:00
|
|
|
#define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
|
2019-11-07 17:09:53 +00:00
|
|
|
/* Reserve the last two tables for metadata register copy. */
|
|
|
|
|
#define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
|
2019-11-07 17:10:04 +00:00
|
|
|
#define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
|
|
|
|
|
/* Tables for metering splits should be added here. */
|
|
|
|
|
#define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
|
2019-09-11 11:03:36 +00:00
|
|
|
#define MLX5_MAX_TABLES_FDB UINT16_MAX
|
2019-04-04 13:04:25 +00:00
|
|
|
|
2019-07-22 14:52:10 +00:00
|
|
|
#define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
|
|
|
|
|
#define MLX5_DBR_SIZE 8
|
|
|
|
|
#define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
|
|
|
|
|
#define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
|
|
|
|
|
|
|
|
|
|
struct mlx5_devx_dbr_page {
|
|
|
|
|
/* Door-bell records, must be first member in structure. */
|
|
|
|
|
uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
|
|
|
|
|
LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
|
|
|
|
|
struct mlx5dv_devx_umem *umem;
|
|
|
|
|
uint32_t dbr_count; /* Number of door-bell records in use. */
|
|
|
|
|
/* 1 bit marks matching door-bell is in use. */
|
|
|
|
|
uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
|
|
|
|
|
};
|
|
|
|
|
|
2019-10-30 23:53:23 +00:00
|
|
|
/* ID generation structure. */
|
|
|
|
|
struct mlx5_flow_id_pool {
|
|
|
|
|
uint32_t *free_arr; /**< Pointer to the a array of free values. */
|
|
|
|
|
uint32_t base_index;
|
|
|
|
|
/**< The next index that can be used without any free elements. */
|
|
|
|
|
uint32_t *curr; /**< Pointer to the index to pop. */
|
|
|
|
|
uint32_t *last; /**< Pointer to the last element in the empty arrray. */
|
2020-01-23 06:01:01 +00:00
|
|
|
uint32_t max_id; /**< Maximum id can be allocated from the pool. */
|
2019-10-30 23:53:23 +00:00
|
|
|
};
|
|
|
|
|
|
2019-03-27 13:15:39 +00:00
|
|
|
/*
|
|
|
|
|
* Shared Infiniband device context for Master/Representors
|
|
|
|
|
* which belong to same IB device with multiple IB ports.
|
|
|
|
|
**/
|
|
|
|
|
struct mlx5_ibv_shared {
|
|
|
|
|
LIST_ENTRY(mlx5_ibv_shared) next;
|
|
|
|
|
uint32_t refcnt;
|
|
|
|
|
uint32_t devx:1; /* Opened with DV. */
|
|
|
|
|
uint32_t max_port; /* Maximal IB device port index. */
|
|
|
|
|
struct ibv_context *ctx; /* Verbs/DV context. */
|
|
|
|
|
struct ibv_pd *pd; /* Protection Domain. */
|
2019-07-22 14:52:15 +00:00
|
|
|
uint32_t pdn; /* Protection Domain number. */
|
2019-07-22 14:52:05 +00:00
|
|
|
uint32_t tdn; /* Transport Domain number. */
|
2019-03-27 13:15:39 +00:00
|
|
|
char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
|
|
|
|
|
char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
|
|
|
|
|
struct ibv_device_attr_ex device_attr; /* Device properties. */
|
2019-04-27 04:32:57 +00:00
|
|
|
LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
|
|
|
|
|
/**< Called by memory event callback. */
|
2020-04-13 21:17:48 +00:00
|
|
|
struct mlx5_mr_share_cache share_cache;
|
2019-04-04 13:04:24 +00:00
|
|
|
/* Shared DV/DR flow data section. */
|
2019-04-04 13:04:25 +00:00
|
|
|
pthread_mutex_t dv_mutex; /* DV context mutex. */
|
2019-11-07 17:09:55 +00:00
|
|
|
uint32_t dv_meta_mask; /* flow META metadata supported mask. */
|
|
|
|
|
uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
|
|
|
|
|
uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
|
2019-04-04 13:04:24 +00:00
|
|
|
uint32_t dv_refcnt; /* DV/DR data reference counter. */
|
2019-05-01 20:40:45 +00:00
|
|
|
void *fdb_domain; /* FDB Direct Rules name space handle. */
|
|
|
|
|
void *rx_domain; /* RX Direct Rules name space handle. */
|
|
|
|
|
void *tx_domain; /* TX Direct Rules name space handle. */
|
2019-11-08 15:23:08 +00:00
|
|
|
struct mlx5_hlist *flow_tbls;
|
|
|
|
|
/* Direct Rules tables for FDB, NIC TX+RX */
|
2019-04-18 13:16:07 +00:00
|
|
|
void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
|
2019-09-09 15:56:45 +00:00
|
|
|
void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
|
2020-04-16 02:42:02 +00:00
|
|
|
uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
|
2019-04-04 13:04:25 +00:00
|
|
|
LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
|
2019-11-08 05:26:57 +00:00
|
|
|
struct mlx5_hlist *tag_table;
|
2020-04-16 02:42:05 +00:00
|
|
|
uint32_t port_id_action_list; /* List of port ID actions. */
|
2020-04-16 02:42:03 +00:00
|
|
|
uint32_t push_vlan_action_list; /* List of push VLAN actions. */
|
2019-07-16 14:34:53 +00:00
|
|
|
struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
|
2020-04-16 02:42:02 +00:00
|
|
|
struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
|
|
|
|
|
/* Memory Pool for mlx5 flow resources. */
|
2019-04-04 13:04:24 +00:00
|
|
|
/* Shared interrupt handler section. */
|
2019-03-27 13:15:45 +00:00
|
|
|
pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
|
|
|
|
|
uint32_t intr_cnt; /* Interrupt handler reference counter. */
|
2019-03-27 13:15:39 +00:00
|
|
|
struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
|
2019-10-22 07:33:35 +00:00
|
|
|
uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
|
2019-07-16 14:34:55 +00:00
|
|
|
struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
|
|
|
|
|
struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
|
2019-10-30 23:53:15 +00:00
|
|
|
struct mlx5_devx_obj *tis; /* TIS object. */
|
|
|
|
|
struct mlx5_devx_obj *td; /* Transport domain. */
|
2019-10-30 23:53:23 +00:00
|
|
|
struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
|
2019-03-27 13:15:39 +00:00
|
|
|
struct mlx5_ibv_shared_port port[]; /* per device port data array. */
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-10 18:41:17 +00:00
|
|
|
/* Per-process private structure. */
|
|
|
|
|
struct mlx5_proc_priv {
|
|
|
|
|
size_t uar_table_sz;
|
|
|
|
|
/* Size of UAR register table. */
|
|
|
|
|
void *uar_table[];
|
|
|
|
|
/* Table of UAR registers for each process. */
|
|
|
|
|
};
|
|
|
|
|
|
2019-11-08 03:49:10 +00:00
|
|
|
/* MTR profile list. */
|
|
|
|
|
TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
|
2019-11-08 03:49:14 +00:00
|
|
|
/* MTR list. */
|
|
|
|
|
TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
|
2019-11-08 03:49:10 +00:00
|
|
|
|
2019-04-10 18:41:17 +00:00
|
|
|
#define MLX5_PROC_PRIV(port_id) \
|
|
|
|
|
((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
|
|
|
|
|
|
2019-02-21 09:29:14 +00:00
|
|
|
struct mlx5_priv {
|
2018-05-09 11:04:50 +00:00
|
|
|
struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
|
2019-03-27 13:15:39 +00:00
|
|
|
struct mlx5_ibv_shared *sh; /* Shared IB device context. */
|
|
|
|
|
uint32_t ibv_port; /* IB device port number. */
|
2019-09-25 07:53:24 +00:00
|
|
|
struct rte_pci_device *pci_dev; /* Backend PCI device. */
|
2019-05-21 16:13:03 +00:00
|
|
|
struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
|
2018-04-05 15:07:19 +00:00
|
|
|
BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
|
|
|
|
|
/* Bit-field of MAC addresses owned by the PMD. */
|
2015-10-30 18:52:40 +00:00
|
|
|
uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
|
|
|
|
|
unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
|
2015-10-30 18:52:30 +00:00
|
|
|
/* Device properties. */
|
|
|
|
|
uint16_t mtu; /* Configured MTU. */
|
2017-05-24 13:44:08 +00:00
|
|
|
unsigned int isolated:1; /* Whether isolated mode is enabled. */
|
2018-07-10 16:04:54 +00:00
|
|
|
unsigned int representor:1; /* Device is a port representor. */
|
2019-03-27 13:15:35 +00:00
|
|
|
unsigned int master:1; /* Device is a E-Switch master. */
|
2019-04-04 13:04:24 +00:00
|
|
|
unsigned int dr_shared:1; /* DV/DR data is shared. */
|
2019-07-16 14:34:56 +00:00
|
|
|
unsigned int counter_fallback:1; /* Use counter fallback management. */
|
2019-11-08 03:49:08 +00:00
|
|
|
unsigned int mtr_en:1; /* Whether support meter. */
|
2020-01-23 06:01:02 +00:00
|
|
|
unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
|
2018-07-10 16:04:54 +00:00
|
|
|
uint16_t domain_id; /* Switch domain identifier. */
|
2019-03-27 13:15:35 +00:00
|
|
|
uint16_t vport_id; /* Associated VF vport index (if any). */
|
2019-09-25 07:53:30 +00:00
|
|
|
uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
|
|
|
|
|
uint32_t vport_meta_mask; /* Used for vport index field match mask. */
|
2018-07-10 16:04:54 +00:00
|
|
|
int32_t representor_id; /* Port representor identifier. */
|
2019-09-25 07:53:34 +00:00
|
|
|
int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
|
2019-07-21 14:56:40 +00:00
|
|
|
unsigned int if_index; /* Associated kernel network device index. */
|
2015-10-30 18:52:31 +00:00
|
|
|
/* RX/TX queues. */
|
|
|
|
|
unsigned int rxqs_n; /* RX queues array size. */
|
|
|
|
|
unsigned int txqs_n; /* TX queues array size. */
|
2017-10-09 14:44:39 +00:00
|
|
|
struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
|
2017-10-09 14:44:40 +00:00
|
|
|
struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
|
2018-05-09 11:13:50 +00:00
|
|
|
struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
|
2017-10-09 14:44:56 +00:00
|
|
|
struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
|
2015-11-02 18:11:57 +00:00
|
|
|
unsigned int (*reta_idx)[]; /* RETA index table. */
|
|
|
|
|
unsigned int reta_idx_n; /* RETA index size. */
|
2018-07-12 09:30:48 +00:00
|
|
|
struct mlx5_drop drop_queue; /* Flow drop queues. */
|
2020-04-16 08:34:30 +00:00
|
|
|
uint32_t flows; /* RTE Flow rules. */
|
|
|
|
|
uint32_t ctrl_flows; /* Control flow rules. */
|
2020-03-24 15:33:59 +00:00
|
|
|
void *inter_flows; /* Intermediate resources for flow creation. */
|
2020-04-16 08:34:29 +00:00
|
|
|
void *rss_desc; /* Intermediate rss description resources. */
|
2020-03-24 15:33:59 +00:00
|
|
|
int flow_idx; /* Intermediate device flow index. */
|
2020-04-09 14:38:41 +00:00
|
|
|
int flow_nested_idx; /* Intermediate device flow index, nested. */
|
2017-10-09 14:44:49 +00:00
|
|
|
LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
|
2019-07-22 14:52:11 +00:00
|
|
|
LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
|
2020-04-16 02:42:07 +00:00
|
|
|
uint32_t hrxqs; /* Verbs Hash Rx queues. */
|
2017-10-09 14:44:48 +00:00
|
|
|
LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
|
2019-10-30 23:53:14 +00:00
|
|
|
LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
|
2019-07-22 14:52:12 +00:00
|
|
|
/* Indirection tables. */
|
|
|
|
|
LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
|
2019-04-04 09:54:08 +00:00
|
|
|
/* Pointer to next element. */
|
|
|
|
|
rte_atomic32_t refcnt; /**< Reference counter. */
|
|
|
|
|
struct ibv_flow_action *verbs_action;
|
|
|
|
|
/**< Verbs modify header action object. */
|
|
|
|
|
uint8_t ft_type; /**< Flow table type, Rx or Tx. */
|
2019-07-22 14:52:24 +00:00
|
|
|
uint8_t max_lro_msg_size;
|
2019-04-04 09:54:06 +00:00
|
|
|
/* Tags resources cache. */
|
2016-10-26 09:44:01 +00:00
|
|
|
uint32_t link_speed_capa; /* Link speed capabilities. */
|
2017-01-17 14:37:08 +00:00
|
|
|
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
|
2018-11-23 08:03:37 +00:00
|
|
|
struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
|
2018-01-10 09:16:58 +00:00
|
|
|
struct mlx5_dev_config config; /* Device configuration. */
|
2018-01-22 12:33:38 +00:00
|
|
|
struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
|
|
|
|
|
/* Context for Verbs allocator. */
|
2018-07-10 16:04:52 +00:00
|
|
|
int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
|
|
|
|
|
int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
|
2019-07-22 14:52:10 +00:00
|
|
|
LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
|
2020-01-29 12:38:47 +00:00
|
|
|
struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
|
net/mlx5: split Rx flows to provide metadata copy
Values set by MARK and SET_META actions should be carried over
to the VF representor in case of flow miss on Tx path. However,
as not all metadata registers are preserved across the different
domains (NIC Rx/Tx and E-Switch FDB), as a workaround, those
values should be carried by reg_c's which are preserved across
domains and copied to STE flow_tag (MARK) and reg_b (META) fields
in the last stage of flow steering, in order to scatter those
values to flow_tag and flow_table_metadata of CQE.
While reg_c[meta] can be copied to reg_b simply by modify-header
action (it is supported by hardware), it is not possible to copy
reg_c[mark] to the STE flow_tag as flow_tag is not a metadata
register and this is not supported by hardware. Instead, it should
be manually set by a flow per MARK ID. For this purpose, there
should be a dedicated flow table - RX_CP_TBL and all the Rx flow
should pass by the table to properly copy values.
As the last action of Rx flow steering must be a terminal action
such as QUEUE, RSS or DROP, if a user flow has Q/RSS action, the
flow must be split in order to pass by the RX_CP_TBL. And the
remained Q/RSS action will be performed by another dedicated
action table - RX_ACT_TBL.
For example, for an ingress flow:
pattern,
actions_having_QRSS
it must be split into two flows. The first one is,
pattern,
actions_except_QRSS / copy (reg_c[2] := flow_id) / jump to RX_CP_TBL
and the second one in RX_ACT_TBL.
(if reg_c[2] == flow_id),
action_QRSS
where flow_id is uniquely allocated and managed identifier.
This patch implements the Rx flow splitting and build the RX_ACT_TBL.
Also, per each egress flow on NIC Tx, a copy action (reg_c[]= reg_a)
should be added in order to transfer metadata from WQE.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-07 17:10:03 +00:00
|
|
|
struct mlx5_flow_id_pool *qrss_id_pool;
|
2019-11-07 17:10:04 +00:00
|
|
|
struct mlx5_hlist *mreg_cp_tbl;
|
|
|
|
|
/* Hash table of Rx metadata register copy table. */
|
2019-11-08 03:49:09 +00:00
|
|
|
uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
|
|
|
|
|
uint8_t mtr_color_reg; /* Meter color match REG_C. */
|
2019-11-08 03:49:10 +00:00
|
|
|
struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
|
2019-11-08 03:49:14 +00:00
|
|
|
struct mlx5_flow_meters flow_meters; /* MTR list. */
|
2018-07-12 12:01:31 +00:00
|
|
|
#ifndef RTE_ARCH_64
|
|
|
|
|
rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
|
|
|
|
|
rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
|
|
|
|
|
/* UAR same-page access control required in 32bit implementations. */
|
|
|
|
|
#endif
|
2019-10-30 23:53:19 +00:00
|
|
|
uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
|
2020-01-28 17:06:43 +00:00
|
|
|
uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
|
2020-04-13 21:17:47 +00:00
|
|
|
struct mlx5_mp_id mp_id; /* ID of a multi-process process */
|
2020-04-16 08:34:28 +00:00
|
|
|
LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
|
2015-10-30 18:52:30 +00:00
|
|
|
};
|
|
|
|
|
|
2018-05-09 11:04:50 +00:00
|
|
|
#define PORT_ID(priv) ((priv)->dev_data->port_id)
|
|
|
|
|
#define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
|
|
|
|
|
|
2016-03-17 15:38:57 +00:00
|
|
|
/* mlx5.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_getenv_int(const char *);
|
2019-04-10 18:41:17 +00:00
|
|
|
int mlx5_proc_priv_init(struct rte_eth_dev *dev);
|
2019-07-22 14:52:10 +00:00
|
|
|
int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
|
|
|
|
|
struct mlx5_devx_dbr_page **dbr_page);
|
|
|
|
|
int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
|
|
|
|
|
uint64_t offset);
|
2019-08-22 10:15:52 +00:00
|
|
|
int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_udp_tunnel *udp_tunnel);
|
2019-10-07 13:56:19 +00:00
|
|
|
uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
|
2019-09-25 07:53:33 +00:00
|
|
|
|
|
|
|
|
/* Macro to iterate over all valid ports for mlx5 driver. */
|
2019-10-07 13:56:19 +00:00
|
|
|
#define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
|
|
|
|
|
for (port_id = mlx5_eth_find_next(0, pci_dev); \
|
2019-09-25 07:53:33 +00:00
|
|
|
port_id < RTE_MAX_ETHPORTS; \
|
2019-10-07 13:56:19 +00:00
|
|
|
port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
|
2016-03-17 15:38:57 +00:00
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/* mlx5_ethdev.c */
|
|
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
|
2019-04-05 13:25:55 +00:00
|
|
|
int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
|
2018-07-25 11:24:33 +00:00
|
|
|
unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
|
2018-10-08 06:28:17 +00:00
|
|
|
int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
|
|
|
|
|
int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
|
|
|
|
|
unsigned int flags);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_configure(struct rte_eth_dev *dev);
|
2019-09-12 16:42:28 +00:00
|
|
|
int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
|
2019-05-02 12:11:34 +00:00
|
|
|
int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
|
2019-02-06 22:25:19 +00:00
|
|
|
int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
|
2016-03-14 20:50:50 +00:00
|
|
|
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
|
|
|
|
|
int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_fc_conf *fc_conf);
|
|
|
|
|
int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_fc_conf *fc_conf);
|
|
|
|
|
void mlx5_dev_link_status_handler(void *arg);
|
2018-03-05 12:21:04 +00:00
|
|
|
void mlx5_dev_interrupt_handler(void *arg);
|
2019-07-16 14:34:55 +00:00
|
|
|
void mlx5_dev_interrupt_handler_devx(void *arg);
|
2018-03-05 12:21:04 +00:00
|
|
|
void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
|
2019-10-22 07:33:35 +00:00
|
|
|
void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
|
2016-03-17 15:38:54 +00:00
|
|
|
int mlx5_set_link_down(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_set_link_up(struct rte_eth_dev *dev);
|
2018-01-20 21:12:21 +00:00
|
|
|
int mlx5_is_removed(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
|
|
|
|
|
eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
|
2019-11-07 17:09:53 +00:00
|
|
|
struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
|
2019-09-25 07:53:31 +00:00
|
|
|
struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
|
2018-07-24 08:36:45 +00:00
|
|
|
int mlx5_sysfs_switch_info(unsigned int ifindex,
|
|
|
|
|
struct mlx5_switch_info *info);
|
net/mlx5: support PF representor
On BlueField platform we have the new entity - PF representor.
This one represents the PCI PF attached to external host on the
side of ARM. The traffic sent by the external host to the NIC
via PF will be seem by ARM on this PF representor.
This patch refactors port recognizing capability on the base of
physical port name. We have two groups of name formats. Legacy
name formats are supported by kernels before ver 5.0 (being
more precise - before the patch [1]) or before Mellanox OFED 4.6,
and new naming formats added by the patch [1].
Legacy naming formats are supported:
- missing physical port name (no sysfs/netlink key) at all,
master is assumed
- decimal digits (for example "12"), representor is assumed,
the value is the index of attached VF
New naming formats are supported:
- "p" followed by decimal digits, for example "p2", master
is assumed
- "pf" followed by PF index concatenated with "vf" followed by
VF index, for example "pf0vf1", representor is assumed.
If index of VF is "-1" it is a special case of host PF
representor, this representor must be indexed in devargs
as 65535, for example representor=[0-3,65535] will
allow representors for VF0, VF1, VF2, VF3 and for host PF.
Note: do not specify representor=[0-65535], it causes devargs
processing error, because number of ports (rte_eth_dev) is
limited.
Applications should distinguish representors and master devices
exclusively by device flag RTE_ETH_DEV_REPRESENTOR and do not
rely on switch port_id (mlx5 PMD deduces ones from representor_id)
values returned by dev_infos_get() API.
[1] https://www.spinics.net/lists/netdev/msg547007.html
Linux-tree: c12ecc23 (Or Gerlitz 2018-04-25 17:32 +0300)
"net/mlx5e: Move to use common phys port names for vport representors"
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2019-04-16 14:10:28 +00:00
|
|
|
void mlx5_sysfs_check_switch_info(bool device_dir,
|
|
|
|
|
struct mlx5_switch_info *switch_info);
|
|
|
|
|
void mlx5_translate_port_name(const char *port_name_in,
|
2019-03-17 06:23:03 +00:00
|
|
|
struct mlx5_switch_info *port_info_out);
|
2019-05-27 04:58:32 +00:00
|
|
|
void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
|
|
|
|
|
rte_intr_callback_fn cb_fn, void *cb_arg);
|
2019-09-09 11:04:35 +00:00
|
|
|
int mlx5_get_module_info(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_dev_module_info *modinfo);
|
|
|
|
|
int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_dev_eeprom_info *info);
|
2019-10-30 23:53:16 +00:00
|
|
|
int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_hairpin_cap *cap);
|
2019-10-30 23:53:19 +00:00
|
|
|
int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
|
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/* mlx5_mac.c */
|
|
|
|
|
|
2019-05-21 16:13:05 +00:00
|
|
|
int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
|
2018-03-05 12:20:58 +00:00
|
|
|
void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
|
2019-05-21 16:13:03 +00:00
|
|
|
int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
|
2018-03-05 12:20:58 +00:00
|
|
|
uint32_t index, uint32_t vmdq);
|
2020-01-29 12:38:47 +00:00
|
|
|
struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
|
|
|
|
|
(struct rte_eth_dev *dev, uint32_t ifindex);
|
2019-05-21 16:13:03 +00:00
|
|
|
int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
|
2018-04-23 11:09:28 +00:00
|
|
|
int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
|
2019-05-21 16:13:03 +00:00
|
|
|
struct rte_ether_addr *mc_addr_set,
|
|
|
|
|
uint32_t nb_mc_addr);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
2015-10-30 18:55:11 +00:00
|
|
|
/* mlx5_rss.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_rss_hash_update(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_conf *rss_conf);
|
|
|
|
|
int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_conf *rss_conf);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
|
|
|
uint16_t reta_size);
|
|
|
|
|
int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
|
|
|
uint16_t reta_size);
|
2015-10-30 18:55:11 +00:00
|
|
|
|
2015-10-30 18:52:37 +00:00
|
|
|
/* mlx5_rxmode.c */
|
|
|
|
|
|
2019-09-14 11:37:24 +00:00
|
|
|
int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
|
2019-09-24 12:56:10 +00:00
|
|
|
int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
|
2015-10-30 18:52:37 +00:00
|
|
|
|
2015-10-30 18:52:36 +00:00
|
|
|
/* mlx5_stats.c */
|
|
|
|
|
|
2018-11-23 08:03:37 +00:00
|
|
|
void mlx5_stats_init(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
|
2019-09-06 14:34:54 +00:00
|
|
|
int mlx5_stats_reset(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
|
|
|
|
|
unsigned int n);
|
2019-09-06 14:34:54 +00:00
|
|
|
int mlx5_xstats_reset(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
|
2018-03-05 12:20:58 +00:00
|
|
|
struct rte_eth_xstat_name *xstats_names,
|
|
|
|
|
unsigned int n);
|
2015-10-30 18:52:36 +00:00
|
|
|
|
2015-10-30 18:52:40 +00:00
|
|
|
/* mlx5_vlan.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
|
|
|
|
|
void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
|
|
|
|
|
int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
|
2020-01-29 12:38:47 +00:00
|
|
|
void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
|
|
|
|
|
void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
|
|
|
|
|
struct mlx5_vf_vlan *vf_vlan);
|
|
|
|
|
void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
|
|
|
|
|
struct mlx5_vf_vlan *vf_vlan);
|
2015-10-30 18:52:40 +00:00
|
|
|
|
2015-10-30 18:52:33 +00:00
|
|
|
/* mlx5_trigger.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_start(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_stop(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_traffic_enable(struct rte_eth_dev *dev);
|
2018-03-05 12:21:05 +00:00
|
|
|
void mlx5_traffic_disable(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_traffic_restart(struct rte_eth_dev *dev);
|
2015-10-30 18:52:33 +00:00
|
|
|
|
2017-10-09 14:44:38 +00:00
|
|
|
/* mlx5_flow.c */
|
2016-03-03 14:26:43 +00:00
|
|
|
|
2019-11-07 17:09:53 +00:00
|
|
|
int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
|
|
|
|
|
bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
|
2018-07-12 09:30:49 +00:00
|
|
|
int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
|
2018-07-12 09:30:48 +00:00
|
|
|
void mlx5_flow_print(struct rte_flow *flow);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_flow_validate(struct rte_eth_dev *dev,
|
|
|
|
|
const struct rte_flow_attr *attr,
|
|
|
|
|
const struct rte_flow_item items[],
|
|
|
|
|
const struct rte_flow_action actions[],
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
|
|
|
|
|
const struct rte_flow_attr *attr,
|
|
|
|
|
const struct rte_flow_item items[],
|
|
|
|
|
const struct rte_flow_action actions[],
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
|
|
|
|
|
struct rte_flow_error *error);
|
2020-04-16 08:34:30 +00:00
|
|
|
void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
|
2018-04-26 17:29:19 +00:00
|
|
|
const struct rte_flow_action *action, void *data,
|
2018-03-05 12:20:58 +00:00
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
enum rte_filter_type filter_type,
|
|
|
|
|
enum rte_filter_op filter_op,
|
|
|
|
|
void *arg);
|
2020-04-16 08:34:30 +00:00
|
|
|
int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
|
|
|
|
|
void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
|
2020-03-24 15:33:57 +00:00
|
|
|
int mlx5_flow_start_default(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_flow_stop_default(struct rte_eth_dev *dev);
|
2020-03-24 15:33:59 +00:00
|
|
|
void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_flow_verify(struct rte_eth_dev *dev);
|
2019-10-30 23:53:22 +00:00
|
|
|
int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_flow_item_eth *eth_spec,
|
|
|
|
|
struct rte_flow_item_eth *eth_mask,
|
|
|
|
|
struct rte_flow_item_vlan *vlan_spec,
|
|
|
|
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struct rte_flow_item_vlan *vlan_mask);
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int mlx5_ctrl_flow(struct rte_eth_dev *dev,
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struct rte_flow_item_eth *eth_spec,
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struct rte_flow_item_eth *eth_mask);
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2019-09-11 11:03:36 +00:00
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struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
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2018-03-05 12:21:04 +00:00
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int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
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void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
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2019-07-16 14:34:55 +00:00
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void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
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uint64_t async_id, int status);
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void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
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void mlx5_flow_query_alarm(void *arg);
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2020-04-07 03:59:45 +00:00
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uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
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void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
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int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
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2019-11-08 03:49:18 +00:00
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bool clear, uint64_t *pkts, uint64_t *bytes);
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2020-01-17 11:56:00 +00:00
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int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
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struct rte_flow_error *error);
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2020-04-17 17:14:53 +00:00
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void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
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2016-12-29 15:15:17 +00:00
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2019-04-01 21:12:54 +00:00
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/* mlx5_mp.c */
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2020-04-13 21:17:47 +00:00
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int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
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int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
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2019-04-01 21:12:56 +00:00
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void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
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void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
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2017-10-06 15:45:49 +00:00
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2020-01-17 11:56:02 +00:00
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/* mlx5_socket.c */
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int mlx5_pmd_socket_init(void);
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2019-11-08 03:49:07 +00:00
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/* mlx5_flow_meter.c */
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int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
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2019-11-08 03:49:14 +00:00
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struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
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uint32_t meter_id);
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2019-11-08 03:49:21 +00:00
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struct mlx5_flow_meter *mlx5_flow_meter_attach
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(struct mlx5_priv *priv,
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uint32_t meter_id,
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const struct rte_flow_attr *attr,
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struct rte_flow_error *error);
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void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
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2019-11-08 03:49:07 +00:00
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2015-10-30 18:52:30 +00:00
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#endif /* RTE_PMD_MLX5_H_ */
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