2018-01-29 13:11:30 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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2018-03-20 19:20:35 +00:00
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* Copyright 2015 Mellanox Technologies, Ltd
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2015-10-30 18:52:30 +00:00
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*/
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#ifndef RTE_PMD_MLX5_H_
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#define RTE_PMD_MLX5_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <limits.h>
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#include <net/if.h>
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#include <netinet/in.h>
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2017-10-09 14:44:53 +00:00
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#include <sys/queue.h>
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2015-10-30 18:52:30 +00:00
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/* Verbs header. */
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/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
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#ifdef PEDANTIC
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2016-09-19 14:36:54 +00:00
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#pragma GCC diagnostic ignored "-Wpedantic"
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2015-10-30 18:52:30 +00:00
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#endif
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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2016-09-19 14:36:54 +00:00
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#pragma GCC diagnostic error "-Wpedantic"
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2015-10-30 18:52:30 +00:00
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#endif
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2017-07-07 00:04:20 +00:00
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#include <rte_pci.h>
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2015-10-30 18:52:30 +00:00
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#include <rte_ether.h>
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2018-01-22 00:16:22 +00:00
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#include <rte_ethdev_driver.h>
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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#include <rte_rwlock.h>
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2015-10-30 18:57:23 +00:00
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#include <rte_interrupts.h>
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2016-03-17 15:38:55 +00:00
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#include <rte_errno.h>
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2016-12-29 15:15:17 +00:00
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#include <rte_flow.h>
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2015-10-30 18:52:30 +00:00
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#include "mlx5_utils.h"
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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#include "mlx5_mr.h"
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2015-10-30 18:52:31 +00:00
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#include "mlx5_rxtx.h"
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2015-10-30 18:52:30 +00:00
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#include "mlx5_autoconf.h"
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#include "mlx5_defs.h"
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enum {
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PCI_VENDOR_ID_MELLANOX = 0x15b3,
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};
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enum {
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PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
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PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
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2017-01-06 00:49:31 +00:00
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PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
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PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
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2018-05-15 06:12:50 +00:00
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PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
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2018-09-02 13:55:59 +00:00
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PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
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2018-12-31 12:43:48 +00:00
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PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
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PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
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2015-10-30 18:52:30 +00:00
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};
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2019-04-01 21:12:54 +00:00
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/* Request types for IPC. */
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enum mlx5_mp_req_type {
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MLX5_MP_REQ_VERBS_CMD_FD = 1,
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2019-04-01 21:12:56 +00:00
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MLX5_MP_REQ_START_RXTX,
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MLX5_MP_REQ_STOP_RXTX,
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2019-04-01 21:12:54 +00:00
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};
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/* Pameters for IPC. */
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struct mlx5_mp_param {
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enum mlx5_mp_req_type type;
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int port_id;
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int result;
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};
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/** Request timeout for IPC. */
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#define MLX5_MP_REQ_TIMEOUT_SEC 5
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/** Key string for IPC. */
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#define MLX5_MP_NAME "net_mlx5_mp"
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2018-07-10 16:04:52 +00:00
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/** Switch information returned by mlx5_nl_switch_info(). */
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struct mlx5_switch_info {
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uint32_t master:1; /**< Master device. */
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uint32_t representor:1; /**< Representor device. */
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2019-03-17 06:23:03 +00:00
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uint32_t port_name_new:1; /**< Rep. port name is in new format. */
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2018-07-10 16:04:52 +00:00
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int32_t port_name; /**< Representor port name. */
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uint64_t switch_id; /**< Switch identifier. */
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};
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2019-02-21 09:29:14 +00:00
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LIST_HEAD(mlx5_dev_list, mlx5_priv);
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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2019-04-01 21:12:55 +00:00
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/* Shared data between primary and secondary processes. */
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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struct mlx5_shared_data {
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2019-04-01 21:12:55 +00:00
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rte_spinlock_t lock;
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/* Global spinlock for primary and secondary processes. */
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int init_done; /* Whether primary has done initialization. */
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unsigned int secondary_cnt; /* Number of secondary processes init'd. */
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void *uar_base;
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/* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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struct mlx5_dev_list mem_event_cb_list;
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rte_rwlock_t mem_event_rwlock;
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};
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2019-04-01 21:12:55 +00:00
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/* Per-process data structure, not visible to other processes. */
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struct mlx5_local_data {
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int init_done; /* Whether a secondary has done initialization. */
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void *uar_base;
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/* Reserved UAR address space for TXQ UAR(hw doorbell) mapping. */
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};
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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extern struct mlx5_shared_data *mlx5_shared_data;
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2018-09-17 09:46:34 +00:00
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struct mlx5_counter_ctrl {
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/* Name of the counter. */
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char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
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|
|
/* Name of the counter on the device table. */
|
|
|
|
|
char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
|
|
|
|
|
uint32_t ib:1; /**< Nonzero for IB counters. */
|
|
|
|
|
};
|
|
|
|
|
|
2017-01-17 14:37:08 +00:00
|
|
|
struct mlx5_xstats_ctrl {
|
|
|
|
|
/* Number of device stats. */
|
|
|
|
|
uint16_t stats_n;
|
2018-09-17 09:46:34 +00:00
|
|
|
/* Number of device stats identified by PMD. */
|
|
|
|
|
uint16_t mlx5_stats_n;
|
2017-01-17 14:37:08 +00:00
|
|
|
/* Index in the device counters table. */
|
|
|
|
|
uint16_t dev_table_idx[MLX5_MAX_XSTATS];
|
|
|
|
|
uint64_t base[MLX5_MAX_XSTATS];
|
2018-09-17 09:46:34 +00:00
|
|
|
struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
|
2017-01-17 14:37:08 +00:00
|
|
|
};
|
|
|
|
|
|
2018-11-23 08:03:37 +00:00
|
|
|
struct mlx5_stats_ctrl {
|
|
|
|
|
/* Base for imissed counter. */
|
|
|
|
|
uint64_t imissed_base;
|
|
|
|
|
};
|
|
|
|
|
|
2019-01-03 15:06:37 +00:00
|
|
|
/* devx counter object */
|
|
|
|
|
struct mlx5_devx_counter_set {
|
|
|
|
|
struct mlx5dv_devx_obj *obj;
|
|
|
|
|
int id; /* Flow counter ID */
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-09 14:44:53 +00:00
|
|
|
/* Flow list . */
|
|
|
|
|
TAILQ_HEAD(mlx5_flows, rte_flow);
|
|
|
|
|
|
2018-01-10 09:16:58 +00:00
|
|
|
/* Default PMD specific parameter value. */
|
|
|
|
|
#define MLX5_ARG_UNSET (-1)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Device configuration structure.
|
|
|
|
|
*
|
|
|
|
|
* Merged configuration from:
|
|
|
|
|
*
|
|
|
|
|
* - Device capabilities,
|
|
|
|
|
* - User device parameters disabled features.
|
|
|
|
|
*/
|
|
|
|
|
struct mlx5_dev_config {
|
|
|
|
|
unsigned int hw_csum:1; /* Checksum offload is supported. */
|
|
|
|
|
unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
|
|
|
|
|
unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
|
|
|
|
|
unsigned int hw_padding:1; /* End alignment padding is supported. */
|
2018-04-05 15:07:19 +00:00
|
|
|
unsigned int vf:1; /* This is a VF. */
|
2018-02-25 07:28:37 +00:00
|
|
|
unsigned int tunnel_en:1;
|
|
|
|
|
/* Whether tunnel stateless offloads are supported. */
|
2018-05-15 11:07:14 +00:00
|
|
|
unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int cqe_comp:1; /* CQE compression is enabled. */
|
2018-10-25 06:24:00 +00:00
|
|
|
unsigned int cqe_pad:1; /* CQE padding is enabled. */
|
2018-01-10 09:17:00 +00:00
|
|
|
unsigned int tso:1; /* Whether TSO is supported. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int tx_vec_en:1; /* Tx vector is enabled. */
|
|
|
|
|
unsigned int rx_vec_en:1; /* Rx vector is enabled. */
|
|
|
|
|
unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
|
2019-04-01 21:17:54 +00:00
|
|
|
unsigned int mr_ext_memseg_en:1;
|
|
|
|
|
/* Whether memseg should be extended for MR creation. */
|
2018-04-23 12:33:02 +00:00
|
|
|
unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
|
2018-04-05 15:07:21 +00:00
|
|
|
unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
|
2018-09-24 23:17:54 +00:00
|
|
|
unsigned int dv_flow_en:1; /* Enable DV flow. */
|
2018-04-08 12:41:20 +00:00
|
|
|
unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
|
2019-01-03 15:06:37 +00:00
|
|
|
unsigned int devx:1; /* Whether devx interface is available or not. */
|
2018-05-09 11:13:50 +00:00
|
|
|
struct {
|
|
|
|
|
unsigned int enabled:1; /* Whether MPRQ is enabled. */
|
|
|
|
|
unsigned int stride_num_n; /* Number of strides. */
|
|
|
|
|
unsigned int min_stride_size_n; /* Min size of a stride. */
|
|
|
|
|
unsigned int max_stride_size_n; /* Max size of a stride. */
|
|
|
|
|
unsigned int max_memcpy_len;
|
|
|
|
|
/* Maximum packet size to memcpy Rx packets. */
|
|
|
|
|
unsigned int min_rxqs_num;
|
|
|
|
|
/* Rx queue count threshold to enable MPRQ. */
|
|
|
|
|
} mprq; /* Configurations for Multi-Packet RQ. */
|
2018-08-13 06:47:57 +00:00
|
|
|
int mps; /* Multi-packet send supported mode. */
|
2018-07-12 09:30:49 +00:00
|
|
|
unsigned int flow_prio; /* Number of flow priorities. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
|
|
|
|
|
unsigned int ind_table_max_size; /* Maximum indirection table size. */
|
|
|
|
|
int txq_inline; /* Maximum packet size for inlining. */
|
|
|
|
|
int txqs_inline; /* Queue number threshold for inlining. */
|
2018-11-01 17:20:32 +00:00
|
|
|
int txqs_vec; /* Queue number threshold for vectorized Tx. */
|
2018-01-10 09:16:58 +00:00
|
|
|
int inline_max_packet_sz; /* Max packet size for inlining. */
|
|
|
|
|
};
|
|
|
|
|
|
2018-01-22 12:33:38 +00:00
|
|
|
/**
|
|
|
|
|
* Type of objet being allocated.
|
|
|
|
|
*/
|
|
|
|
|
enum mlx5_verbs_alloc_type {
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_NONE,
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
|
|
|
|
|
MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Verbs allocator needs a context to know in the callback which kind of
|
|
|
|
|
* resources it is allocating.
|
|
|
|
|
*/
|
|
|
|
|
struct mlx5_verbs_alloc_ctx {
|
|
|
|
|
enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
|
|
|
|
|
const void *obj; /* Pointer to the DPDK object. */
|
|
|
|
|
};
|
|
|
|
|
|
net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
|
|
|
LIST_HEAD(mlx5_mr_list, mlx5_mr);
|
|
|
|
|
|
2018-07-12 09:30:48 +00:00
|
|
|
/* Flow drop context necessary due to Verbs API. */
|
|
|
|
|
struct mlx5_drop {
|
|
|
|
|
struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
|
|
|
|
|
struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
|
|
|
|
|
};
|
|
|
|
|
|
2018-10-18 18:29:20 +00:00
|
|
|
struct mlx5_flow_tcf_context;
|
2018-07-13 09:40:37 +00:00
|
|
|
|
2019-03-27 13:15:39 +00:00
|
|
|
/* Per port data of shared IB device. */
|
|
|
|
|
struct mlx5_ibv_shared_port {
|
|
|
|
|
uint32_t ih_port_id;
|
|
|
|
|
/*
|
|
|
|
|
* Interrupt handler port_id. Used by shared interrupt
|
|
|
|
|
* handler to find the corresponding rte_eth device
|
|
|
|
|
* by IB port index. If value is equal or greater
|
|
|
|
|
* RTE_MAX_ETHPORTS it means there is no subhandler
|
|
|
|
|
* installed for specified IB port index.
|
|
|
|
|
*/
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Shared Infiniband device context for Master/Representors
|
|
|
|
|
* which belong to same IB device with multiple IB ports.
|
|
|
|
|
**/
|
|
|
|
|
struct mlx5_ibv_shared {
|
|
|
|
|
LIST_ENTRY(mlx5_ibv_shared) next;
|
|
|
|
|
uint32_t refcnt;
|
|
|
|
|
uint32_t devx:1; /* Opened with DV. */
|
|
|
|
|
uint32_t max_port; /* Maximal IB device port index. */
|
|
|
|
|
struct ibv_context *ctx; /* Verbs/DV context. */
|
|
|
|
|
struct ibv_pd *pd; /* Protection Domain. */
|
|
|
|
|
char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
|
|
|
|
|
char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
|
|
|
|
|
struct ibv_device_attr_ex device_attr; /* Device properties. */
|
2019-03-27 13:15:45 +00:00
|
|
|
pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
|
|
|
|
|
uint32_t intr_cnt; /* Interrupt handler reference counter. */
|
2019-03-27 13:15:39 +00:00
|
|
|
struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
|
|
|
|
|
struct mlx5_ibv_shared_port port[]; /* per device port data array. */
|
|
|
|
|
};
|
|
|
|
|
|
2019-02-21 09:29:14 +00:00
|
|
|
struct mlx5_priv {
|
|
|
|
|
LIST_ENTRY(mlx5_priv) mem_event_cb;
|
|
|
|
|
/**< Called by memory event callback. */
|
2018-05-09 11:04:50 +00:00
|
|
|
struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
|
2019-03-27 13:15:39 +00:00
|
|
|
struct mlx5_ibv_shared *sh; /* Shared IB device context. */
|
|
|
|
|
uint32_t ibv_port; /* IB device port number. */
|
2017-10-09 14:44:55 +00:00
|
|
|
struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
|
2018-04-05 15:07:19 +00:00
|
|
|
BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
|
|
|
|
|
/* Bit-field of MAC addresses owned by the PMD. */
|
2015-10-30 18:52:40 +00:00
|
|
|
uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
|
|
|
|
|
unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
|
2015-10-30 18:52:30 +00:00
|
|
|
/* Device properties. */
|
|
|
|
|
uint16_t mtu; /* Configured MTU. */
|
2017-05-24 13:44:08 +00:00
|
|
|
unsigned int isolated:1; /* Whether isolated mode is enabled. */
|
2018-07-10 16:04:54 +00:00
|
|
|
unsigned int representor:1; /* Device is a port representor. */
|
2019-03-27 13:15:35 +00:00
|
|
|
unsigned int master:1; /* Device is a E-Switch master. */
|
2018-07-10 16:04:54 +00:00
|
|
|
uint16_t domain_id; /* Switch domain identifier. */
|
2019-03-27 13:15:35 +00:00
|
|
|
uint16_t vport_id; /* Associated VF vport index (if any). */
|
2018-07-10 16:04:54 +00:00
|
|
|
int32_t representor_id; /* Port representor identifier. */
|
2015-10-30 18:52:31 +00:00
|
|
|
/* RX/TX queues. */
|
|
|
|
|
unsigned int rxqs_n; /* RX queues array size. */
|
|
|
|
|
unsigned int txqs_n; /* TX queues array size. */
|
2017-10-09 14:44:39 +00:00
|
|
|
struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
|
2017-10-09 14:44:40 +00:00
|
|
|
struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
|
2018-05-09 11:13:50 +00:00
|
|
|
struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
|
2017-10-09 14:44:56 +00:00
|
|
|
struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
|
2015-11-02 18:11:57 +00:00
|
|
|
unsigned int (*reta_idx)[]; /* RETA index table. */
|
|
|
|
|
unsigned int reta_idx_n; /* RETA index size. */
|
2018-07-12 09:30:48 +00:00
|
|
|
struct mlx5_drop drop_queue; /* Flow drop queues. */
|
2017-10-09 14:44:53 +00:00
|
|
|
struct mlx5_flows flows; /* RTE Flow rules. */
|
|
|
|
|
struct mlx5_flows ctrl_flows; /* Control flow rules. */
|
2018-07-12 09:31:07 +00:00
|
|
|
LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
|
|
|
|
|
/* Flow counters. */
|
net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
|
|
|
struct {
|
|
|
|
|
uint32_t dev_gen; /* Generation number to flush local caches. */
|
|
|
|
|
rte_rwlock_t rwlock; /* MR Lock. */
|
|
|
|
|
struct mlx5_mr_btree cache; /* Global MR cache table. */
|
|
|
|
|
struct mlx5_mr_list mr_list; /* Registered MR list. */
|
|
|
|
|
struct mlx5_mr_list mr_free_list; /* Freed MR list. */
|
|
|
|
|
} mr;
|
2017-10-09 14:44:49 +00:00
|
|
|
LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
|
2017-10-09 14:44:46 +00:00
|
|
|
LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
|
2017-10-09 14:44:51 +00:00
|
|
|
LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
|
2017-10-09 14:44:48 +00:00
|
|
|
LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
|
2017-10-09 14:44:47 +00:00
|
|
|
LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
|
2017-10-09 14:44:50 +00:00
|
|
|
/* Verbs Indirection tables. */
|
|
|
|
|
LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
|
2018-09-24 23:17:45 +00:00
|
|
|
LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
|
2018-11-01 09:37:33 +00:00
|
|
|
LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
|
2018-12-27 11:09:38 +00:00
|
|
|
LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
|
2016-10-26 09:44:01 +00:00
|
|
|
uint32_t link_speed_capa; /* Link speed capabilities. */
|
2017-01-17 14:37:08 +00:00
|
|
|
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
|
2018-11-23 08:03:37 +00:00
|
|
|
struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
|
2018-01-10 09:16:58 +00:00
|
|
|
struct mlx5_dev_config config; /* Device configuration. */
|
2018-01-22 12:33:38 +00:00
|
|
|
struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
|
|
|
|
|
/* Context for Verbs allocator. */
|
2018-07-10 16:04:52 +00:00
|
|
|
int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
|
|
|
|
|
int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
|
2018-04-05 15:07:19 +00:00
|
|
|
uint32_t nl_sn; /* Netlink message sequence number. */
|
2018-07-12 12:01:31 +00:00
|
|
|
#ifndef RTE_ARCH_64
|
|
|
|
|
rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
|
|
|
|
|
rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
|
|
|
|
|
/* UAR same-page access control required in 32bit implementations. */
|
|
|
|
|
#endif
|
2018-10-18 18:29:20 +00:00
|
|
|
struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
|
2015-10-30 18:52:30 +00:00
|
|
|
};
|
|
|
|
|
|
2018-05-09 11:04:50 +00:00
|
|
|
#define PORT_ID(priv) ((priv)->dev_data->port_id)
|
|
|
|
|
#define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
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|
|
|
|
|
2016-03-17 15:38:57 +00:00
|
|
|
/* mlx5.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_getenv_int(const char *);
|
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/* mlx5_ethdev.c */
|
|
|
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|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
|
2018-07-25 11:24:33 +00:00
|
|
|
unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
|
2018-10-08 06:28:17 +00:00
|
|
|
int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
|
|
|
|
|
int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
|
|
|
|
|
unsigned int flags);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_configure(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
|
2019-02-06 22:25:19 +00:00
|
|
|
int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
|
2016-03-14 20:50:50 +00:00
|
|
|
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
|
|
|
|
|
int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_fc_conf *fc_conf);
|
|
|
|
|
int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_fc_conf *fc_conf);
|
|
|
|
|
int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
|
|
|
|
|
struct rte_pci_addr *pci_addr);
|
|
|
|
|
void mlx5_dev_link_status_handler(void *arg);
|
2018-03-05 12:21:04 +00:00
|
|
|
void mlx5_dev_interrupt_handler(void *arg);
|
|
|
|
|
void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
|
2016-03-17 15:38:54 +00:00
|
|
|
int mlx5_set_link_down(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_set_link_up(struct rte_eth_dev *dev);
|
2018-01-20 21:12:21 +00:00
|
|
|
int mlx5_is_removed(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
|
|
|
|
|
eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
|
2018-07-10 16:04:54 +00:00
|
|
|
unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
|
|
|
|
|
uint16_t *port_list,
|
|
|
|
|
unsigned int port_list_n);
|
2018-07-24 08:36:45 +00:00
|
|
|
int mlx5_sysfs_switch_info(unsigned int ifindex,
|
|
|
|
|
struct mlx5_switch_info *info);
|
2019-03-17 06:23:03 +00:00
|
|
|
bool mlx5_translate_port_name(const char *port_name_in,
|
|
|
|
|
struct mlx5_switch_info *port_info_out);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
|
|
|
|
/* mlx5_mac.c */
|
|
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
|
2018-03-05 12:20:58 +00:00
|
|
|
void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
|
|
|
|
|
int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
|
|
|
|
|
uint32_t index, uint32_t vmdq);
|
2018-04-11 16:32:51 +00:00
|
|
|
int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
|
2018-04-23 11:09:28 +00:00
|
|
|
int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
|
|
|
|
|
struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
2015-10-30 18:55:11 +00:00
|
|
|
/* mlx5_rss.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_rss_hash_update(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_conf *rss_conf);
|
|
|
|
|
int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_conf *rss_conf);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
|
|
|
uint16_t reta_size);
|
|
|
|
|
int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *reta_conf,
|
|
|
|
|
uint16_t reta_size);
|
2015-10-30 18:55:11 +00:00
|
|
|
|
2015-10-30 18:52:37 +00:00
|
|
|
/* mlx5_rxmode.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
|
2015-10-30 18:52:37 +00:00
|
|
|
|
2015-10-30 18:52:36 +00:00
|
|
|
/* mlx5_stats.c */
|
|
|
|
|
|
2018-11-23 08:03:37 +00:00
|
|
|
void mlx5_stats_init(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
|
|
|
|
|
void mlx5_stats_reset(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
|
|
|
|
|
unsigned int n);
|
2018-03-05 12:20:58 +00:00
|
|
|
void mlx5_xstats_reset(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
|
2018-03-05 12:20:58 +00:00
|
|
|
struct rte_eth_xstat_name *xstats_names,
|
|
|
|
|
unsigned int n);
|
2015-10-30 18:52:36 +00:00
|
|
|
|
2015-10-30 18:52:40 +00:00
|
|
|
/* mlx5_vlan.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
|
|
|
|
|
void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
|
|
|
|
|
int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
|
2015-10-30 18:52:40 +00:00
|
|
|
|
2015-10-30 18:52:33 +00:00
|
|
|
/* mlx5_trigger.c */
|
|
|
|
|
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_dev_start(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_dev_stop(struct rte_eth_dev *dev);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_traffic_enable(struct rte_eth_dev *dev);
|
2018-03-05 12:21:05 +00:00
|
|
|
void mlx5_traffic_disable(struct rte_eth_dev *dev);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_traffic_restart(struct rte_eth_dev *dev);
|
2015-10-30 18:52:33 +00:00
|
|
|
|
2017-10-09 14:44:38 +00:00
|
|
|
/* mlx5_flow.c */
|
2016-03-03 14:26:43 +00:00
|
|
|
|
2018-07-12 09:30:49 +00:00
|
|
|
int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
|
2018-07-12 09:30:48 +00:00
|
|
|
void mlx5_flow_print(struct rte_flow *flow);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_flow_validate(struct rte_eth_dev *dev,
|
|
|
|
|
const struct rte_flow_attr *attr,
|
|
|
|
|
const struct rte_flow_item items[],
|
|
|
|
|
const struct rte_flow_action actions[],
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
|
|
|
|
|
const struct rte_flow_attr *attr,
|
|
|
|
|
const struct rte_flow_item items[],
|
|
|
|
|
const struct rte_flow_action actions[],
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
|
|
|
|
|
struct rte_flow_error *error);
|
2018-03-05 12:21:04 +00:00
|
|
|
void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
|
2018-03-05 12:20:58 +00:00
|
|
|
int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
|
2018-04-26 17:29:19 +00:00
|
|
|
const struct rte_flow_action *action, void *data,
|
2018-03-05 12:20:58 +00:00
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
|
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
|
|
|
|
|
enum rte_filter_type filter_type,
|
|
|
|
|
enum rte_filter_op filter_op,
|
|
|
|
|
void *arg);
|
2018-03-05 12:21:04 +00:00
|
|
|
int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
|
|
|
|
|
void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
|
|
|
|
|
int mlx5_flow_verify(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_flow_item_eth *eth_spec,
|
|
|
|
|
struct rte_flow_item_eth *eth_mask,
|
|
|
|
|
struct rte_flow_item_vlan *vlan_spec,
|
|
|
|
|
struct rte_flow_item_vlan *vlan_mask);
|
|
|
|
|
int mlx5_ctrl_flow(struct rte_eth_dev *dev,
|
|
|
|
|
struct rte_flow_item_eth *eth_spec,
|
|
|
|
|
struct rte_flow_item_eth *eth_mask);
|
|
|
|
|
int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
|
2016-12-29 15:15:17 +00:00
|
|
|
|
2019-04-01 21:12:54 +00:00
|
|
|
/* mlx5_mp.c */
|
2019-04-01 21:12:56 +00:00
|
|
|
void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
|
2019-04-01 21:12:54 +00:00
|
|
|
int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
|
2019-04-01 21:12:55 +00:00
|
|
|
void mlx5_mp_init_primary(void);
|
|
|
|
|
void mlx5_mp_uninit_primary(void);
|
2019-04-01 21:12:56 +00:00
|
|
|
void mlx5_mp_init_secondary(void);
|
|
|
|
|
void mlx5_mp_uninit_secondary(void);
|
2017-10-06 15:45:49 +00:00
|
|
|
|
2018-04-05 15:07:19 +00:00
|
|
|
/* mlx5_nl.c */
|
|
|
|
|
|
2018-07-24 06:50:27 +00:00
|
|
|
int mlx5_nl_init(int protocol);
|
2018-04-05 15:07:19 +00:00
|
|
|
int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
|
|
|
|
|
uint32_t index);
|
|
|
|
|
int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
|
|
|
|
|
uint32_t index);
|
|
|
|
|
void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
|
|
|
|
|
void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
|
2018-04-05 15:07:20 +00:00
|
|
|
int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
|
|
|
|
|
int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
|
2019-03-27 13:15:37 +00:00
|
|
|
unsigned int mlx5_nl_portnum(int nl, const char *name);
|
2019-03-27 13:15:36 +00:00
|
|
|
unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
|
2018-07-10 16:04:52 +00:00
|
|
|
int mlx5_nl_switch_info(int nl, unsigned int ifindex,
|
|
|
|
|
struct mlx5_switch_info *info);
|
2018-04-05 15:07:19 +00:00
|
|
|
|
2019-01-03 15:06:37 +00:00
|
|
|
/* mlx5_devx_cmds.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
|
|
|
|
|
struct mlx5_devx_counter_set *dcx);
|
|
|
|
|
int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
|
|
|
|
|
int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
|
|
|
|
|
int clear,
|
|
|
|
|
uint64_t *pkts, uint64_t *bytes);
|
2015-10-30 18:52:30 +00:00
|
|
|
#endif /* RTE_PMD_MLX5_H_ */
|
